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radeonsi: si_emit_buffered_compute_sh_regs support gang cs

Browse source 
To be used by task shader gang cs.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38044>
This commit is contained in:
Qiang Yu 2025-07-02 16:58:28 +08:00 • committed by Marge Bot
parent b713f453c6
commit 355e499b52
3 changed files with 14 additions and 11 deletions
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2
src/gallium/drivers/radeonsi/si_compute.c
View file

@ -805,7 +805,7 @@ static void si_emit_dispatch_packets(struct si_context *sctx, const struct pipe_
if (sctx->gfx_level >= GFX12 || sctx->screen->info.has_set_sh_pairs_packed) {
radeon_end();
si_emit_buffered_compute_sh_regs(sctx);
si_emit_buffered_compute_sh_regs(sctx, cs);
radeon_begin_again(cs);
}

2
src/gallium/drivers/radeonsi/si_state.h
View file

@ -699,7 +699,7 @@ void si_cp_dma_prefetch(struct radeon_cmdbuf *cs,
void si_set_vertex_buffer_descriptor(struct si_screen *sscreen, struct si_vertex_elements *velems,
const struct pipe_vertex_buffer *vb, unsigned element_index,
uint32_t *out);
void si_emit_buffered_compute_sh_regs(struct si_context *sctx);
void si_emit_buffered_compute_sh_regs(struct si_context *sctx, struct radeon_cmdbuf *cs);
void si_emit_buffered_gfx_sh_regs_for_mesh(struct si_context *sctx);
void si_init_draw_functions_GFX6(struct si_context *sctx);
void si_init_draw_functions_GFX7(struct si_context *sctx);

21
src/gallium/drivers/radeonsi/si_state_draw.cpp
View file

@ -1208,7 +1208,9 @@ static void si_emit_draw_registers(struct si_context *sctx,
}
static ALWAYS_INLINE void
gfx11_emit_buffered_sh_regs_inline(struct si_context *sctx, unsigned *num_regs,
gfx11_emit_buffered_sh_regs_inline(struct si_context *sctx,
struct radeon_cmdbuf *cs,
unsigned *num_regs,
struct ac_gfx11_reg_pair *reg_pairs)
{
unsigned reg_count = *num_regs;
@ -1220,7 +1222,7 @@ gfx11_emit_buffered_sh_regs_inline(struct si_context *sctx, unsigned *num_regs,
/* If there is only one register, we can't use the packed SET packet. */
if (reg_count == 1) {
radeon_begin(&sctx->gfx_cs);
radeon_begin(cs);
radeon_emit(PKT3(PKT3_SET_SH_REG, 1, 0));
radeon_emit(reg_pairs[0].reg_offset[0]);
radeon_emit(reg_pairs[0].reg_value[0]);
@ -1232,7 +1234,7 @@ gfx11_emit_buffered_sh_regs_inline(struct si_context *sctx, unsigned *num_regs,
PKT3_SET_SH_REG_PAIRS_PACKED;
unsigned padded_reg_count = align(reg_count, 2);
radeon_begin(&sctx->gfx_cs);
radeon_begin(cs);
radeon_emit(PKT3(packet, (padded_reg_count / 2) * 3, 0) | PKT3_RESET_FILTER_CAM_S(1));
radeon_emit(padded_reg_count);
radeon_emit_array(reg_pairs, (reg_count / 2) * 3);
@ -1261,15 +1263,15 @@ gfx11_emit_buffered_sh_regs_inline(struct si_context *sctx, unsigned *num_regs,
#if GFX_VER == 6 /* declare this function only once because there is only one variant. */
void si_emit_buffered_compute_sh_regs(struct si_context *sctx)
void si_emit_buffered_compute_sh_regs(struct si_context *sctx, struct radeon_cmdbuf *cs)
{
if (sctx->gfx_level >= GFX12) {
radeon_begin(&sctx->gfx_cs);
radeon_begin(cs);
gfx12_emit_buffered_sh_regs_inline(&sctx->buffered_compute_sh_regs.num,
sctx->buffered_compute_sh_regs.gfx12.regs);
radeon_end();
} else {
gfx11_emit_buffered_sh_regs_inline(sctx, &sctx->buffered_compute_sh_regs.num,
gfx11_emit_buffered_sh_regs_inline(sctx, cs, &sctx->buffered_compute_sh_regs.num,
sctx->buffered_compute_sh_regs.gfx11.regs);
}
}
@ -1283,7 +1285,8 @@ void si_emit_buffered_gfx_sh_regs_for_mesh(struct si_context *sctx)
sctx->buffered_gfx_sh_regs.gfx12.regs);
radeon_end();
} else {
gfx11_emit_buffered_sh_regs_inline(sctx, &sctx->buffered_gfx_sh_regs.num,
gfx11_emit_buffered_sh_regs_inline(sctx, &sctx->gfx_cs,
&sctx->buffered_gfx_sh_regs.num,
sctx->buffered_gfx_sh_regs.gfx11.regs);
}
}
@ -1441,7 +1444,7 @@ static void si_emit_draw_packets(struct si_context *sctx, const struct pipe_draw
sctx->buffered_gfx_sh_regs.gfx12.regs);
} else if (HAS_SH_PAIRS_PACKED) {
radeon_end();
gfx11_emit_buffered_sh_regs_inline(sctx, &sctx->buffered_gfx_sh_regs.num,
gfx11_emit_buffered_sh_regs_inline(sctx, cs, &sctx->buffered_gfx_sh_regs.num,
sctx->buffered_gfx_sh_regs.gfx11.regs);
radeon_begin_again(cs);
}
@ -1569,7 +1572,7 @@ static void si_emit_draw_packets(struct si_context *sctx, const struct pipe_draw
sctx->buffered_gfx_sh_regs.gfx12.regs);
} else if (HAS_SH_PAIRS_PACKED) {
radeon_end();
gfx11_emit_buffered_sh_regs_inline(sctx, &sctx->buffered_gfx_sh_regs.num,
gfx11_emit_buffered_sh_regs_inline(sctx, cs, &sctx->buffered_gfx_sh_regs.num,
sctx->buffered_gfx_sh_regs.gfx11.regs);
radeon_begin_again(cs);
}