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Author SHA1 Message Date
Gert Wollny
ca5bbff558 r600/sfn: Fix readport check 
We have to take multi-slot instructions into account, and we don't fail
when there are still possible bank swizzle values to be checked.

For clarity also rename the bank swizzle iterator iterator.

Fixes: 79ca456b48
   r600/sfn: rewrite NIR backend

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20739>
 2023-01-17 19:19:01 +00:00
Rhys Perry
42d51ef2bb radv/gfx11: expose shaderBufferFloat32AtomicAdd 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19810>
 2023-01-17 17:39:15 +00:00
Rhys Perry
7dd16791ca radv: load ssbo_atomic_fadd descriptor 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19810>
 2023-01-17 17:39:15 +00:00
Rhys Perry
068c84f275 aco: add support for fp32 addition atomics 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19810>
 2023-01-17 17:39:15 +00:00
Rhys Perry
ea1ac3901a ac/llvm: add support for fp32 addition atomics 
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19810>
 2023-01-17 17:39:15 +00:00
José Roberto de Souza
e879b28994 anv: Move anv_device_check_status() code to i915/anv_device.c 
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Rohan Garg <rohan.garg@intel.com>
Acked-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20428>
 2023-01-17 17:10:18 +00:00
José Roberto de Souza
94af444490 anv: Split i915 code from anv_batch_chain.c 
There is no change in behavior here.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Rohan Garg <rohan.garg@intel.com>
Acked-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20428>
 2023-01-17 17:10:18 +00:00
José Roberto de Souza
94ca73b356 anv: Export anv_exec_batch_debug() and chain_command_buffers() 
This functions will be used by i915 and Xe KMD.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Rohan Garg <rohan.garg@intel.com>
Acked-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20428>
 2023-01-17 17:10:18 +00:00
José Roberto de Souza
80c89c4606 anv: Start to move i915 specific code from anv_device to i915/anv_device 
More code re-organization to separate i915_drm.h specific code from
the rest.

No behavior changes here.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Rohan Garg <rohan.garg@intel.com>
Acked-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20428>
 2023-01-17 17:10:18 +00:00
Gert Wollny
8084b412ca virgl: drop the separable flag for cases that can't be handled 
The host can't assign more than 32 locations explicitly, and we
exhaust this already when we handle patches and generics. So
drop the separable flag in cases when we have other IO that
uses generated names that will have to be matched by name.

v2: skip tests for VS input and FS outputs

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20738>
 2023-01-17 16:58:52 +00:00
Rob Clark
aa7c83786d freedreno/ci: Add an a618 flake 
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20749>
 2023-01-17 16:33:29 +00:00
Rob Clark
a7a46556ec Revert "freedreno/ci: Switch a630 jobs over to manual" 
This reverts commit 0cc3701338.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20749>
 2023-01-17 16:33:29 +00:00
Rob Clark
23e6d0ce79 Revert "freedreno/ci: Switch also performance a630 job to manual" 
This reverts commit 3be7a28b24.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20749>
 2023-01-17 16:33:29 +00:00
Lionel Landwerlin
f9115b6d51 intel: use a shared UUID with other drivers 
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20408>
 2023-01-17 17:36:07 +02:00
Tapani Pälli
53de48f1c4 intel/compiler: add cpp_std=c++17 when building tests 
Otherwise build fails:

"../src/intel/compiler/brw_private.h:40:4: note:
 ‘std::variant’ is only available from C++17 onwards"

Fixes: 6c194ddd18 ("intel/compiler: Prepare SIMD selection helpers to handle different prog_datas")
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20725>
 2023-01-17 13:58:03 +00:00
Gert Wollny
d59e5aa08f virgl: Request setting the atomic offset in the range_base 
With that NTT can encode the array base of atomic arrays separately
so that the host driver can address the arrays correctly.

Fixes GL-CTS: KHR-Single-GL43.arrays_of_arrays_gl.AtomicUsage

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19980>
 2023-01-17 13:19:04 +00:00
Gert Wollny
994cf0e995 virgl: lower image variable offsets into the intrinsic range_base value 
With that we get the correct base offset when accessing image arrays.
This is required if there a various images with different access
specifiers, because only with the correct base offset the host driver is
able to pick the right array.

Fixes GL-CTS: KHR-GL43.shading_language_420pack.binding_image_array

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19980>
 2023-01-17 13:19:04 +00:00
Gert Wollny
7380656a8c ntt: Make use of the range_base offset when translating atomics in NTT 
v2: Unconditionally add teh range base, it is properly initialized.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19980>
 2023-01-17 13:19:04 +00:00
Gert Wollny
36f19058ae ntt: handle the image intrinsic range_base when translating to TGSI 
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19980>
 2023-01-17 13:19:04 +00:00
Gert Wollny
2e05cfa179 nir: Add range_base to atomic_counter and an option to use it 
Some drivers may encode constant offsets in the instruction, so
make it possible for the drivers to request lowering the atomic
uniform offset into the range_base variable of the intrinsic.

v2: drop patch to use build-in array offset evaluation, it makes
    problems with zink, and update the code accordingly
v3: always initialize range base

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19980>
 2023-01-17 13:19:04 +00:00
Gert Wollny
c4cde91c1b nir: Add possibility to store image var offset in range_base 
Add the intrinsic range_base value to the image intrinsics and add
the option to store the image array offset into range_base instead
of adding it to the image array index if the driver requests it.

v2: Always initialize range_base

v3: fix for bindless intrinsics

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19980>
 2023-01-17 13:19:04 +00:00
Jesse Natalie
2f4c7b5ccf dzn: Use typeless format for creation of depth-only or stencil-only D24S8 
When querying capabilities or creating views using a scoped aspect
mask, we want to return the format for the correct single-channel
format, but when actually creating the resource (aspect mask 0),
we want to use the typeless format, since the single-channel formats
don't report multisampling support.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20614>
 2023-01-17 12:47:16 +00:00
Jesse Natalie
9f928adf81 dzn: Set MultisampleEnable to enable MSAA lines 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20614>
 2023-01-17 12:47:16 +00:00
Jesse Natalie
ca20577622 dzn: Storage buffer sizes need to be 4-byte-aligned 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20614>
 2023-01-17 12:47:16 +00:00
Jesse Natalie
b948a5db4f dzn: Support int border colors 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20614>
 2023-01-17 12:47:16 +00:00
Jesse Natalie
10282bbd96 dzn: Use R24G8_TYPELESS for 24/8 depth resources 
This is the same that was already being done for R32G8X24, not sure
why it was missed for R24G8.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20614>
 2023-01-17 12:47:16 +00:00
Jesse Natalie
a3005ecb56 dzn: When changing root signature, dirty descriptors too 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20614>
 2023-01-17 12:47:16 +00:00
Jesse Natalie
14f0c85874 dzn: Support alpha blend factor 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20614>
 2023-01-17 12:47:16 +00:00
Jesse Natalie
aa3fc8753d dzn: Get options13 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20614>
 2023-01-17 12:47:16 +00:00
Jesse Natalie
22eb9b1c12 spirv2dxil: Replace not-provided inputs with zero instead of undef 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20614>
 2023-01-17 12:47:16 +00:00
Jesse Natalie
61c391781e spirv2dxil: Allow killing position as an undef varying 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20614>
 2023-01-17 12:47:16 +00:00
Jesse Natalie
3ddf41cb7d spirv2dxil: When removing unused inputs, make sure they're actually inputs 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20614>
 2023-01-17 12:47:16 +00:00
Jesse Natalie
00b9c10cf7 spirv2dxil: For removing unused vars, consider the whole I/O var size 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20614>
 2023-01-17 12:47:16 +00:00
Jesse Natalie
85f44304d8 microsoft/compiler: Set num_components to 4 when updating pos write instructions 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20614>
 2023-01-17 12:47:16 +00:00
Jesse Natalie
5d8e89f92f microsoft/compiler: Use nir info.fs.uses_sample_shading to force sample-rate 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20614>
 2023-01-17 12:47:16 +00:00
Jesse Natalie
cbc481f39f microsoft/compiler: Re-work the logic for adding SV_SampleIndex to force sample-rate 
Only add SV_SampleIndex if there exists a sample-rate var that has either flat
interpolation or centroid (and therefore can't force sample rate implicitly),
unless there is also a sample-rate var that doesn't have those properties.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20614>
 2023-01-17 12:47:16 +00:00
Jesse Natalie
b151ed4b95 microsoft/compiler: Always emit float types in the I/O signature for structs 
There's VK tests that have mismatching interpolation specifiers between FS
and the previous stage. For structs, that resulted in different types, which
breaks DXIL validation.

We could link the shaders and have that overwrite the interpolation field from
the previous shader, but we could also just not care and always use float.
I don't see any regressions from that.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20614>
 2023-01-17 12:47:16 +00:00
Jesse Natalie
c1a3d6b9a9 microsoft/compiler: Remove arrays when testing for structs in I/O 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20614>
 2023-01-17 12:47:16 +00:00
Jesse Natalie
c86bd4bfbc microsoft/compiler: Implement texture sample count query 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20614>
 2023-01-17 12:47:16 +00:00
Jesse Natalie
47481e8151 microsoft/compiler: Lower pack_[u/s]norm_2x16 
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20614>
 2023-01-17 12:47:16 +00:00
Simon Fels
4a0aeae371 virgl/vtest: allow socket being specified by env variable 
Signed-off-by: Simon Fels <simon.fels@canonical.com>
Reviewed-by: Corentin Noël <corentin.noel@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20736>
 2023-01-17 12:02:38 +00:00
Simon Fels
501309ef32 venus: allow vtest socket being specified by env variable 
Signed-off-by: Simon Fels <simon.fels@canonical.com>
Reviewed-by: Corentin Noël <corentin.noel@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20736>
 2023-01-17 12:02:38 +00:00
Illia Polishchuk
530a62ce73 hasvk: Add extra memory types for hasvk driver instead of a single one 
Replicates a fix from Anv.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Illia Polishchuk <illia.a.polishchuk@globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7360
Tested-by: Matti Hämäläinen <ccr@tnsp.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20720>
 2023-01-17 10:48:20 +00:00
Illia Polishchuk
8491b1fd5e ANV: Add extra memory types for ANV driver instead of a single one 
Some game engines can't handle single type well
And Intel on Windows uses 3 types so it's better to add extra one here

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7360
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Illia Polishchuk <illia.a.polishchuk@globallogic.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20693>
 2023-01-17 07:41:52 +00:00
Dave Airlie
83a1d56faa ci: bump vk cts to 1.3.3.1 + and a crash fix. 
With the video changes some crashes were introduced in CTS,
apply the fix.

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20629>
 2023-01-17 04:23:08 +00:00
Thong Thai
bb003d406e gallium/auxiliary/vl: clean-up progressive shader 
Add the progressive shader to the vl_compositor_cs_cleanup_shaders
function.

Signed-off-by: Thong Thai <thong.thai@amd.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8086
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8088
Tested-by: Mark Herbert <mark.herbert42@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20730>
 2023-01-16 22:48:26 +00:00
Alyssa Rosenzweig
f02354d3e2 pan/mdg: Remove MSGS debug 
These should all be unreachable and what's left is dead-code.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19350>
 2023-01-16 22:20:43 +00:00
Alyssa Rosenzweig
23968aeeb5 pan/mdg: Scalarize LUT instructions in NIR 
Simpler. Small shaderdb regressions from using IR registers instead of
SSA, but that's probably what we needed for correctness (given that SSA
is violated otherwise) hence the Cc.

total instructions in shared programs: 1520220 -> 1518127 (-0.14%)
instructions in affected programs: 167437 -> 165344 (-1.25%)
helped: 662
HURT: 206
helped stats (abs) min: 1.0 max: 46.0 x̄: 3.65 x̃: 2
helped stats (rel) min: 0.18% max: 22.22% x̄: 2.43% x̃: 1.71%
HURT stats (abs)   min: 1.0 max: 7.0 x̄: 1.56 x̃: 1
HURT stats (rel)   min: 0.17% max: 8.33% x̄: 2.66% x̃: 2.33%
95% mean confidence interval for instructions value: -2.65 -2.18
95% mean confidence interval for instructions %-change: -1.45% -0.99%
Instructions are helped.

total bundles in shared programs: 649844 -> 649345 (-0.08%)
bundles in affected programs: 59278 -> 58779 (-0.84%)
helped: 577
HURT: 249
helped stats (abs) min: 1.0 max: 39.0 x̄: 1.56 x̃: 1
helped stats (rel) min: 0.26% max: 30.00% x̄: 3.13% x̃: 2.19%
HURT stats (abs)   min: 1.0 max: 12.0 x̄: 1.61 x̃: 1
HURT stats (rel)   min: 0.58% max: 25.00% x̄: 5.25% x̃: 4.00%
95% mean confidence interval for bundles value: -0.78 -0.43
95% mean confidence interval for bundles %-change: -0.98% -0.23%
Bundles are helped.

total quadwords in shared programs: 1136767 -> 1134956 (-0.16%)
quadwords in affected programs: 141780 -> 139969 (-1.28%)
helped: 744
HURT: 311
helped stats (abs) min: 1.0 max: 9.0 x̄: 3.13 x̃: 2
helped stats (rel) min: 0.14% max: 26.67% x̄: 2.77% x̃: 2.13%
HURT stats (abs)   min: 1.0 max: 8.0 x̄: 1.68 x̃: 1
HURT stats (rel)   min: 0.35% max: 10.00% x̄: 3.17% x̃: 1.69%
95% mean confidence interval for quadwords value: -1.89 -1.54
95% mean confidence interval for quadwords %-change: -1.27% -0.77%
Quadwords are helped.

total registers in shared programs: 90461 -> 90273 (-0.21%)
registers in affected programs: 2833 -> 2645 (-6.64%)
helped: 250
HURT: 82
helped stats (abs) min: 1.0 max: 2.0 x̄: 1.08 x̃: 1
helped stats (rel) min: 6.67% max: 33.33% x̄: 14.06% x̃: 12.50%
HURT stats (abs)   min: 1.0 max: 1.0 x̄: 1.00 x̃: 1
HURT stats (rel)   min: 6.67% max: 50.00% x̄: 13.90% x̃: 12.50%
95% mean confidence interval for registers value: -0.67 -0.47
95% mean confidence interval for registers %-change: -8.62% -5.69%
Registers are helped.

total threads in shared programs: 55685 -> 55686 (<.01%)
threads in affected programs: 76 -> 77 (1.32%)
helped: 20
HURT: 17
helped stats (abs) min: 1.0 max: 2.0 x̄: 1.30 x̃: 1
helped stats (rel) min: 100.00% max: 100.00% x̄: 100.00% x̃: 100.00%
HURT stats (abs)   min: 1.0 max: 2.0 x̄: 1.47 x̃: 1
HURT stats (rel)   min: 50.00% max: 50.00% x̄: 50.00% x̃: 50.00%
95% mean confidence interval for threads value: -0.47 0.52
95% mean confidence interval for threads %-change: 5.81% 56.35%
Inconclusive result (value mean confidence interval includes 0).

total spills in shared programs: 1387 -> 1379 (-0.58%)
spills in affected programs: 283 -> 275 (-2.83%)
helped: 5
HURT: 1

total fills in shared programs: 5256 -> 5176 (-1.52%)
fills in affected programs: 557 -> 477 (-14.36%)
helped: 5
HURT: 1

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19350>
 2023-01-16 22:20:43 +00:00
Alyssa Rosenzweig
10759d1708 pan/mdg: Use special NIR ops for trig scaling 
Otherwise the lowering is fundamentally unsound due to incorrect constant
folding, even though it worked by chance with the old pass ordering. We're about
to change slightly the way we handle fsin/fcos, which was enough to trigger this
unsoundness.

shader-db results are mostly a toss-up.

total instructions in shared programs: 1520675 -> 1520220 (-0.03%)
instructions in affected programs: 96841 -> 96386 (-0.47%)
helped: 397
HURT: 3
helped stats (abs) min: 1.0 max: 4.0 x̄: 1.15 x̃: 1
helped stats (rel) min: 0.22% max: 6.25% x̄: 1.15% x̃: 0.40%
HURT stats (abs)   min: 1.0 max: 1.0 x̄: 1.00 x̃: 1
HURT stats (rel)   min: 0.58% max: 2.08% x̄: 1.08% x̃: 0.58%
95% mean confidence interval for instructions value: -1.19 -1.08
95% mean confidence interval for instructions %-change: -1.26% -1.01%
Instructions are helped.

total bundles in shared programs: 650088 -> 649844 (-0.04%)
bundles in affected programs: 31132 -> 30888 (-0.78%)
helped: 229
HURT: 23
helped stats (abs) min: 1.0 max: 4.0 x̄: 1.21 x̃: 1
helped stats (rel) min: 0.49% max: 7.14% x̄: 1.28% x̃: 0.71%
HURT stats (abs)   min: 1.0 max: 3.0 x̄: 1.48 x̃: 1
HURT stats (rel)   min: 0.83% max: 8.33% x̄: 2.38% x̃: 1.85%
95% mean confidence interval for bundles value: -1.08 -0.86
95% mean confidence interval for bundles %-change: -1.15% -0.74%
Bundles are helped.

total quadwords in shared programs: 1137388 -> 1136767 (-0.05%)
quadwords in affected programs: 71826 -> 71205 (-0.86%)
helped: 367
HURT: 17
helped stats (abs) min: 1.0 max: 8.0 x̄: 1.80 x̃: 1
helped stats (rel) min: 0.31% max: 17.24% x̄: 2.27% x̃: 0.96%
HURT stats (abs)   min: 1.0 max: 6.0 x̄: 2.29 x̃: 2
HURT stats (rel)   min: 0.44% max: 11.11% x̄: 2.18% x̃: 1.47%
95% mean confidence interval for quadwords value: -1.76 -1.47
95% mean confidence interval for quadwords %-change: -2.36% -1.78%
Quadwords are helped.

total registers in shared programs: 90483 -> 90461 (-0.02%)
registers in affected programs: 890 -> 868 (-2.47%)
helped: 67
HURT: 44
helped stats (abs) min: 1.0 max: 1.0 x̄: 1.00 x̃: 1
helped stats (rel) min: 8.33% max: 25.00% x̄: 10.52% x̃: 9.09%
HURT stats (abs)   min: 1.0 max: 2.0 x̄: 1.02 x̃: 1
HURT stats (rel)   min: 9.09% max: 50.00% x̄: 31.15% x̃: 33.33%
95% mean confidence interval for registers value: -0.39 -0.01
95% mean confidence interval for registers %-change: 1.75% 10.25%
Inconclusive result (value mean confidence interval and %-change mean confidence interval disagree).

total threads in shared programs: 55694 -> 55685 (-0.02%)
threads in affected programs: 21 -> 12 (-42.86%)
helped: 1
HURT: 5
helped stats (abs) min: 1.0 max: 1.0 x̄: 1.00 x̃: 1
helped stats (rel) min: 100.00% max: 100.00% x̄: 100.00% x̃: 100.00%
HURT stats (abs)   min: 2.0 max: 2.0 x̄: 2.00 x̃: 2
HURT stats (rel)   min: 50.00% max: 50.00% x̄: 50.00% x̃: 50.00%
95% mean confidence interval for threads value: -2.79 -0.21
95% mean confidence interval for threads %-change: -89.26% 39.26%
Inconclusive result (%-change mean confidence interval includes 0).

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19350>
 2023-01-16 22:20:43 +00:00
Alyssa Rosenzweig
c3839bd540 nir: Optimize vendored sin/cos the same way 
As we've done for the AMD one, to prevent any codegen regression from switching
the Midgard lowering.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Italo Nicola <italonicola@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19350>
 2023-01-16 22:20:43 +00:00