In amdgpu_cs.c, struct amdgpu_ib variable is named as ib which creates
confusion since struct drm_amdgpu_cs_chunk_ib is also called as ib in
some places.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26612>
preamble ib is created using amdgpu_cs_setup_preemption()
function. only IB_MAIN memory is allocated from struct amdgpu_ib.
Hence remove ib_type variable from struct amdgpu_ib.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26612>
This is not needed. validate_ir_tree() is called at the end of the
glsl ir linker and the IR is not modified again after so we can
drop this.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26628>
Perhaps it should use div_round_up() unlike normal timestamp conversion,
but this is close enough and it makes the connection to the 19.2MHz RBBM
counter more obvious.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26640>
The kernel returns the 19.2MHz RBBM counter, same as what is used for
timestamp queries. So it needs to be converted the same way.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26640>
Vulkan backend of Hades can only handle at most 3 swapchain images.
It affects all drivers after below commit:
04d654a5d0
and then only affects specific driver backend which enables
extra_xwayland_image in wsi device options after below commit:
c1a62476ac
Cc: mesa-stable
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Renato Pereyra <renatopereyra@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26607>
Once decl_reg is handled, src[0].ssa->divergent will be properly set, so
load_reg and load_reg_indirect do not need special treatment.
shader-db can run to completion on HSW, IVB, and SNB now. No other
testing was done.
v2: Refactor nir_intrinsic_load_reg and nir_intrinsic_load_reg_indirect
handling. Suggested by Daniel Schürmann.
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Fixes: 4fd257d20f ("nir: Properly handle divergence for load_reg")
Fixes: 6dbb5f1e07 ("intel/fs: rerun divergence analysis prior to convert_from_ssa")
Closes: #10233
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26436>
These are unused, and the comments about the relationships between it an
the other variants seems to be seriously outdated. Let's get rid of it.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26418>
These are hard limits and don't depend on wave size.
Accordingly, also update the usage in order to avoid
reporting unreasonable occupancy.
Totals from 192 (0.24% of 79330) affected shaders:
MaxWaves: 5814 -> 3072 (-47.16%)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26521>
vkd3d-proton requires this memory bit in various cases (adding
it to the GTT memory type significantly reduces failures in the
vkd3d-proton test suite) 🐸
I'm not sure if Tegra supports this bit though so I'm not adding it
to the VRAM-less path (hopefully someone can provide an actual answer)
The next step would be adding HOST_VISIBLE bit to the VRAM type (this
will likely require more work and maybe even some KMD changes) which
would make gamescope work (Faith said that DXVK benefits from it too)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26621>
We've copied the signature too many times already. This will also be used
more.
It intentionally deviates from the name by not including the "_vbo" part.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26619>
Currently, we have:
- cso_context_base is the base class, but cso_context is passed to functions
- cso_context is the derived class
Change:
- cso_context to become the base class, and is passed to functions
- cso_context_priv to become the derived class.
mesa/main will need to access the base class directly.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26619>
