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winsys/amdgpu: rename ib variable name to chunk_ib
rename struct drm_amdgpu_cs_chunk_ib ib variable name to chunk_ib for improving code readability. Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26612>
This commit is contained in:
Yogesh Mohan Marimuthu
Marge Bot
parent
34fba64cf6
commit
52aca8542f
2 changed files with 42 additions and 42 deletions
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@ -243,7 +243,7 @@ amdgpu_cs_get_next_fence(struct radeon_cmdbuf *rcs)
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}
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fence = amdgpu_fence_create(cs->ctx,
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cs->csc->ib[IB_MAIN].ip_type);
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cs->csc->chunk_ib[IB_MAIN].ip_type);
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if (!fence)
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return NULL;
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@ -555,12 +555,12 @@ amdgpu_ctx_query_reset_status(struct radeon_winsys_ctx *rwctx, bool full_reset_o
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static bool amdgpu_cs_has_user_fence(struct amdgpu_cs_context *cs)
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{
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return cs->ib[IB_MAIN].ip_type != AMDGPU_HW_IP_UVD &&
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cs->ib[IB_MAIN].ip_type != AMDGPU_HW_IP_VCE &&
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cs->ib[IB_MAIN].ip_type != AMDGPU_HW_IP_UVD_ENC &&
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cs->ib[IB_MAIN].ip_type != AMDGPU_HW_IP_VCN_DEC &&
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cs->ib[IB_MAIN].ip_type != AMDGPU_HW_IP_VCN_ENC &&
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cs->ib[IB_MAIN].ip_type != AMDGPU_HW_IP_VCN_JPEG;
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return cs->chunk_ib[IB_MAIN].ip_type != AMDGPU_HW_IP_UVD &&
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cs->chunk_ib[IB_MAIN].ip_type != AMDGPU_HW_IP_VCE &&
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cs->chunk_ib[IB_MAIN].ip_type != AMDGPU_HW_IP_UVD_ENC &&
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cs->chunk_ib[IB_MAIN].ip_type != AMDGPU_HW_IP_VCN_DEC &&
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cs->chunk_ib[IB_MAIN].ip_type != AMDGPU_HW_IP_VCN_ENC &&
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cs->chunk_ib[IB_MAIN].ip_type != AMDGPU_HW_IP_VCN_JPEG;
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}
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static inline unsigned amdgpu_cs_epilog_dws(struct amdgpu_cs *cs)
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@ -918,7 +918,7 @@ static bool amdgpu_get_new_ib(struct amdgpu_winsys *ws,
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* and there is less waiting for buffers and fences. Proof:
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* http://www.phoronix.com/scan.php?page=article&item=mesa-111-si&num=1
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*/
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struct drm_amdgpu_cs_chunk_ib *info = &cs->csc->ib[IB_MAIN];
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struct drm_amdgpu_cs_chunk_ib *chunk_ib = &cs->csc->chunk_ib[IB_MAIN];
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/* This is the minimum size of a contiguous IB. */
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unsigned ib_size = 4 * 1024 * 4;
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@ -947,11 +947,11 @@ static bool amdgpu_get_new_ib(struct amdgpu_winsys *ws,
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return false;
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}
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info->va_start = amdgpu_winsys_bo(main_ib->big_ib_buffer)->va + main_ib->used_ib_space;
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info->ib_bytes = 0;
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chunk_ib->va_start = amdgpu_winsys_bo(main_ib->big_ib_buffer)->va + main_ib->used_ib_space;
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chunk_ib->ib_bytes = 0;
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/* ib_bytes is in dwords and the conversion to bytes will be done before
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* the CS ioctl. */
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main_ib->ptr_ib_size = &info->ib_bytes;
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main_ib->ptr_ib_size = &chunk_ib->ib_bytes;
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main_ib->ptr_ib_size_inside_ib = false;
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amdgpu_cs_add_buffer(cs->main_ib.rcs, main_ib->big_ib_buffer,
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@ -963,7 +963,7 @@ static bool amdgpu_get_new_ib(struct amdgpu_winsys *ws,
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ib_size = main_ib->big_ib_buffer->size - main_ib->used_ib_space;
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rcs->current.max_dw = ib_size / 4 - amdgpu_cs_epilog_dws(cs);
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rcs->gpu_address = info->va_start;
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rcs->gpu_address = chunk_ib->va_start;
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return true;
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}
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@ -993,41 +993,41 @@ static bool amdgpu_init_cs_context(struct amdgpu_winsys *ws,
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{
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switch (ip_type) {
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case AMD_IP_SDMA:
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cs->ib[IB_MAIN].ip_type = AMDGPU_HW_IP_DMA;
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cs->chunk_ib[IB_MAIN].ip_type = AMDGPU_HW_IP_DMA;
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break;
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case AMD_IP_UVD:
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cs->ib[IB_MAIN].ip_type = AMDGPU_HW_IP_UVD;
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cs->chunk_ib[IB_MAIN].ip_type = AMDGPU_HW_IP_UVD;
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break;
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case AMD_IP_UVD_ENC:
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cs->ib[IB_MAIN].ip_type = AMDGPU_HW_IP_UVD_ENC;
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cs->chunk_ib[IB_MAIN].ip_type = AMDGPU_HW_IP_UVD_ENC;
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break;
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case AMD_IP_VCE:
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cs->ib[IB_MAIN].ip_type = AMDGPU_HW_IP_VCE;
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cs->chunk_ib[IB_MAIN].ip_type = AMDGPU_HW_IP_VCE;
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break;
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case AMD_IP_VCN_DEC:
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cs->ib[IB_MAIN].ip_type = AMDGPU_HW_IP_VCN_DEC;
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cs->chunk_ib[IB_MAIN].ip_type = AMDGPU_HW_IP_VCN_DEC;
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break;
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case AMD_IP_VCN_ENC:
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cs->ib[IB_MAIN].ip_type = AMDGPU_HW_IP_VCN_ENC;
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cs->chunk_ib[IB_MAIN].ip_type = AMDGPU_HW_IP_VCN_ENC;
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break;
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case AMD_IP_VCN_JPEG:
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cs->ib[IB_MAIN].ip_type = AMDGPU_HW_IP_VCN_JPEG;
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cs->chunk_ib[IB_MAIN].ip_type = AMDGPU_HW_IP_VCN_JPEG;
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break;
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case AMD_IP_VPE:
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cs->ib[IB_MAIN].ip_type = AMDGPU_HW_IP_VPE;
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cs->chunk_ib[IB_MAIN].ip_type = AMDGPU_HW_IP_VPE;
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break;
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case AMD_IP_COMPUTE:
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case AMD_IP_GFX:
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cs->ib[IB_MAIN].ip_type = ip_type == AMD_IP_GFX ? AMDGPU_HW_IP_GFX :
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AMDGPU_HW_IP_COMPUTE;
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cs->chunk_ib[IB_MAIN].ip_type = ip_type == AMD_IP_GFX ? AMDGPU_HW_IP_GFX :
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AMDGPU_HW_IP_COMPUTE;
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/* The kernel shouldn't invalidate L2 and vL1. The proper place for cache
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* invalidation is the beginning of IBs (the previous commit does that),
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@ -1038,8 +1038,8 @@ static bool amdgpu_init_cs_context(struct amdgpu_winsys *ws,
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* is always late.
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*/
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if (ws->info.drm_minor >= 26) {
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cs->ib[IB_PREAMBLE].flags = AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE;
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cs->ib[IB_MAIN].flags = AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE;
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cs->chunk_ib[IB_PREAMBLE].flags = AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE;
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cs->chunk_ib[IB_MAIN].flags = AMDGPU_IB_FLAG_TC_WB_NOT_INVALIDATE;
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}
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break;
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@ -1047,8 +1047,8 @@ static bool amdgpu_init_cs_context(struct amdgpu_winsys *ws,
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assert(0);
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}
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cs->ib[IB_PREAMBLE].flags |= AMDGPU_IB_FLAG_PREAMBLE;
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cs->ib[IB_PREAMBLE].ip_type = cs->ib[IB_MAIN].ip_type;
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cs->chunk_ib[IB_PREAMBLE].flags |= AMDGPU_IB_FLAG_PREAMBLE;
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cs->chunk_ib[IB_PREAMBLE].ip_type = cs->chunk_ib[IB_MAIN].ip_type;
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cs->last_added_bo = NULL;
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return true;
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@ -1203,10 +1203,10 @@ amdgpu_cs_setup_preemption(struct radeon_cmdbuf *rcs, const uint32_t *preamble_i
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amdgpu_bo_unmap(&ws->dummy_ws.base, preamble_bo);
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for (unsigned i = 0; i < 2; i++) {
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csc[i]->ib[IB_PREAMBLE].va_start = amdgpu_winsys_bo(preamble_bo)->va;
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csc[i]->ib[IB_PREAMBLE].ib_bytes = preamble_num_dw * 4;
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csc[i]->chunk_ib[IB_PREAMBLE].va_start = amdgpu_winsys_bo(preamble_bo)->va;
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csc[i]->chunk_ib[IB_PREAMBLE].ib_bytes = preamble_num_dw * 4;
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csc[i]->ib[IB_MAIN].flags |= AMDGPU_IB_FLAG_PREEMPT;
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csc[i]->chunk_ib[IB_MAIN].flags |= AMDGPU_IB_FLAG_PREEMPT;
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}
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assert(!cs->preamble_ib_bo);
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@ -1355,7 +1355,7 @@ static bool is_noop_fence_dependency(struct amdgpu_cs *acs,
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acs->ws->info.ip[acs->ip_type].num_queues == 1) &&
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!amdgpu_fence_is_syncobj(fence) &&
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fence->ctx == acs->ctx &&
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fence->fence.ip_type == cs->ib[IB_MAIN].ip_type)
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fence->fence.ip_type == cs->chunk_ib[IB_MAIN].ip_type)
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return true;
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return amdgpu_fence_wait((void *)fence, 0, false);
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@ -1706,26 +1706,26 @@ static void amdgpu_cs_submit_ib(void *job, void *gdata, int thread_index)
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}
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/* IB */
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if (cs->ib[IB_PREAMBLE].ib_bytes) {
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if (cs->chunk_ib[IB_PREAMBLE].ib_bytes) {
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chunks[num_chunks].chunk_id = AMDGPU_CHUNK_ID_IB;
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chunks[num_chunks].length_dw = sizeof(struct drm_amdgpu_cs_chunk_ib) / 4;
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chunks[num_chunks].chunk_data = (uintptr_t)&cs->ib[IB_PREAMBLE];
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chunks[num_chunks].chunk_data = (uintptr_t)&cs->chunk_ib[IB_PREAMBLE];
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num_chunks++;
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}
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/* IB */
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cs->ib[IB_MAIN].ib_bytes *= 4; /* Convert from dwords to bytes. */
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cs->chunk_ib[IB_MAIN].ib_bytes *= 4; /* Convert from dwords to bytes. */
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chunks[num_chunks].chunk_id = AMDGPU_CHUNK_ID_IB;
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chunks[num_chunks].length_dw = sizeof(struct drm_amdgpu_cs_chunk_ib) / 4;
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chunks[num_chunks].chunk_data = (uintptr_t)&cs->ib[IB_MAIN];
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chunks[num_chunks].chunk_data = (uintptr_t)&cs->chunk_ib[IB_MAIN];
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num_chunks++;
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if (cs->secure) {
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cs->ib[IB_PREAMBLE].flags |= AMDGPU_IB_FLAGS_SECURE;
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cs->ib[IB_MAIN].flags |= AMDGPU_IB_FLAGS_SECURE;
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cs->chunk_ib[IB_PREAMBLE].flags |= AMDGPU_IB_FLAGS_SECURE;
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cs->chunk_ib[IB_MAIN].flags |= AMDGPU_IB_FLAGS_SECURE;
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} else {
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cs->ib[IB_PREAMBLE].flags &= ~AMDGPU_IB_FLAGS_SECURE;
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cs->ib[IB_MAIN].flags &= ~AMDGPU_IB_FLAGS_SECURE;
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cs->chunk_ib[IB_PREAMBLE].flags &= ~AMDGPU_IB_FLAGS_SECURE;
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cs->chunk_ib[IB_MAIN].flags &= ~AMDGPU_IB_FLAGS_SECURE;
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}
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bool noop = acs->noop;
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@ -1733,10 +1733,10 @@ static void amdgpu_cs_submit_ib(void *job, void *gdata, int thread_index)
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if (noop && acs->ip_type == AMD_IP_GFX) {
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/* Reduce the IB size and fill it with NOP to make it like an empty IB. */
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unsigned noop_dw_size = ws->info.ip[AMD_IP_GFX].ib_pad_dw_mask + 1;
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assert(cs->ib[IB_MAIN].ib_bytes / 4 >= noop_dw_size);
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assert(cs->chunk_ib[IB_MAIN].ib_bytes / 4 >= noop_dw_size);
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cs->ib_main_addr[0] = PKT3(PKT3_NOP, noop_dw_size - 2, 0);
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cs->ib[IB_MAIN].ib_bytes = noop_dw_size * 4;
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cs->chunk_ib[IB_MAIN].ib_bytes = noop_dw_size * 4;
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noop = false;
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}
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@ -1891,7 +1891,7 @@ static int amdgpu_cs_flush(struct radeon_cmdbuf *rcs,
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cs->next_fence = NULL;
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} else {
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cur->fence = amdgpu_fence_create(cs->ctx,
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cur->ib[IB_MAIN].ip_type);
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cur->chunk_ib[IB_MAIN].ip_type);
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}
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if (fence)
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amdgpu_fence_reference(fence, cur->fence);
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@ -72,7 +72,7 @@ struct amdgpu_fence_list {
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};
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struct amdgpu_cs_context {
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struct drm_amdgpu_cs_chunk_ib ib[IB_NUM];
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struct drm_amdgpu_cs_chunk_ib chunk_ib[IB_NUM];
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uint32_t *ib_main_addr; /* the beginning of IB before chaining */
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struct amdgpu_winsys *ws;
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