Commit graph

7232 commits

Author SHA1 Message Date
Caio Oliveira
c4355d3f24 intel/compiler: Make brw_nir_populate_wm_prog_data() static
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13629>
2021-11-03 11:09:48 -07:00
Vadym Shovkoplias
732cfa525f anv: Include viewport size in scissor rectangle
Prevent drawing outside the viewport when viewport size
is smaller than framebuffer size.

v2: (Jason Ekstrand)
- re-emit scissor on viewport change
- do the same calculations for other platforms

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5515
Signed-off-by: Vadym Shovkoplias <vadym.shovkoplias@globallogic.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13594>
2021-11-03 17:48:10 +00:00
Caio Marcelo de Oliveira Filho
71022a53e4 anv: Process FS last when compiling graphics pipeline
Enum values for MESA_SHADER_TASK and MESA_SHADER_MESH are larger than
MESA_SHADER_FRAGMENT, so can't rely on the them for ordering anymore.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13637>
2021-11-03 17:28:25 +00:00
Caio Marcelo de Oliveira Filho
a0109a3754 anv: Make shaders array in anv_graphics_pipeline fit Task/Mesh
We could decouple the locations in the array from the gl_shader_stage
enum values, but for now this is convenient.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13637>
2021-11-03 17:28:25 +00:00
Caio Marcelo de Oliveira Filho
eb430aa9e7 anv: Get rid of "may be used initialized" warning in anv_QueueSubmit2KHR
The code is correct, but compiler can't see it.  Initialize the value
to NULL and assert on it if the function succeeds.  It both helps the
compiler and make the code slightly more robust.

```
../src/intel/vulkan/anv_queue.c: In function ‘anv_QueueSubmit2KHR’:
../src/intel/vulkan/anv_queue.c:932:16: warning: ‘impl’ may be used uninitialized in this function [-Wmaybe-uninitialized]
  932 |       result = anv_queue_submit_add_timeline_wait(queue, submit,
      |                ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  933 |                                                   &impl->timeline,
      |                                                   ~~~~~~~~~~~~~~~~
  934 |                                                   value);
      |                                                   ~~~~~~
../src/intel/vulkan/anv_queue.c:899:31: note: ‘impl’ was declared here
  899 |    struct anv_semaphore_impl *impl;
      |                               ^~~~
```

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13638>
2021-11-03 17:14:36 +00:00
Vinson Lee
f13d486ee7 intel/compiler: Initialize SIMDSelectionTest member error.
Fix defect reported by Coverity Scan.

Uninitialized pointer field (UNINIT_CTOR)
uninit_member: Non-static class member error is not initialized
in this constructor nor in any functions that it calls.

Fixes: 7558340ebb ("intel/compiler: Add helpers to select SIMD for compute shaders")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13608>
2021-11-03 04:22:35 +00:00
Vinson Lee
d863e62b32 intel/compiler: Change selected_simd return type to int.
brw_simd_select return type is int.

Fix defect reported by Coverity Scan.

Unsigned compared against 0 (NO_EFFECT)
unsigned_compare: This less-than-zero comparison of an unsigned value is never true. selected_simd < 0U.

Fixes: 7dda0cf2b8 ("intel/compiler: Use SIMD selection helpers for CS")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13606>
2021-11-03 01:48:46 +00:00
Vadym Shovkoplias
2dbb66997e intel/fs: Fix a cmod prop bug when cmod is set to inst that doesn't support it
Fixes dEQP-VK.reconvergence.*nesting* tests.

There are cases when cmod is set to an instruction that cannot have
conditional modifier. E.g. following:

 find_live_channel(32) vgrf166:UD,  NoMask
 cmp.z.f0.0(32) null:D, vgrf166+0.0<0>:D, 0d

is optimized to:

 find_live_channel.z.f0.0(32) vgrf166:UD,  NoMask

v2:
 - Add unit test to check cmod is not set to 'find_live_channel' (Matt Turner)
 - Update flag_subreg when conditonal_mod is updated (Ian Romanick)

Signed-off-by: Vadym Shovkoplias <vadym.shovkoplias@globallogic.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5431
Fixes: 32b7ba66b0 ("intel/compiler: fix cmod propagation optimisations")
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13268>
2021-11-01 21:08:12 +00:00
Jason Ekstrand
4108fda426 vulkan: Move all the common object code to runtime/
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13156>
2021-10-29 23:12:32 +00:00
Kenneth Graunke
2f58a63b2f intel/genxml: Add XY_BLOCK_COPY_BLT on Tigerlake and later.
This is a new blitter command introduced on Tigerlake and expanded
substantially on XeHP.  XY_BLOCK_COPY_BLT is actually fast, unlike
the legacy blitter commands.  iris will use this in the future, and
anv hopefully could use it for a transfer queue someday as well.

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13520>
2021-10-28 14:17:32 -07:00
Kenneth Graunke
9163500aa1 intel/genxml: Allow MI_FLUSH_DW on the blitter
Pretty sure this is how you flush the blitter.

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13520>
2021-10-28 14:17:32 -07:00
Kenneth Graunke
d9ffdfc16d intel/genxml: Include blitter commands in gen*_pack.h
We're going to want to use the blitter again on newer hardware,
which means we need to be able to use genxml to emit those commands.

Acked-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13520>
2021-10-28 14:17:29 -07:00
Kenneth Graunke
7b78b2fcac intel/genxml: Assert that all MOCS fields are non-zero on Gfx7+
Let's try and catch performance problems before we have to do large
painful amounts of analysis to detect a missed field.

Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>
2021-10-28 19:45:56 +00:00
Kenneth Graunke
ebe2a2b5f6 intel/genxml: Add an field option for nonzero="true"
This asserts that the value supplied is non-zero.  Useful for things
like MOCS fields on modern platforms where we really want to avoid
setting it to 0 (uncached).

mbz types cannot be flagged as nonzero.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>
2021-10-28 19:45:56 +00:00
Kenneth Graunke
dfe455b6df anv: Set MOCS on NULL stream output buffers
We'd like to add safeguards against accidental use of MOCS 0 (uncached),
which can have large performance implications.  One case where we use
MOCS of 0 is disabled stream output targets,  MOCS shouldn't matter, as
there's no actual buffer to be cached.

That said, it should be harmless to set MOCS for these null stream
output buffers; we can just assume a MOCS for generic internal buffers.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>
2021-10-28 19:45:55 +00:00
Kenneth Graunke
818b5d2b9e anv: Set MOCS on NULL vertex buffers
We'd like to add safeguards against accidental use of MOCS 0 (uncached),
which can have large performance implications.  One case where we use
MOCS of 0 is 3DSTATE_VERTEX_BUFFERS where we set NullVertexBuffer.
It shouldn't matter here, as there's no actual buffer to be cached.

That said, it should be harmless to set MOCS for null vertex buffers.
We can assume an internal buffer and request isl's vertex buffer MOCS.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>
2021-10-28 19:45:55 +00:00
Kenneth Graunke
7ae9f516f0 anv: Set MOCS in 3DSTATE_CONSTANT_XS even if there isn't a buffer.
This avoids MOCS != 0 assertions in later patches.  iris also does this,
and we do it for the 3DSTATE_CONSTANT_ALL packet path as well.  It's a
bit pointless, but it should hopefully be harmless also.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>
2021-10-28 19:45:55 +00:00
Kenneth Graunke
158ad07b3e anv: Set MOCS for 3DSTATE_CONSTANT_XS on Gfx7.x as well
We were only setting this on Gfx9+.  It's MBZ on Gfx8, but it exists
on Gfx7.x and doesn't have those restrictions there; we should set it.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>
2021-10-28 19:45:55 +00:00
Kenneth Graunke
b4310ef8ee anv: Set default MOCS for NULL depth/stencil/HiZ buffers
isl now uses info->mocs regardless of whether there's any actual
depth/stencil/HiZ buffers involved, so pass it a legitimate one,
rather than zero.  When we have entirely NULL surfaces, we just
default to isl's MOCS value for an internal depth buffer.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>
2021-10-28 19:45:55 +00:00
Kenneth Graunke
fc5168b01d blorp: Use a non-zero MOCS for disabled constant buffers
We'd like to add safeguards against accidental use of MOCS 0 (uncached),
which can have large performance implications.  One case where we use
MOCS of 0 is disabled constant buffers, where MOCS shouldn't matter, as
there's no actual buffer to be cached.

That said, it should be harmless to set MOCS for these null constant
buffers; we can just assume a generic MOCS for internal buffers.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>
2021-10-28 19:45:55 +00:00
Kenneth Graunke
28a503c1a1 blorp: Fill in MOCS for null depth/stencil/HiZ buffers.
isl now uses info->mocs regardless of whether there's any actual
depth/stencil/HiZ buffers involved, so pass it a legitimate one,
rather than zero.  We just assume a generic internal MOCS when we
have entirely NULL surfaces.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>
2021-10-28 19:45:55 +00:00
Kenneth Graunke
edce4649b8 blorp: Fill in MOCS even for SURFTYPE_NULL surfaces.
We'd like to add safeguards against accidental use of MOCS 0 (uncached),
which can have large performance implications.  One case where we use
MOCS of 0 is SURFTYPE_NULL surfaces, where MOCS really shouldn't matter,
as there's no actual surface to be cached.

That said, it should be harmless to set MOCS for these null surfaces;
we can just assume a generic MOCS for internal buffers.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>
2021-10-28 19:45:55 +00:00
Kenneth Graunke
c27fcb1d3b isl: Fill in MOCS for NULL depth, stencil, and HiZ buffers.
We'd like to add safeguards against accidental use of MOCS 0 (uncached),
which can have large performance implications.  One case where we use
MOCS of 0 is SURFTYPE_NULL depth, stencil, and HiZ buffers, where MOCS
really shouldn't matter, as there's no actual surface to be cached.

That said, it should be harmless to set MOCS for these null surfaces.
We now set the one provided in info->mocs regardless of whether any
buffers actually exist or not.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>
2021-10-28 19:45:55 +00:00
Kenneth Graunke
801ecb6f12 isl: Fill in MOCS even for SURFTYPE_NULL surfaces.
We'd like to add safeguards against accidental use of MOCS 0 (uncached),
which can have large performance implications.  One case where we use
MOCS of 0 is SURFTYPE_NULL surfaces, where MOCS really shouldn't matter,
as there's no actual surface to be cached.

That said, it should be harmless to set MOCS for these null surfaces;
we can just assume a generic MOCS for internal buffers.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>
2021-10-28 19:45:55 +00:00
Kenneth Graunke
78d2605e57 intel/genxml: Change 3DSTATE_CONSTANT_XS::MOCS to be MBZ on Gfx8.
The Broadwell PRM says: "Constant Buffer Object Control State must
always be programmed to zero."

This patch changes the MOCS field in gen8.xml to be "mbz" type, so that
it's impossible to set it to a non-zero value.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>
2021-10-28 19:45:55 +00:00
Kenneth Graunke
956effb88a intel/genxml: Drop "Hierarchical Depth Buffer MOCS" field
This is redundant with the existing "MOCS" field.  We don't need both.

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>
2021-10-28 19:45:55 +00:00
Kenneth Graunke
e69d395cd1 intel/genxml: Add an "mbz" data type
There are some fields which Must Be Zero, and we don't want to allow
setting them from the template struct, but we do want them in the XML
to allow them to be decoded properly, and for documentation purposes.

This adds a new "mbz" type, much like "mbo", except it doesn't set
anything in the struct.  We also update the decoder to handle it.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>
2021-10-28 19:45:55 +00:00
Kenneth Graunke
58dc7f6ea6 intel/genxml: Fix Indirect Object Access Upper Bound on Gfx4
We had this field mislabeled as "Instruction Access Upper Bound", but
instruction state base address doesn't exist until Gfx5.  This is
supposed to be the upper bound for indirect object base address,
matching the G45 copy.

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>
2021-10-28 19:45:55 +00:00
Lionel Landwerlin
d3b3daa06b intel/pps: reuse timestamp_frequency from intel_device_info
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Antonio Caggiano <antonio.caggiano@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13571>
2021-10-28 13:16:56 +03:00
Lionel Landwerlin
43d5b55bc1 intel/pps: provide accurate min sampling period
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Antonio Caggiano <antonio.caggiano@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13571>
2021-10-28 13:16:56 +03:00
Lionel Landwerlin
3dda80fcf6 intel/dev: printout timestamp period
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Antonio Caggiano <antonio.caggiano@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13571>
2021-10-28 13:16:56 +03:00
Jordan Justen
64157c706e intel/dev/test: Assert (verx10 / 10) == ver
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13568>
2021-10-28 09:19:07 +00:00
Sagar Ghuge
565d65baaf anv: Enable CCS for storage image formats
v2: (Jason Ekstrand)
- Restructure if condition.
- Add early return.

v3: (Felix)
- Don't set aux_supported to false for storage image on XeHPG.

v4: (Nanley)
- Check image view format against fmt_list.
- Add helper anv_get_isl_format_with_usage.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3606>
2021-10-27 10:59:56 -07:00
Sagar Ghuge
64ea7e5e33 anv: Pass correct aux usage while filling out surface state
While filling out surface state, pass correct aux usage for storage
images as we support compression on XeHPG.

v2: (Jason Ekstrand)
- Move assertion down a bit
- Use general layout aux usage

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3606>
2021-10-27 10:59:56 -07:00
Sagar Ghuge
1ee043e662 anv: Drop hint if primitive id is required or not
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13474>
2021-10-26 18:22:14 +00:00
Sagar Ghuge
3f33222426 intel/compiler: Track primitive id in domain/evaluation shader
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Suggeted-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13474>
2021-10-26 18:22:14 +00:00
Sagar Ghuge
2b86cf2850 intel/genxml: Add new Primitive ID Not Required bit field to 3DSTATE_DS
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13474>
2021-10-26 18:22:14 +00:00
Caio Marcelo de Oliveira Filho
3072e6e0da intel/compiler: Don't use SIMD larger than needed for workgroup
Unless we are combining multiple workgroups in the same HW thread,
there's no advantage of using SIMD16 when SIMD8 already fits the
entire workgroup.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13249>
2021-10-26 17:49:09 +00:00
Caio Marcelo de Oliveira Filho
4e7b71e00c intel/compiler: Use SIMD selection helpers for variable workgroup size
Variable workgroup size works by compiling as much SIMD variants as
possible and then selecting the right one during dispatch (when the
actual workgroup size is passed to us).

Instead of replicating the logic in a separate function, reuse the
same logic for regular SIMD selection.  And move function for that
together with the remaining simd selection functions.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13249>
2021-10-26 17:49:09 +00:00
Caio Marcelo de Oliveira Filho
7dda0cf2b8 intel/compiler: Use SIMD selection helpers for CS
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13249>
2021-10-26 17:49:09 +00:00
Caio Marcelo de Oliveira Filho
7558340ebb intel/compiler: Add helpers to select SIMD for compute shaders
Clean up the logic and move it to functions that work with prog_data
attributes to select the right SIMD.  This shouldn't change any
behavior compared to the original.

Having it extracted will allow reuse by Task/Mesh and make it easier
to write tests.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13249>
2021-10-26 17:49:09 +00:00
Lionel Landwerlin
a6031cd9bd anv: fix push constant lowering with bindless shaders
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 9fa1cdfe7f ("intel/rt: Implement push constants as global memory reads")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13529>
2021-10-26 15:41:43 +00:00
Kenneth Graunke
e79e1ca304 intel: Drop Tigerlake revision 0 workarounds
Tigerlake revision 0 is an early stepping that should not be used in
production anywhere, so this code was only used for hardware bringup.
We can drop the unnecessary workarounds.  This also keeps them from
triggering on early steppings of other Gfx12 parts.

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13266>
2021-10-21 16:53:43 -07:00
Sagar Ghuge
b83c9b21a6 intel/compiler: Set correct cache policy for A64 byte scattered read
This doesn't impact any performance since the previous typo value
matches the current cache control value.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13458>
2021-10-21 17:32:23 +00:00
Jason Ekstrand
39f2594531 anv: Implement VK_EXT_global_priority_query
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11250>
2021-10-20 15:51:59 +00:00
Vinson Lee
9eb010ee1e anv: Fix assertion.
Fix defect reported by Coverity Scan.

Assign instead of compare (PW.ASSIGN_WHERE_COMPARE_MEANT)
assign_where_compare_meant: use of "=" where "==" may have been intended

Fixes: 35315c68a5 ("anv: Use the common wrapper for GetPhysicalDeviceFormatProperties")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13395>
2021-10-18 09:04:47 +00:00
Jason Ekstrand
3ace6b968b compiler/types: Add a texture type
This is separate from images and samplers.  It's a texture (not a
storage image) without a sampler.  We also add C-visible helpers to
convert between sampler and image types.

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13389>
2021-10-16 05:49:34 +00:00
Jason Ekstrand
956199e870 nir: s/nir_var_mem_image/nir_var_image/g
We typically use nir_var_mem_* for stuff that has an explicit byte-based
memory layout.  Images are opaque.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13386>
2021-10-16 03:47:10 +00:00
Dylan Baker
e73096bd6d meson: use gtest protocol for gtest based tests when possible
With the `gtest` protocol meson will add some extra arguments to the
test to generate better junit results, which may be useful. This
protocol is only available in meson 0.55.0+, so keep using the default
`exitcode` protocol for meson older than that.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8484>
2021-10-16 03:22:24 +00:00
Marcin Ślusarz
d05f7b4a2c intel: fix INTEL_DEBUG environment variable on 32-bit systems
INTEL_DEBUG is defined (since 4015e1876a) as:

 #define INTEL_DEBUG __builtin_expect(intel_debug, 0)

which unfortunately chops off upper 32 bits from intel_debug
on platforms where sizeof(long) != sizeof(uint64_t) because
__builtin_expect is defined only for the long type.

Fix this by changing the definition of INTEL_DEBUG to be function-like
macro with "flags" argument. New definition returns 0 or 1 when
any of the flags match.

Most of the changes in this commit were generated using:
for c in `git grep INTEL_DEBUG | grep "&" | grep -v i915 | awk -F: '{print $1}' | sort | uniq`; do
    perl -pi -e "s/INTEL_DEBUG & ([A-Z0-9a-z_]+)/INTEL_DBG(\1)/" $c
    perl -pi -e "s/INTEL_DEBUG & (\([A-Z0-9_ |]+\))/INTEL_DBG\1/" $c
done
but it didn't handle all cases and required minor cleanups (like removal
of round brackets which were not needed anymore).

Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13334>
2021-10-15 19:55:14 +00:00