Commit graph

16650 commits

Author SHA1 Message Date
Tom Stellard
2809ae3d44 radeon/llvm: Fix encoding of FP immediates on SI 2012-08-29 15:52:10 -04:00
Tom Stellard
05113fd266 radeon/llvm: Create a register class for the M0 register
The Common Subexpression Elimination pass will not operate on
instructions with physical register defs, so we end up with
several redundant copies to M0 when using interpolation.

Adding a register class that only contains the M0 register allows
use to use a virtual register to represent M0, and makes it possible
for the Common Subexpression Elimination pass to remove the extra
copies.
2012-08-29 15:52:10 -04:00
Tom Stellard
733c28a0d9 radeon/llvm: Set the neverHasSideEffects bit on more instructions
This flag makes these instructions candidates for the dead code
elimination and common subexpression elimination.
2012-08-29 15:52:10 -04:00
Tom Stellard
cf4ac69928 radeon/llvm: Declare the interpolation intrinsics as ReadOnly
This signals to the Dead Code Elimination pass that it is safe to
remove these instructions when they are dead.
2012-08-29 15:52:10 -04:00
Tom Stellard
73a2c4b9db radeon/llvm: Mark M0 as a def when lowering interpolation instructions 2012-08-29 15:52:10 -04:00
Michel Dänzer
70f9dbe298 radeon/llvm: Handle TGSI KIL opcode for SI.
Fixes piglit fp-kil and glBitmap() with radeonsi.

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
2012-08-28 20:27:23 +02:00
Michel Dänzer
16e42a5dd0 radeon/llvm: Basic support for SI EXEC register.
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
2012-08-28 20:26:50 +02:00
Michel Dänzer
6ca64393c9 radeonsi: Don't write to the PA_SC_RASTER_CONFIG register.
It should be initialized by the kernel as necessary.

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2012-08-28 20:24:52 +02:00
Marek Olšák
999b7f6665 r600g: fix relative addressing on RS780 and RS880
They should be treated like RV670.

Tested-by: Michel Dänzer <michel.daenzer@amd.com>
2012-08-28 18:27:03 +02:00
José Fonseca
bc8509b43b llvmpipe: Bump the maximum texture size (in pixels).
But cap the size in bytes, to avoid depleting the whole system memory,
with humongus textures.

Tested with max-texture-size piglit test.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
2012-08-28 15:18:43 +01:00
Vadim Girlin
6463eb013f u_vbuf: avoid unnecessary update of the vertex elements
Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
Reviewed-by: Marek Olšák <maraeo@gmail.com>
2012-08-28 18:01:13 +04:00
Brian Paul
f308c80490 gallium/util: implement tile code for PIPE_FORMAT_Z32_FLOAT
Reviewed-by: José Fonseca <jfonseca@vmware.com>
2012-08-27 13:32:53 -06:00
Marek Olšák
7f0fcf17c3 r300g: implement TRUNC correctly
This fixes some integer division tests.
2012-08-27 14:35:18 +02:00
Michel Dänzer
f402acdbe2 radeonsi: Use FP16 shader export format when necessary / possible.
Fixes piglit fbo-blending-formats.

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2012-08-27 11:51:56 +02:00
Michel Dänzer
26c7139d2c radeonsi: Refactor initialization of shader export intrinsic arguments.
In preparation for extending this code, which would make it rather unwieldy in
its current place.

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2012-08-27 11:51:49 +02:00
Michel Dänzer
d1e40b3d40 radeonsi: Maintain cache of pixel shader variants according to contxt state.
Mostly inspired by r600g commit 4acf71f01e
('r600g: cache shader variants instead of rebuilding v3').

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2012-08-27 11:51:41 +02:00
Michel Dänzer
84fdda280f radeonsi: Drop extraneous semicolons from pm4 state macro definitions.
Could cause build failures if trying to use the macros in certain constructs.

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2012-08-27 11:50:38 +02:00
Marek Olšák
a3d9d7ec79 r600g: implement compression for MSAA colorbuffers for evergreen
This adds the FMASK and CMASK buffers. They share the same resource
with color data.

COMPRESSION and FAST_CLEAR are always enabled if both FMASK and CMASK are
allocated. We initialize the CMASK to a "compressed" state (not "fast cleared"),
so that we can keep FAST_CLEAR enabled all the time.

Both FMASK and CMASK must be present at the moment. If either one is missing,
the other one is not used.

v2: add cayman regs in the list

Reviewed-by: Jerome Glisse <jglisse@redhat.com>
2012-08-27 04:31:00 +02:00
Marek Olšák
48edfe0505 r600g: cleanup names around depth decompression
for consistency with the upcoming color decompression naming

Reviewed-by: Jerome Glisse <jglisse@redhat.com>
2012-08-27 04:31:00 +02:00
Marek Olšák
3ac54ac2c8 r600g: fix evergreen 8x MSAA sample positions
The original samples positions took samples outside of the pixel boundary,
leading to dark pixels on the edge of the colorbuffer, among other things.

Reviewed-by: Jerome Glisse <jglisse@redhat.com>
2012-08-27 04:31:00 +02:00
Marek Olšák
1cfec6e2c8 r600g: set CB_TARGET_MASK to 0xf and not 0xff for resolve on evergreen
independent_blend_enable must be true, so that the colormask isn't replicated
in all colorbuffers.

Reviewed-by: Jerome Glisse <jglisse@redhat.com>
2012-08-27 04:30:59 +02:00
Marek Olšák
1516a4f353 gallium/u_blitter: initialize sample mask in resolve
Reviewed-by: Jerome Glisse <jglisse@redhat.com>
2012-08-27 04:30:59 +02:00
Tom Stellard
07c71d6ede r300/compiler: Use variable lists in the rename_regs pass 2012-08-26 20:39:49 -04:00
Jakob Bornecrantz
33ee019422 st/dri: Support width and height getters
Tested-by: Scott Moreau <oreaus@gmail.com>
Signed-off-by: Jakob Bornecrantz <jakob@vmware.com>
2012-08-26 15:40:18 +02:00
Jakob Bornecrantz
15effe1fab st/dri: Claim to support validate_usage
Support version 3 as well as 2, since that is only the new format query,
which Jesse added support for to st/dri when he added it to dri_inteface.h.

Tested-by: Scott Moreau <oreaus@gmail.com>
Signed-off-by: Jakob Bornecrantz <jakob@vmware.com>
2012-08-26 15:40:10 +02:00
Brian Paul
229868edf7 wgl: update some comments 2012-08-24 14:09:03 -06:00
Christian König
9aacd5cc67 radeonsi: remove old tilling handling
Just use the functionality provided by the surface manager instead.

This fixes just another bunch of piglit tests.

Signed-off-by: Christian König <deathsimple@vodafone.de>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2012-08-24 18:11:31 +02:00
Blaž Tomažič
87280d56a3 clover: Accept CL_MEM_READ_WRITE flag
Fix API functions for memory objects to accept CL_MEM_READ_WRITE flag.

Signed-off-by: Blaž Tomažič <blaz.tomazic@gmail.com>
[ Francisco Jerez: Drop incorrect change in clCreateSubBuffer. ]
2012-08-24 17:10:14 +02:00
Tom Stellard
167ecf5ba3 radeon/llvm: Cleanup R600Instructions.td 2012-08-24 14:14:55 +00:00
José Fonseca
3e3f99277d draw: Fix regression in draw_set_sampler(_views).
draw->samplers(_views) now has PIPE_SHADER_TYPES elements, instead of
PIPE_MAX_SAMPLERS as before.

Also, shader_stage must be less than PIPE_SHADER_TYPES to prevent buffer
overflow.

Trivial.
2012-08-24 11:28:00 +01:00
Tom Stellard
1434a86f50 radeon/llvm: Set End of Program bit on RAT instructions
This code was accidently dropped during the MCCodeEmitter conversion.
2012-08-23 21:54:32 +00:00
Tom Stellard
1bd7b29a66 radeon/llvm: Use correct instruction for moving immediates
This should fix an assertion failure that was happening in some compute
shaders.
2012-08-23 21:54:32 +00:00
Tom Stellard
2ad8608cb3 radeon/llvm: Fix some coding style issues 2012-08-23 21:54:32 +00:00
Tom Stellard
228a6641cc radeon/llvm: Pull changes from external version of the backend 2012-08-23 21:54:32 +00:00
Tom Stellard
5a1edb8655 radeon/llvm: Simplify the convert to ISA pass 2012-08-23 21:54:32 +00:00
Tom Stellard
cb5227b403 radeon/llvm: Make sure to use the Text section in the AsmPrinter 2012-08-23 21:54:31 +00:00
Vadim Girlin
68d6441930 st/dri: pass config options to the state tracker
Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
2012-08-23 19:57:51 +04:00
Vadim Girlin
a6457c0692 st/mesa: accept and handle configuration options from st/dri
Currently there is a single option - force_glsl_extensions_warn.

Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
2012-08-23 19:57:51 +04:00
Vadim Girlin
44f69fc825 st/dri: add force_glsl_extensions_warn option to dri options
Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
2012-08-23 19:57:51 +04:00
Vadim Girlin
e7c177ec9e st/dri: use driver name for driconf section lookup
The name is taken from the driver_descriptor, so it will be the same as
expected by driconf utility.

Signed-off-by: Vadim Girlin <vadimgirlin@gmail.com>
2012-08-23 19:57:51 +04:00
Vadim Girlin
6547733593 swrast: add DRM_DRIVER_DESCRIPTOR to store driver name 2012-08-23 19:57:50 +04:00
Tom Stellard
90bd1d52bb radeon/llvm: Use the MCCodeEmitter for R600 2012-08-23 15:00:48 +00:00
Tom Stellard
235318a578 radeon/llvm: Use the MCCodeEmitter for SI 2012-08-23 15:00:48 +00:00
Tom Stellard
2de24024c1 radeon/llvm: Set 64BitPtr feature bit for SI 2012-08-23 15:00:48 +00:00
Tom Stellard
3f9b6aa0f4 radeon/llvm: Lower RETFLAG DAG Node to S_ENDPGM on SI 2012-08-23 15:00:48 +00:00
Tom Stellard
e30b4644b6 radeon/llvm: Add AsmPrinter 2012-08-23 15:00:48 +00:00
Tom Stellard
e61c54cb6b radeon/llvm: Mark JUMP as a pseudo instruction 2012-08-23 15:00:48 +00:00
Tom Stellard
ead72204f1 radeon/llvm: Remove the last uses of MachineOperand flags 2012-08-23 15:00:47 +00:00
Tom Stellard
67a47a445b radeon/llvm: Add flag operand to some instructions
This new operand replaces the MachineOperand flags in LLVM, which
will be deprecated soon.  Eventually all instructions should have a flag
operand, but for now this operand has only been added to instructions
that need it.
2012-08-23 15:00:47 +00:00
Tom Stellard
3a7a56e7aa radeon/llvm: Encapsulate setting of MachineOperand flags
MachineOperand flags will be removed soon, so it is convienent to
have only one function that modifies them.
2012-08-23 15:00:47 +00:00