mirror of
https://gitlab.freedesktop.org/mesa/mesa.git
synced 2025-12-25 02:10:11 +01:00
radeonsi: remove old tilling handling
Just use the functionality provided by the surface manager instead. This fixes just another bunch of piglit tests. Signed-off-by: Christian König <deathsimple@vodafone.de> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
This commit is contained in:
Christian König
parent
86f29cf7d0
commit
9aacd5cc67
3 changed files with 31 additions and 279 deletions
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@ -46,13 +46,7 @@ struct r600_resource_texture {
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* for the stencil buffer below. */
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enum pipe_format real_format;
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unsigned offset[PIPE_MAX_TEXTURE_LEVELS];
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unsigned pitch_in_bytes[PIPE_MAX_TEXTURE_LEVELS]; /* transfer */
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unsigned pitch_in_blocks[PIPE_MAX_TEXTURE_LEVELS]; /* texture resource */
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unsigned layer_size[PIPE_MAX_TEXTURE_LEVELS];
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unsigned array_mode[PIPE_MAX_TEXTURE_LEVELS];
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unsigned pitch_override;
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unsigned size;
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unsigned depth;
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unsigned dirty_db;
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struct r600_resource_texture *flushed_depth_texture;
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@ -60,11 +54,8 @@ struct r600_resource_texture {
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struct radeon_surface surface;
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};
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#define R600_TEX_IS_TILED(tex, level) ((tex)->array_mode[level] != V_009910_ARRAY_LINEAR_GENERAL && (tex)->array_mode[level] != V_009910_ARRAY_LINEAR_ALIGNED)
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struct r600_surface {
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struct pipe_surface base;
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unsigned aligned_height;
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};
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void r600_init_screen_resource_functions(struct pipe_screen *screen);
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@ -69,175 +69,8 @@ static void r600_copy_from_staging_texture(struct pipe_context *ctx, struct r600
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static unsigned r600_texture_get_offset(struct r600_resource_texture *rtex,
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unsigned level, unsigned layer)
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{
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unsigned offset = rtex->offset[level];
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switch (rtex->resource.b.b.target) {
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case PIPE_TEXTURE_3D:
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case PIPE_TEXTURE_CUBE:
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default:
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return offset + layer * rtex->layer_size[level];
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}
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}
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static unsigned r600_get_block_alignment(struct pipe_screen *screen,
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enum pipe_format format,
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unsigned array_mode)
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{
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struct r600_screen* rscreen = (struct r600_screen *)screen;
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unsigned pixsize = util_format_get_blocksize(format);
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int p_align;
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switch(array_mode) {
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case V_009910_ARRAY_1D_TILED_THIN1:
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p_align = MAX2(8,
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((rscreen->tiling_info.group_bytes / 8 / pixsize)));
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break;
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case V_009910_ARRAY_2D_TILED_THIN1:
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p_align = MAX2(rscreen->tiling_info.num_banks,
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(((rscreen->tiling_info.group_bytes / 8 / pixsize)) *
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rscreen->tiling_info.num_banks)) * 8;
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break;
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case V_009910_ARRAY_LINEAR_ALIGNED:
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p_align = MAX2(64, rscreen->tiling_info.group_bytes / pixsize);
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break;
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case V_009910_ARRAY_LINEAR_GENERAL:
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default:
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p_align = rscreen->tiling_info.group_bytes / pixsize;
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break;
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}
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return p_align;
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}
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static unsigned r600_get_height_alignment(struct pipe_screen *screen,
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unsigned array_mode)
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{
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struct r600_screen* rscreen = (struct r600_screen *)screen;
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int h_align;
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switch (array_mode) {
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case V_009910_ARRAY_2D_TILED_THIN1:
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h_align = rscreen->tiling_info.num_channels * 8;
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break;
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case V_009910_ARRAY_1D_TILED_THIN1:
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case V_009910_ARRAY_LINEAR_ALIGNED:
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h_align = 8;
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break;
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case V_009910_ARRAY_LINEAR_GENERAL:
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default:
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h_align = 1;
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break;
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}
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return h_align;
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}
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static unsigned r600_get_base_alignment(struct pipe_screen *screen,
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enum pipe_format format,
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unsigned array_mode)
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{
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struct r600_screen* rscreen = (struct r600_screen *)screen;
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unsigned pixsize = util_format_get_blocksize(format);
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int p_align = r600_get_block_alignment(screen, format, array_mode);
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int h_align = r600_get_height_alignment(screen, array_mode);
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int b_align;
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switch (array_mode) {
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case V_009910_ARRAY_2D_TILED_THIN1:
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b_align = MAX2(rscreen->tiling_info.num_banks * rscreen->tiling_info.num_channels * 8 * 8 * pixsize,
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p_align * pixsize * h_align);
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break;
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case V_009910_ARRAY_1D_TILED_THIN1:
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case V_009910_ARRAY_LINEAR_ALIGNED:
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case V_009910_ARRAY_LINEAR_GENERAL:
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default:
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b_align = rscreen->tiling_info.group_bytes;
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break;
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}
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return b_align;
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}
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static unsigned mip_minify(unsigned size, unsigned level)
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{
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unsigned val;
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val = u_minify(size, level);
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if (level > 0)
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val = util_next_power_of_two(val);
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return val;
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}
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static unsigned r600_texture_get_nblocksx(struct pipe_screen *screen,
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struct r600_resource_texture *rtex,
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unsigned level)
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{
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struct pipe_resource *ptex = &rtex->resource.b.b;
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unsigned nblocksx, block_align, width;
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unsigned blocksize = util_format_get_blocksize(rtex->real_format);
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if (rtex->pitch_override)
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return rtex->pitch_override / blocksize;
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width = mip_minify(ptex->width0, level);
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nblocksx = util_format_get_nblocksx(rtex->real_format, width);
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block_align = r600_get_block_alignment(screen, rtex->real_format,
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rtex->array_mode[level]);
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nblocksx = align(nblocksx, block_align);
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return nblocksx;
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}
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static unsigned r600_texture_get_nblocksy(struct pipe_screen *screen,
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struct r600_resource_texture *rtex,
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unsigned level)
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{
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struct pipe_resource *ptex = &rtex->resource.b.b;
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unsigned height, tile_height;
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height = mip_minify(ptex->height0, level);
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height = util_format_get_nblocksy(rtex->real_format, height);
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tile_height = r600_get_height_alignment(screen,
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rtex->array_mode[level]);
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/* XXX Hack around an alignment issue. Less tests fail with this.
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*
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* The thing is depth-stencil buffers should be tiled, i.e.
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* the alignment should be >=8. If I make them tiled, stencil starts
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* working because it no longer overlaps with the depth buffer
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* in memory, but texturing like drawpix-stencil breaks. */
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if (util_format_is_depth_or_stencil(rtex->real_format) && tile_height < 8)
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tile_height = 8;
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height = align(height, tile_height);
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return height;
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}
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static void r600_texture_set_array_mode(struct pipe_screen *screen,
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struct r600_resource_texture *rtex,
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unsigned level, unsigned array_mode)
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{
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struct pipe_resource *ptex = &rtex->resource.b.b;
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switch (array_mode) {
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case V_009910_ARRAY_LINEAR_GENERAL:
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case V_009910_ARRAY_LINEAR_ALIGNED:
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case V_009910_ARRAY_1D_TILED_THIN1:
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default:
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rtex->array_mode[level] = array_mode;
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break;
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case V_009910_ARRAY_2D_TILED_THIN1:
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{
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unsigned w, h, tile_height, tile_width;
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tile_height = r600_get_height_alignment(screen, array_mode);
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tile_width = r600_get_block_alignment(screen, rtex->real_format, array_mode);
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w = mip_minify(ptex->width0, level);
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h = mip_minify(ptex->height0, level);
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if (w <= tile_width || h <= tile_height)
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rtex->array_mode[level] = V_009910_ARRAY_1D_TILED_THIN1;
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else
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rtex->array_mode[level] = array_mode;
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}
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break;
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}
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return rtex->surface.level[level].offset +
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layer * rtex->surface.level[level].slice_size;
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}
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static int r600_init_surface(struct radeon_surface *surface,
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@ -316,9 +149,7 @@ static int r600_setup_surface(struct pipe_screen *screen,
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unsigned array_mode,
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unsigned pitch_in_bytes_override)
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{
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struct pipe_resource *ptex = &rtex->resource.b.b;
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struct r600_screen *rscreen = (struct r600_screen*)screen;
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unsigned i;
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int r;
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if (util_format_is_depth_or_stencil(rtex->real_format)) {
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@ -330,7 +161,6 @@ static int r600_setup_surface(struct pipe_screen *screen,
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if (r) {
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return r;
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}
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rtex->size = rtex->surface.bo_size;
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if (pitch_in_bytes_override && pitch_in_bytes_override != rtex->surface.level[0].pitch_bytes) {
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/* old ddx on evergreen over estimate alignment for 1d, only 1 level
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* for those
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@ -342,74 +172,9 @@ static int r600_setup_surface(struct pipe_screen *screen,
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rtex->surface.stencil_offset = rtex->surface.level[0].slice_size;
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}
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}
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for (i = 0; i <= ptex->last_level; i++) {
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rtex->offset[i] = rtex->surface.level[i].offset;
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rtex->layer_size[i] = rtex->surface.level[i].slice_size;
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rtex->pitch_in_bytes[i] = rtex->surface.level[i].pitch_bytes;
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switch (rtex->surface.level[i].mode) {
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case RADEON_SURF_MODE_LINEAR_ALIGNED:
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rtex->array_mode[i] = V_009910_ARRAY_LINEAR_ALIGNED;
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break;
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case RADEON_SURF_MODE_1D:
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rtex->array_mode[i] = V_009910_ARRAY_1D_TILED_THIN1;
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break;
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case RADEON_SURF_MODE_2D:
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rtex->array_mode[i] = V_009910_ARRAY_2D_TILED_THIN1;
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break;
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default:
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case RADEON_SURF_MODE_LINEAR:
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rtex->array_mode[i] = 0;
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break;
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}
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}
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return 0;
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}
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static void r600_setup_miptree(struct pipe_screen *screen,
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struct r600_resource_texture *rtex,
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unsigned array_mode)
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{
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struct pipe_resource *ptex = &rtex->resource.b.b;
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enum chip_class chipc = ((struct r600_screen*)screen)->chip_class;
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unsigned size, layer_size, i, offset;
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unsigned nblocksx, nblocksy;
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for (i = 0, offset = 0; i <= ptex->last_level; i++) {
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unsigned blocksize = util_format_get_blocksize(rtex->real_format);
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unsigned base_align = r600_get_base_alignment(screen, rtex->real_format, array_mode);
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r600_texture_set_array_mode(screen, rtex, i, array_mode);
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nblocksx = r600_texture_get_nblocksx(screen, rtex, i);
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nblocksy = r600_texture_get_nblocksy(screen, rtex, i);
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if (array_mode == V_009910_ARRAY_LINEAR_GENERAL)
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layer_size = align(nblocksx, 64) * nblocksy * blocksize;
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else
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layer_size = nblocksx * nblocksy * blocksize;
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if (ptex->target == PIPE_TEXTURE_CUBE) {
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if (chipc >= CAYMAN)
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size = layer_size * 8;
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}
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else if (ptex->target == PIPE_TEXTURE_3D)
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size = layer_size * u_minify(ptex->depth0, i);
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else
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size = layer_size * ptex->array_size;
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/* align base image and start of miptree */
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if ((i == 0) || (i == 1))
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offset = align(offset, base_align);
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rtex->offset[i] = offset;
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rtex->layer_size[i] = layer_size;
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rtex->pitch_in_blocks[i] = nblocksx; /* CB talks in elements */
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rtex->pitch_in_bytes[i] = nblocksx * blocksize;
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offset += size;
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}
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rtex->size = offset;
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}
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/* Figure out whether u_blitter will fallback to a transfer operation.
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* If so, don't use a staging resource.
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*/
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@ -470,10 +235,10 @@ static boolean r600_texture_get_handle(struct pipe_screen* screen,
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surface->tile_split,
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surface->stencil_tile_split,
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surface->mtilea,
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rtex->pitch_in_bytes[0]);
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surface->level[0].pitch_bytes);
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return rscreen->ws->buffer_get_handle(resource->buf,
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rtex->pitch_in_bytes[0], whandle);
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surface->level[0].pitch_bytes, whandle);
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}
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static void r600_texture_destroy(struct pipe_screen *screen,
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@ -483,7 +248,7 @@ static void r600_texture_destroy(struct pipe_screen *screen,
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struct si_resource *resource = &rtex->resource;
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if (rtex->flushed_depth_texture)
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si_resource_reference(&rtex->flushed_depth_texture, NULL);
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si_resource_reference((struct si_resource **)&rtex->flushed_depth_texture, NULL);
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pb_reference(&resource->buf, NULL);
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FREE(rtex);
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@ -515,7 +280,8 @@ static struct pipe_transfer* si_texture_get_transfer(struct pipe_context *ctx,
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* the CPU is much happier reading out of cached system memory
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* than uncached VRAM.
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*/
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if (R600_TEX_IS_TILED(rtex, level))
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if (rtex->surface.level[level].mode != RADEON_SURF_MODE_LINEAR_ALIGNED &&
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rtex->surface.level[level].mode != RADEON_SURF_MODE_LINEAR)
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use_staging_texture = TRUE;
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if ((usage & PIPE_TRANSFER_READ) && u_box_volume(box) > 1024)
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@ -558,7 +324,7 @@ static struct pipe_transfer* si_texture_get_transfer(struct pipe_context *ctx,
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FREE(trans);
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return NULL;
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}
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trans->transfer.stride = rtex->flushed_depth_texture->pitch_in_bytes[level];
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trans->transfer.stride = rtex->flushed_depth_texture->surface.level[level].pitch_bytes;
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trans->offset = r600_texture_get_offset(rtex->flushed_depth_texture, level, box->z);
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return &trans->transfer;
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} else if (use_staging_texture) {
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@ -592,8 +358,8 @@ static struct pipe_transfer* si_texture_get_transfer(struct pipe_context *ctx,
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return NULL;
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}
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trans->transfer.stride =
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((struct r600_resource_texture *)trans->staging_texture)->pitch_in_bytes[0];
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trans->transfer.stride = ((struct r600_resource_texture *)trans->staging_texture)
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->surface.level[0].pitch_bytes;
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if (usage & PIPE_TRANSFER_READ) {
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r600_copy_to_staging_texture(ctx, trans);
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/* Always referenced in the blit. */
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@ -601,8 +367,8 @@ static struct pipe_transfer* si_texture_get_transfer(struct pipe_context *ctx,
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}
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return &trans->transfer;
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}
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trans->transfer.stride = rtex->pitch_in_bytes[level];
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trans->transfer.layer_stride = rtex->layer_size[level];
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trans->transfer.stride = rtex->surface.level[level].pitch_bytes;
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trans->transfer.layer_stride = rtex->surface.level[level].slice_size;
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trans->offset = r600_texture_get_offset(rtex, level, box->z);
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return &trans->transfer;
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}
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@ -646,7 +412,7 @@ static void* si_texture_transfer_map(struct pipe_context *ctx,
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struct r600_resource_texture *rtex = (struct r600_resource_texture*)transfer->resource;
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if (rtex->flushed_depth_texture)
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buf = si_resource(rtex->flushed_depth_texture)->cs_buf;
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buf = rtex->flushed_depth_texture->resource.cs_buf;
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else
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buf = si_resource(transfer->resource)->cs_buf;
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@ -675,7 +441,7 @@ static void si_texture_transfer_unmap(struct pipe_context *ctx,
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struct r600_resource_texture *rtex = (struct r600_resource_texture*)transfer->resource;
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if (rtex->flushed_depth_texture) {
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buf = si_resource(rtex->flushed_depth_texture)->cs_buf;
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buf = rtex->flushed_depth_texture->resource.cs_buf;
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} else {
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buf = si_resource(transfer->resource)->cs_buf;
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}
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@ -726,7 +492,6 @@ r600_texture_create_object(struct pipe_screen *screen,
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if (util_format_is_depth_or_stencil(rtex->real_format) && permit_hardware_blit(screen, base))
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rtex->depth = 1;
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r600_setup_miptree(screen, rtex, array_mode);
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rtex->surface = *surface;
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r = r600_setup_surface(screen, rtex, array_mode, pitch_in_bytes_override);
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if (r) {
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@ -736,11 +501,11 @@ r600_texture_create_object(struct pipe_screen *screen,
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/* Now create the backing buffer. */
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if (!buf && alloc_bo) {
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struct pipe_resource *ptex = &rtex->resource.b.b;
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unsigned base_align = r600_get_base_alignment(screen, ptex->format, array_mode);
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unsigned base_align = rtex->surface.bo_alignment;
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unsigned size = rtex->surface.bo_size;
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base_align = rtex->surface.bo_alignment;
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if (!si_init_resource(rscreen, resource, rtex->size, base_align, base->bind, base->usage)) {
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if (!si_init_resource(rscreen, resource, size, base_align, base->bind, base->usage)) {
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FREE(rtex);
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return NULL;
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}
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@ -799,16 +564,14 @@ static struct pipe_surface *r600_create_surface(struct pipe_context *pipe,
|
|||
pipe_resource_reference(&surface->base.texture, texture);
|
||||
surface->base.context = pipe;
|
||||
surface->base.format = surf_tmpl->format;
|
||||
surface->base.width = mip_minify(texture->width0, level);
|
||||
surface->base.height = mip_minify(texture->height0, level);
|
||||
surface->base.width = rtex->surface.level[level].npix_x;
|
||||
surface->base.height = rtex->surface.level[level].npix_y;
|
||||
surface->base.usage = surf_tmpl->usage;
|
||||
surface->base.texture = texture;
|
||||
surface->base.u.tex.first_layer = surf_tmpl->u.tex.first_layer;
|
||||
surface->base.u.tex.last_layer = surf_tmpl->u.tex.last_layer;
|
||||
surface->base.u.tex.level = level;
|
||||
|
||||
surface->aligned_height = r600_texture_get_nblocksy(pipe->screen,
|
||||
rtex, level);
|
||||
return &surface->base;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -1805,7 +1805,7 @@ static struct pipe_sampler_view *si_create_sampler_view(struct pipe_context *ctx
|
|||
unsigned format, num_format, /*endian,*/ tiling_index;
|
||||
uint32_t pitch = 0;
|
||||
unsigned char state_swizzle[4], swizzle[4];
|
||||
unsigned height, depth, width;
|
||||
unsigned height, depth, width, offset_level, last_level;
|
||||
int first_non_void;
|
||||
uint64_t va;
|
||||
|
||||
|
|
@ -1852,11 +1852,12 @@ static struct pipe_sampler_view *si_create_sampler_view(struct pipe_context *ctx
|
|||
/* not supported any more */
|
||||
//endian = si_colorformat_endian_swap(format);
|
||||
|
||||
height = texture->height0;
|
||||
depth = texture->depth0;
|
||||
width = texture->width0;
|
||||
pitch = align(tmp->pitch_in_blocks[0] *
|
||||
util_format_get_blockwidth(state->format), 8);
|
||||
offset_level = state->u.tex.first_level;
|
||||
last_level = state->u.tex.last_level - offset_level;
|
||||
width = tmp->surface.level[offset_level].npix_x;
|
||||
height = tmp->surface.level[offset_level].npix_y;
|
||||
depth = tmp->surface.level[offset_level].npix_z;
|
||||
pitch = tmp->surface.level[offset_level].nblk_x * util_format_get_blockwidth(state->format);
|
||||
|
||||
if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
|
||||
height = 1;
|
||||
|
|
@ -1907,12 +1908,9 @@ static struct pipe_sampler_view *si_create_sampler_view(struct pipe_context *ctx
|
|||
}
|
||||
|
||||
va = r600_resource_va(ctx->screen, texture);
|
||||
if (state->u.tex.last_level) {
|
||||
view->state[0] = (va + tmp->offset[1]) >> 8;
|
||||
} else {
|
||||
view->state[0] = (va + tmp->offset[0]) >> 8;
|
||||
}
|
||||
view->state[1] = (S_008F14_BASE_ADDRESS_HI((va + tmp->offset[0]) >> 40) |
|
||||
va += tmp->surface.level[offset_level].offset;
|
||||
view->state[0] = va >> 8;
|
||||
view->state[1] = (S_008F14_BASE_ADDRESS_HI(va >> 40) |
|
||||
S_008F14_DATA_FORMAT(format) |
|
||||
S_008F14_NUM_FORMAT(num_format));
|
||||
view->state[2] = (S_008F18_WIDTH(width - 1) |
|
||||
|
|
@ -1921,8 +1919,8 @@ static struct pipe_sampler_view *si_create_sampler_view(struct pipe_context *ctx
|
|||
S_008F1C_DST_SEL_Y(si_map_swizzle(swizzle[1])) |
|
||||
S_008F1C_DST_SEL_Z(si_map_swizzle(swizzle[2])) |
|
||||
S_008F1C_DST_SEL_W(si_map_swizzle(swizzle[3])) |
|
||||
S_008F1C_BASE_LEVEL(state->u.tex.first_level) |
|
||||
S_008F1C_LAST_LEVEL(state->u.tex.last_level) |
|
||||
S_008F1C_BASE_LEVEL(offset_level) |
|
||||
S_008F1C_LAST_LEVEL(last_level) |
|
||||
S_008F1C_TILING_INDEX(tiling_index) |
|
||||
S_008F1C_TYPE(si_tex_dim(texture->target)));
|
||||
view->state[4] = (S_008F20_DEPTH(depth - 1) | S_008F20_PITCH(pitch - 1));
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue