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radeon/llvm: Remove the last uses of MachineOperand flags
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parent
67a47a445b
commit
ead72204f1
2 changed files with 27 additions and 8 deletions
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@ -316,7 +316,7 @@ R600InstrInfo::InsertBranch(MachineBasicBlock &MBB,
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} else {
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MachineInstr *PredSet = findFirstPredicateSetterFrom(MBB, MBB.end());
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assert(PredSet && "No previous predicate !");
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PredSet->getOperand(1).addTargetFlag(1<<4);
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AddFlag(PredSet, 1, MO_FLAG_PUSH);
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PredSet->getOperand(2).setImm(Cond[1].getImm());
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BuildMI(&MBB, DL, get(AMDGPU::JUMP))
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@ -327,7 +327,7 @@ R600InstrInfo::InsertBranch(MachineBasicBlock &MBB,
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} else {
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MachineInstr *PredSet = findFirstPredicateSetterFrom(MBB, MBB.end());
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assert(PredSet && "No previous predicate !");
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PredSet->getOperand(1).addTargetFlag(1<<4);
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AddFlag(PredSet, 1, MO_FLAG_PUSH);
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PredSet->getOperand(2).setImm(Cond[1].getImm());
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BuildMI(&MBB, DL, get(AMDGPU::JUMP))
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.addMBB(TBB)
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@ -356,8 +356,7 @@ R600InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const
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case AMDGPU::JUMP:
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if (isPredicated(I)) {
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MachineInstr *predSet = findFirstPredicateSetterFrom(MBB, I);
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char flag = predSet->getOperand(1).getTargetFlags() & (~(1<<4));
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predSet->getOperand(1).setTargetFlags(flag);
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ClearFlag(predSet, 1, MO_FLAG_PUSH);
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}
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I->eraseFromParent();
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break;
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@ -375,8 +374,7 @@ R600InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const
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case AMDGPU::JUMP:
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if (isPredicated(I)) {
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MachineInstr *predSet = findFirstPredicateSetterFrom(MBB, I);
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char flag = predSet->getOperand(1).getTargetFlags() & (~(1<<4));
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predSet->getOperand(1).setTargetFlags(flag);
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ClearFlag(predSet, 1, MO_FLAG_PUSH);
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}
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I->eraseFromParent();
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break;
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@ -532,14 +530,20 @@ bool R600InstrInfo::HasFlagOperand(const MachineInstr &MI) const
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return GET_FLAG_OPERAND_IDX(MI) != 0;
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}
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void R600InstrInfo::AddFlag(MachineInstr *MI, unsigned Operand,
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unsigned Flag) const
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MachineOperand &R600InstrInfo::GetFlagOp(MachineInstr *MI) const
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{
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unsigned FlagIndex = GET_FLAG_OPERAND_IDX(*MI);
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assert(FlagIndex != 0 &&
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"Instruction flags not supported for this instruction");
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MachineOperand &FlagOp = MI->getOperand(FlagIndex);
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assert(FlagOp.isImm());
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return FlagOp;
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}
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void R600InstrInfo::AddFlag(MachineInstr *MI, unsigned Operand,
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unsigned Flag) const
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{
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MachineOperand &FlagOp = GetFlagOp(MI);
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FlagOp.setImm(FlagOp.getImm() | (Flag << (NUM_MO_FLAGS * Operand)));
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}
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@ -554,3 +558,12 @@ bool R600InstrInfo::IsFlagSet(const MachineInstr &MI, unsigned Operand,
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return !!((MI.getOperand(FlagIndex).getImm() >>
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(NUM_MO_FLAGS * Operand)) & Flag);
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}
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void R600InstrInfo::ClearFlag(MachineInstr *MI, unsigned Operand,
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unsigned Flag) const
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{
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MachineOperand &FlagOp = GetFlagOp(MI);
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unsigned InstFlags = FlagOp.getImm();
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InstFlags &= ~(Flag << (NUM_MO_FLAGS * Operand));
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FlagOp.setImm(InstFlags);
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}
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@ -119,6 +119,12 @@ namespace llvm {
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///IsFlagSet - Determine if the specified flag is set on this Operand.
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bool IsFlagSet(const MachineInstr &MI, unsigned Operand, unsigned Flag) const;
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///GetFlagOp - Return the operand containing the flags for this instruction.
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MachineOperand &GetFlagOp(MachineInstr *MI) const;
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///ClearFlag - Clear the specified flag on the instruction.
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void ClearFlag(MachineInstr *MI, unsigned Operand, unsigned Flag) const;
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};
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} // End llvm namespace
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