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radeon/llvm: Cleanup R600Instructions.td
This commit is contained in:
Tom Stellard
parent
388af5b6f4
commit
167ecf5ba3
2 changed files with 28 additions and 93 deletions
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@ -113,7 +113,6 @@ bool R600InstrInfo::isPlaceHolderOpcode(unsigned Opcode) const
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switch (Opcode) {
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default: return false;
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case AMDGPU::RETURN:
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case AMDGPU::LAST:
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case AMDGPU::MASK_WRITE:
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case AMDGPU::RESERVE_REG:
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return true;
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@ -179,10 +179,10 @@ class EG_CF_RAT <bits <8> cf_inst, bits <6> rat_inst, bits<4> rat_id, dag outs,
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bits<1> MARK;
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bits<1> BARRIER;
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/* CF_ALLOC_EXPORT_WORD0_RAT */
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// CF_ALLOC_EXPORT_WORD0_RAT
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let Inst{3-0} = rat_id;
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let Inst{9-4} = rat_inst;
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let Inst{10} = 0; /* Reserved */
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let Inst{10} = 0; // Reserved
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let Inst{12-11} = RIM;
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let Inst{14-13} = TYPE;
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let Inst{21-15} = RW_GPR;
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@ -190,7 +190,7 @@ class EG_CF_RAT <bits <8> cf_inst, bits <6> rat_inst, bits<4> rat_id, dag outs,
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let Inst{29-23} = INDEX_GPR;
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let Inst{31-30} = ELEM_SIZE;
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/* CF_ALLOC_EXPORT_WORD1_BUF */
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// CF_ALLOC_EXPORT_WORD1_BUF
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let Inst{43-32} = ARRAY_SIZE;
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let Inst{47-44} = COMP_MASK;
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let Inst{51-48} = BURST_COUNT;
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@ -201,21 +201,6 @@ class EG_CF_RAT <bits <8> cf_inst, bits <6> rat_inst, bits<4> rat_id, dag outs,
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let Inst{63} = BARRIER;
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}
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/*
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def store_global : PatFrag<(ops node:$value, node:$ptr),
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(store node:$value, node:$ptr),
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[{
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const Value *Src;
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const PointerType *Type;
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if ((src = cast<StoreSDNode>(N)->getSrcValue() &&
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PT = dyn_cast<PointerType>(Src->getType()))) {
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return PT->getAddressSpace() == 1;
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}
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return false;
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}]>;
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*/
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def load_param : PatFrag<(ops node:$ptr),
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(load node:$ptr),
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[{
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@ -227,36 +212,6 @@ def load_param : PatFrag<(ops node:$ptr),
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return false;
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}]>;
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//class EG_CF <bits<32> inst, string asm> :
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// InstR600 <inst, (outs), (ins), asm, []>;
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/* XXX: We will use this when we emit the real ISA.
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bits<24> ADDR = 0;
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bits<3> JTS = 0;
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bits<3> PC = 0;
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bits<5> CF_CONS = 0;
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bits<2> COND = 0;
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bits<6> COUNT = 0;
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bits<1> VPM = 0;
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bits<1> EOP = 0;
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bits<8> CF_INST = 0;
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bits<1> WQM = 0;
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bits<1> B = 0;
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let Inst{23-0} = ADDR;
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let Inst{26-24} = JTS;
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let Inst{34-32} = PC;
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let Inst{39-35} = CF_CONST;
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let Inst{41-40} = COND;
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let Inst{47-42} = COUNT;
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let Inst{52} = VPM;
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let Inst{53} = EOP;
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let Inst{61-54} = CF_INST;
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let Inst{62} = WQM;
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let Inst{63} = B;
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//}
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*/
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def isR600 : Predicate<"Subtarget.device()"
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"->getGeneration() == AMDGPUDeviceInfo::HD4XXX">;
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def isR700 : Predicate<"Subtarget.device()"
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@ -279,9 +234,10 @@ def isR600toCayman : Predicate<
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let Predicates = [isR600toCayman] in {
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/* ------------------------------------------- */
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/* Common Instructions R600, R700, Evergreen, Cayman */
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/* ------------------------------------------- */
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//===----------------------------------------------------------------------===//
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// Common Instructions R600, R700, Evergreen, Cayman
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//===----------------------------------------------------------------------===//
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def ADD : R600_2OP <
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0x0, "ADD",
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[(set R600_Reg32:$dst, (fadd R600_Reg32:$src0, R600_Reg32:$src1))]
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@ -308,10 +264,9 @@ def MIN : R600_2OP <
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[(set R600_Reg32:$dst, (AMDGPUfmin R600_Reg32:$src0, R600_Reg32:$src1))]
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>;
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/* For the SET* instructions there is a naming conflict in TargetSelectionDAG.td,
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* so some of the instruction names don't match the asm string.
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* XXX: Use the defs in TargetSelectionDAG.td instead of intrinsics.
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*/
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// For the SET* instructions there is a naming conflict in TargetSelectionDAG.td,
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// so some of the instruction names don't match the asm string.
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// XXX: Use the defs in TargetSelectionDAG.td instead of intrinsics.
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def SETE : R600_2OP <
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0x08, "SETE",
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@ -492,8 +447,9 @@ def CNDE_INT : R600_3OP <
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(select R600_Reg32:$src0, R600_Reg32:$src2, R600_Reg32:$src1))]
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>;
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/* Texture instructions */
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//===----------------------------------------------------------------------===//
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// Texture instructions
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//===----------------------------------------------------------------------===//
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def TEX_LD : R600_TEX <
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0x03, "TEX_LD",
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@ -568,7 +524,9 @@ def TEX_SAMPLE_C_G : R600_TEX <
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[]
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>;
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/* Helper classes for common instructions */
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//===----------------------------------------------------------------------===//
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// Helper classes for common instructions
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//===----------------------------------------------------------------------===//
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class MUL_LIT_Common <bits<32> inst> : R600_3OP <
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inst, "MUL_LIT",
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@ -738,8 +696,9 @@ class COS_Common <bits<32> inst> : R600_1OP <
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let Trig = 1;
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}
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/* Helper patterns for complex intrinsics */
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/* -------------------------------------- */
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//===----------------------------------------------------------------------===//
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// Helper patterns for complex intrinsics
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//===----------------------------------------------------------------------===//
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class DIV_Common <InstR600 recip_ieee> : Pat<
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(int_AMDGPU_div R600_Reg32:$src0, R600_Reg32:$src1),
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@ -756,9 +715,9 @@ class TGSI_LIT_Z_Common <InstR600 mul_lit, InstR600 log_clamped, InstR600 exp_ie
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(exp_ieee (mul_lit (log_clamped (MAX R600_Reg32:$src_y, (f32 ZERO))), R600_Reg32:$src_w, R600_Reg32:$src_x))
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>;
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/* ---------------------- */
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/* R600 / R700 Only Instructions */
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/* ---------------------- */
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//===----------------------------------------------------------------------===//
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// R600 / R700 Instructions
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//===----------------------------------------------------------------------===//
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let Predicates = [isR600] in {
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@ -835,9 +794,9 @@ def RECIP_UINT_eg : RECIP_UINT_Common<0x94>;
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} // End Predicates = [isEG]
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/* ------------------------------- */
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/* Evergreen / Cayman Instructions */
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/* ------------------------------- */
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//===----------------------------------------------------------------------===//
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// Evergreen / Cayman Instructions
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//===----------------------------------------------------------------------===//
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let Predicates = [isEGorCayman] in {
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@ -926,7 +885,7 @@ def RAT_WRITE_CACHELESS_eg : EG_CF_RAT <0x57, 0x2, 0, (outs),
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[]>
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{
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let RIM = 0;
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/* XXX: Have a separate instruction for non-indexed writes. */
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// XXX: Have a separate instruction for non-indexed writes.
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let TYPE = 1;
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let RW_REL = 0;
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let ELEM_SIZE = 0;
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@ -940,6 +899,7 @@ def RAT_WRITE_CACHELESS_eg : EG_CF_RAT <0x57, 0x2, 0, (outs),
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}
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} // End usesCustomInserter = 1
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// i32 global_store
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def : Pat <
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(global_store (i32 R600_TReg32_X:$val), R600_TReg32_X:$ptr),
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@ -1128,31 +1088,7 @@ def : Pat <
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} // End isCayman
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/* Other Instructions */
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let isCodeGenOnly = 1 in {
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/*
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def SWIZZLE : AMDGPUShaderInst <
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(outs GPRV4F32:$dst),
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(ins GPRV4F32:$src0, i32imm:$src1),
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"SWIZZLE $dst, $src0, $src1",
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[(set GPRV4F32:$dst, (int_AMDGPU_swizzle GPRV4F32:$src0, imm:$src1))]
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>;
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*/
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def LAST : AMDGPUShaderInst <
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(outs),
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(ins),
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"LAST",
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[]
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>;
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def GET_CHAN : AMDGPUShaderInst <
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(outs R600_Reg32:$dst),
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(ins R600_Reg128:$src0, i32imm:$src1),
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"GET_CHAN $dst, $src0, $src1",
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[]
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>;
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def MULLIT : AMDGPUShaderInst <
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(outs R600_Reg128:$dst),
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@ -1218,7 +1154,7 @@ def MASK_WRITE : AMDGPUShaderInst <
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} // End usesCustomInserter = 1
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//===---------------------------------------------------------------------===//
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// return instruction
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// Return instruction
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//===---------------------------------------------------------------------===//
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let isTerminator = 1, isReturn = 1, isBarrier = 1, hasCtrlDep = 1 in {
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def RETURN : ILFormat<(outs), (ins variable_ops),
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