3199 commits

Author	SHA1	Message	Date
Marek Olšák	c1237256cb	ac/nir/tess: execute the tess level workgroup vote on all chips ... It will be used to skip stores for discarded patches. Reviewed-by: Timur Kristóf <timur.kristof@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34780>	2025-06-07 16:29:39 +00:00
Marek Olšák	9c16228359	ac/nir/tess: write TCS per-vertex outputs to memory as vec4 stores at the end ... This improves write throughput for TCS outputs. It follows the same idea as attribute stores in hw GS. The improvement is easily measurable with a microbenchmark. It also has the advantage that multiple output stores to the same address don't result in multiple memory stores. Each output components gets only one memory store at the end of the shader. Reviewed-by: Timur Kristóf <timur.kristof@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34780>	2025-06-07 16:29:39 +00:00
Marek Olšák	509f0e62ad	ac/nir/tess: allow passing explicit patch_offset to VMEM/LDS offset calculations ... Reviewed-by: Timur Kristóf <timur.kristof@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34780>	2025-06-07 16:29:39 +00:00
Marek Olšák	a59464b6e3	radv,radeonsi: precompute and pass TCS per-vertex output stride via a user SGPR ... It's a stride of 1 output, which isn't 16. It's 16 * num_threads, aligned to 256. tcs_offchip_layout has 5 unused bits, so let's use them. Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Reviewed-by: Timur Kristóf <timur.kristof@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34780>	2025-06-07 16:29:39 +00:00
Marek Olšák	742227c65c	radv,radeonsi: make TCS_OFFCHIP_LAYOUT_NUM_PATCHES not off by one ... We never use 128 anyway. Reviewed-by: Timur Kristóf <timur.kristof@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34780>	2025-06-07 16:29:39 +00:00
Marek Olšák	534b282573	ac/nir/tess: adjust memory layout of TCS outputs to have aligned store offsets ... There is a comment that explains it. Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Reviewed-by: Timur Kristóf <timur.kristof@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34780>	2025-06-07 16:29:38 +00:00
Marek Olšák	80236f2367	ac/nir/tess: add if/endif for HS threads in NIR instead of ACO/LLVM ... This just removes the if/endif wrapping for LLVM, and hopefully the ACO change does the same thing. ACO had redundant code in endif_merged_wave_info, which is removed here. Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Reviewed-by: Timur Kristóf <timur.kristof@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34780>	2025-06-07 16:29:38 +00:00
Marek Olšák	cd366b57d9	ac/nir: implement load_subgroup_id/local_invocation_index for TCS on gfx6-10.x ... Reviewed-by: Timur Kristóf <timur.kristof@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34780>	2025-06-07 16:29:38 +00:00
Marek Olšák	c3034fa82c	amd: replace most u_bit_consecutive* with BITFIELD_MASK/RANGE ... Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35346>	2025-06-04 17:46:38 +00:00
Karol Herbst	4f5ce2d5aa	ac/nir: fix unaligned single component load/stores ... This fixes two problems: 1. we need to lower the bit_size according to the alignment. 2. num_components could end up being 0, so we need to round up instead. Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/13102 Reviewed-by: Rhys Perry <pendingchaos02@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34976>	2025-06-03 13:14:31 +00:00
Samuel Pitoiset	47f5d25f93	radv,radeonsi: emit UPDATE_DB_SUMMARIZER_TIMEOUT on GFX12 ... This try to mitigate the HiZ GPU hang by increasing a timeout. Loosely based on PAL but I can confirm it delays the hang when BOTTOM_OF_PIPE_TS is used as a workaround. This must be emitted when the GFX queue is idle. Cc: mesa-stable Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35212>	2025-06-02 07:30:18 +00:00
David Rosca	8f4e251c98	radeonsi/vcn: Support disabling HEVC dependent slice segments ... With older FW this needs to be always enabled, but it can now be disabled when using the new separate header instructions for dependent_slice_segment_flag and slice_segment_address. Reviewed-by: Ruijing Dong <ruijing.dong@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35072>	2025-05-30 08:29:53 +00:00
Samuel Pitoiset	fe2c93a788	ac/nir: enable 64-bit lowering for bitfield_extract ... Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35187>	2025-05-29 08:45:41 +02:00
Yogesh Mohan Marimuthu	1af419deed	ac: for userq do not set info->has_fw_based_shadowing ... register shadow enabling for user queue is different code flow than kernel queue. In case of kernel queue preamble ib is initialized which is not requried for kernel queue. Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34803>	2025-05-27 14:25:50 +00:00
Yogesh Mohan Marimuthu	137907945f	ac: add AMD_USERQ env var to enable user queue ... user queue is enabled only if AMD_USERQ env var is set and Kernel supports user queue. Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34803>	2025-05-27 14:25:50 +00:00
Yogesh Mohan Marimuthu	97c48c5aa7	ac: fix getting mcbp info for userq ... Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34803>	2025-05-27 14:25:50 +00:00
Samuel Pitoiset	235f70e475	ac/gpu_info: add has_cp_dma_with_null_prt_bug ... CP DMA is broken on GFX8-9 with NULL PRT pages. The workaround is to use compute instead. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35071>	2025-05-21 09:41:23 +00:00
Samuel Pitoiset	e345b03c89	ac/gpu_info: rename has_zerovram_support to has_default_zerovram_support ... To avoid confusion between RADEON_FLAG_ZERO_VRAM and default VRAM allocation clears since AMDGPU 3.59+. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35021>	2025-05-20 12:43:59 +00:00
Samuel Pitoiset	b79f1a3af3	ac/gpu_info: allow 32-bit predicate on GFX11+ ... This is natively supported. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34953>	2025-05-15 05:51:04 +00:00
Marek Olšák	6e4154b7ef	ac/nir: fix export_ps_outputs not preserving divergence metadata ... Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34492>	2025-05-14 20:19:16 +00:00
David Rosca	69455e8208	ac/uvd: Add ac_uvd_alloc_stream_handle ... Cc: mesa-stable Reviewed-by: Ruijing Dong <ruijing.dong@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34807>	2025-05-13 09:36:47 +00:00
Samuel Pitoiset	4b16de5e0d	ac/gpu_info: add has_zerovram_support ... AMDGPU 3.59.0+ clears VRAM on allocations. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34896>	2025-05-12 06:53:55 +00:00
Boyuan Zhang	e1f9dde5c0	radeonsi/vcn: add drm keyblob for cenc ... Add new message buffer for drm keyblob which contains local policy for cenc Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: Ruijing Dong <ruijing.dong@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34854>	2025-05-09 17:54:14 +00:00
Boyuan Zhang	2b6ecc8269	radeonsi/vcn: add drm key for cenc ... Add new function to handle drm message buffer for cenc, which is different than legacy mode. Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: Ruijing Dong <ruijing.dong@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34854>	2025-05-09 17:54:14 +00:00
Boyuan Zhang	d6e2438113	radeonsi/vcn: add subsample for cenc ... Create new buffer for subsample parameters and submit it for cenc decryption Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com> Reviewed-by: Ruijing Dong <ruijing.dong@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34854>	2025-05-09 17:54:14 +00:00
Georg Lehmann	a2209547db	ac/nir: enable nir_op_bfdot2_bfadd ... Reviewed-by: Rhys Perry <pendingchaos02@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34768>	2025-05-09 11:20:26 +00:00
Georg Lehmann	f364303084	ac/nir: set lower_bfloat16_conversions ... Reviewed-by: Rhys Perry <pendingchaos02@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34768>	2025-05-09 11:20:26 +00:00
Rhys Perry	3b42626973	ac/nir: allow 8/16-bit smem loads ... fossil-db (gfx1201): Totals from 295 (0.37% of 79377) affected shaders: Instrs: 314018 -> 313355 (-0.21%); split: -0.22%, +0.00% CodeSize: 1697996 -> 1696528 (-0.09%); split: -0.11%, +0.02% Latency: 4197719 -> 4197106 (-0.01%) InvThroughput: 1258891 -> 1258744 (-0.01%) PreSGPRs: 12232 -> 12230 (-0.02%) SALU: 66762 -> 66269 (-0.74%) Signed-off-by: Rhys Perry <pendingchaos02@gmail.com> Reviewed-by: Georg Lehmann <dadschoorse@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34162>	2025-05-08 13:30:50 +00:00
Rhys Perry	5b116c4de9	ac/nir: allow vectorization of unsupported 8/16-bit loads ... These can later be lowered to a vectorized 32-bit load. fossil-db (gfx1201): Totals from 1259 (1.59% of 79377) affected shaders: MaxWaves: 36821 -> 36817 (-0.01%) Instrs: 4363702 -> 4355749 (-0.18%); split: -0.23%, +0.05% CodeSize: 22779980 -> 22706504 (-0.32%); split: -0.37%, +0.05% VGPRs: 69672 -> 69792 (+0.17%); split: -0.02%, +0.19% SpillSGPRs: 675 -> 673 (-0.30%) Latency: 26684053 -> 26663819 (-0.08%); split: -0.11%, +0.03% InvThroughput: 5617687 -> 5614798 (-0.05%); split: -0.10%, +0.04% VClause: 106830 -> 106654 (-0.16%); split: -0.17%, +0.00% SClause: 75523 -> 75495 (-0.04%); split: -0.04%, +0.01% Copies: 323199 -> 323525 (+0.10%); split: -0.10%, +0.20% Branches: 109475 -> 109480 (+0.00%); split: -0.00%, +0.01% PreSGPRs: 55036 -> 55040 (+0.01%) PreVGPRs: 47538 -> 47582 (+0.09%); split: -0.12%, +0.21% VALU: 2377777 -> 2389977 (+0.51%); split: -0.02%, +0.53% SALU: 578272 -> 578385 (+0.02%); split: -0.02%, +0.04% VMEM: 190065 -> 181204 (-4.66%) SMEM: 99709 -> 99565 (-0.14%) VOPD: 244 -> 243 (-0.41%); split: +0.41%, -0.82% Signed-off-by: Rhys Perry <pendingchaos02@gmail.com> Reviewed-by: Georg Lehmann <dadschoorse@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34162>	2025-05-08 13:30:50 +00:00
Rhys Perry	6dbf44ad9c	ac/nir: allow less than one register of overfetch ... This is to allow vectorization of 8/16-bit loads, which can later be cheaply lowered to a 32-bit load. fossil-db (gfx1201): Totals from 178 (0.22% of 79377) affected shaders: MaxWaves: 4138 -> 4102 (-0.87%) Instrs: 619714 -> 617917 (-0.29%); split: -0.32%, +0.03% CodeSize: 3364396 -> 3352724 (-0.35%); split: -0.38%, +0.03% VGPRs: 12896 -> 12980 (+0.65%); split: -0.19%, +0.84% SpillSGPRs: 546 -> 545 (-0.18%) Latency: 7589585 -> 7406076 (-2.42%); split: -2.45%, +0.04% InvThroughput: 1926356 -> 1879866 (-2.41%); split: -2.42%, +0.00% VClause: 12301 -> 11750 (-4.48%) SClause: 13614 -> 13583 (-0.23%); split: -0.45%, +0.22% Copies: 82207 -> 82265 (+0.07%); split: -0.10%, +0.17% Branches: 19284 -> 19266 (-0.09%) PreSGPRs: 9525 -> 9457 (-0.71%) PreVGPRs: 12366 -> 12421 (+0.44%) VALU: 347928 -> 348020 (+0.03%); split: -0.01%, +0.04% SALU: 82620 -> 82519 (-0.12%); split: -0.19%, +0.07% VMEM: 22248 -> 21430 (-3.68%) SMEM: 17951 -> 17843 (-0.60%) Signed-off-by: Rhys Perry <pendingchaos02@gmail.com> Reviewed-by: Georg Lehmann <dadschoorse@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34162>	2025-05-08 13:30:50 +00:00
Rhys Perry	ddef4bddf8	ac/nir: round components when lowering 8/16-bit loads to 32-bit ... Signed-off-by: Rhys Perry <pendingchaos02@gmail.com> Reviewed-by: Georg Lehmann <dadschoorse@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34162>	2025-05-08 13:30:50 +00:00
Jesse.Zhang	d8624e6a79	winsys/amdgpu: Add support for queue priority in Mesa ... This patch adds support for queue priority levels in Mesa's AMDGPU winsys layer. The changes include: 1. Updated ac_drm_create_userqueue() to accept and pass through flags parameter 2. Modified amdgpu_userq_init() to use the flags when creating queues 3. Added flags field to amdgpu_userq struct to store priority settings 4. Updated header definitions to match kernel UAPI changes This aligns with the kernel changes provided by Alex: https://lists.freedesktop.org/archives/amd-gfx/2025-April/122782.html https://lists.freedesktop.org/archives/amd-gfx/2025-April/122780.html https://lists.freedesktop.org/archives/amd-gfx/2025-April/122786.html v2: We only need 1 normal priority queue and 1 TMZ normal priority queue.(Marek Olšák) v3: Simplified to only support normal priority queues v4: use a local variable instead of being in struct amdgpu_userq.(Marek Olšák) v5: rebase the latest main branch. Signed-off-by: Jesse.Zhang <Jesse.zhang@amd.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34568>	2025-05-08 04:29:29 +00:00
Marek Olšák	870d17012a	ac: adjust maximum HS workgroup size ... This has no effect on triangles because max 64 patches implied max 192 threads, but it improves performance for cases when the number of threads per patch is > 3. This improves the score for gfxbench5 "gl_tess_off" (offscreen) by 11% on Navi48. Reviewed-by: Timur Kristóf <timur.kristof@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34863>	2025-05-08 02:54:13 +00:00
Marek Olšák	dfc3c1135c	ac/nir/tess: don't pass nir_intrinsic_instr to hs_output_lds_offset ... It will be used without intrinsics. Reviewed-by: Timur Kristóf <timur.kristof@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34863>	2025-05-08 02:54:13 +00:00
Marek Olšák	4bbe497d9b	ac/nir/tess: don't pass nir_intrinsic_instr to VMEM IO calc helpers ... These will be used without intrinsics. Reviewed-by: Timur Kristóf <timur.kristof@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34863>	2025-05-08 02:54:13 +00:00
Marek Olšák	360494f50d	ac/nir/tess: remove unused variables ... Reviewed-by: Timur Kristóf <timur.kristof@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34863>	2025-05-08 02:54:12 +00:00
Marek Olšák	f58c0cbb6a	nir: split *_accessed_indirectly* bitmasks into *_read/written_indirectly* ... for AMD Reviewed-by: Timur Kristóf <timur.kristof@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34863>	2025-05-08 02:54:12 +00:00
Konstantin Seurer	84b9c281fe	radv: Return VK_ERROR_INCOMPATIBLE_DRIVER for unsupported devices ... VK_ERROR_INITIALIZATION_FAILED will fail physical device enumeration. Returning VK_ERROR_INCOMPATIBLE_DRIVER means that the driver can still be used on supported GPUs when multiple GPUs are installed. cc: mesa-stable Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34783>	2025-05-07 08:26:33 +02:00
Marek Olšák	7f0de1a512	ac: remove gfx11_emulate_clear_state ... We don't use CLEAR_STATE on gfx11 anymore. Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34589>	2025-05-02 18:40:11 +00:00
Marek Olšák	5e487dbc49	amd: stop using CLEAR_STATE on gfx11 ... It's not allowed with user queues, so this will make it simpler to support user queues. There are 2 groups of registers: - those that are never set by radv and radeonsi - those are now set in the shared preamble - those that are set by radv but not radeonsi - those are now set in the radeonsi preamble Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34589>	2025-05-02 18:40:11 +00:00
Pierre-Eric Pelloux-Prayer	992a340eab	ac/nir: init blake3 for cs blit shader ... Reviewed-by: Marek Olšák <marek.olsak@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34574>	2025-04-23 07:59:10 +00:00
Marek Olšák	2948f7ce96	ac/gpu_info: rename tess ring variables, fold double_offchip_wg ... Reviewed-by: Timur Kristóf <timur.kristof@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34544>	2025-04-19 22:55:00 -04:00
Marek Olšák	d2e016c37d	ac/nir: don't store tess levels for TES in TCS if no_varying is set ... Reviewed-by: Timur Kristóf <timur.kristof@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34544>	2025-04-19 22:55:00 -04:00
Marek Olšák	be8977811b	ac/nir: remove shader_info parameter from ac_nir_compute_tess_wg_info ... Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Reviewed-by: Timur Kristóf <timur.kristof@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34544>	2025-04-19 22:55:00 -04:00
Marek Olšák	6d9e708642	ac/gpu_info: reduce the tess offchip ring size and compute it proportionately ... .. to the CU count. We allocated too much. This reduces the tess offchip ring size as follows (examples): - GFX11-12: - Navi31, Navi33, and Navi48 get 75% decrease. - Navi32 gets 68.75% decrease. - Phoenix gets 81.25% decrease. - Phoenix2 gets 93.75% decrease. - GFX10.3: - Navi21 and Navi22 get 37.5% decrease. - Navi23 and Navi24 get 50% decrease. - Rembrandt gets 62.5% decrease. - VanGogh gets 75% decrease. - Raphael gets 93.75% decrease. - GFX8-9: - Vega10 gets 0% decrease. - Vega20 gets 49.6% decrease. - Raven gets 65.3% decrease. - Raven2 gets 93.7% decrease. - Stoney gets 81% decrease. No difference in performance was measured. Reviewed-by: Timur Kristóf <timur.kristof@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34544>	2025-04-19 22:55:00 -04:00
Marek Olšák	9333c0a1ed	ac/gpu_info: compute the tess factor ring size proportionately to the CU count ... No change in the size on GPUs with 16 CUs per SE such as Navi31 and Navi48. Navi21 and Navi32 get 25% increase. (20 CUs per SE) APUs get a significant decrease. For example: - Phoenix gets 25% decrease - Vangogh gets 50% decrease - Phoenix2 gets 75% decrease - Raphael and Stoney get 87.5% decrease Reviewed-by: Timur Kristóf <timur.kristof@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34544>	2025-04-19 22:55:00 -04:00
Marek Olšák	5fb2de9454	ac/nir: don't include TCS offchip size in LDS_SIZE ... This drastically reduces LDS usage for TCS. Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Reviewed-by: Timur Kristóf <timur.kristof@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34544>	2025-04-19 22:55:00 -04:00
Marek Olšák	b8f2fb81f6	ac/gpu_info: print tessellation ring info ... Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Reviewed-by: Timur Kristóf <timur.kristof@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34544>	2025-04-19 22:55:00 -04:00
Marek Olšák	b8d15fee3d	ac: minor cleanup of ac_compute_num_tess_patches ... No change in behavior. Reviewed-by: Timur Kristóf <timur.kristof@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34544>	2025-04-19 22:55:00 -04:00
Marek Olšák	a905a17f39	ac: use HS offchip wg size from radeon_info in ac_compute_num_tess_patches ... Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Reviewed-by: Timur Kristóf <timur.kristof@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34544>	2025-04-19 22:55:00 -04:00