fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2025-12-30 10:00:14 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

nir: split *_accessed_indirectly* bitmasks into *_read/written_indirectly*

Browse source 
for AMD

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34863>
This commit is contained in:
Marek Olšák 2025-04-21 02:44:18 -04:00 • committed by Marge Bot
parent afd8fefb79
commit f58c0cbb6a
8 changed files with 54 additions and 36 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

3
src/amd/common/nir/ac_nir_lower_ngg_mesh.c
View file

@ -1365,7 +1365,8 @@ ac_nir_lower_ngg_mesh(nir_shader *shader,
bool uses_cull = shader->info.outputs_written & BITFIELD64_BIT(VARYING_SLOT_CULL_PRIMITIVE);
/* Can't handle indirect register addressing, pretend as if they were cross-invocation. */
uint64_t cross_invocation_access = shader->info.mesh.ms_cross_invocation_output_access |
shader->info.outputs_accessed_indirectly;
(shader->info.outputs_read_indirectly |
shader->info.outputs_written_indirectly);
unsigned max_vertices = shader->info.mesh.max_vertices_out;
unsigned max_primitives = shader->info.mesh.max_primitives_out;

18
src/amd/vulkan/radv_shader_info.c
View file

@ -1800,14 +1800,16 @@ radv_link_shaders_info(struct radv_device *device, struct radv_shader_stage *pro
vs_stage->nir->info.float_controls_execution_mode == tcs_stage->nir->info.float_controls_execution_mode;
if (vs_stage->info.vs.tcs_in_out_eq) {
vs_stage->info.vs.tcs_inputs_via_temp = vs_stage->nir->info.outputs_written &
~vs_stage->nir->info.outputs_accessed_indirectly &
tcs_stage->nir->info.tess.tcs_same_invocation_inputs_read;
vs_stage->info.vs.tcs_inputs_via_lds = tcs_stage->nir->info.tess.tcs_cross_invocation_inputs_read |
(tcs_stage->nir->info.tess.tcs_same_invocation_inputs_read &
tcs_stage->nir->info.inputs_read_indirectly) |
(tcs_stage->nir->info.tess.tcs_same_invocation_inputs_read &
vs_stage->nir->info.outputs_accessed_indirectly);
vs_stage->info.vs.tcs_inputs_via_temp =
vs_stage->nir->info.outputs_written &
~(vs_stage->nir->info.outputs_read_indirectly | vs_stage->nir->info.outputs_written_indirectly) &
tcs_stage->nir->info.tess.tcs_same_invocation_inputs_read;
vs_stage->info.vs.tcs_inputs_via_lds =
tcs_stage->nir->info.tess.tcs_cross_invocation_inputs_read |
(tcs_stage->nir->info.tess.tcs_same_invocation_inputs_read &
tcs_stage->nir->info.inputs_read_indirectly) |
(tcs_stage->nir->info.tess.tcs_same_invocation_inputs_read &
(vs_stage->nir->info.outputs_read_indirectly | vs_stage->nir->info.outputs_written_indirectly));
}
}
}

29
src/compiler/nir/nir_gather_info.c
View file

@ -163,11 +163,11 @@ set_io_mask(nir_shader *shader, nir_variable *var, int offset, int len,
if (is_patch_generic) {
shader->info.patch_outputs_read |= bitfield;
if (indirect)
shader->info.patch_outputs_accessed_indirectly |= bitfield;
shader->info.patch_outputs_read_indirectly |= bitfield;
} else {
shader->info.outputs_read |= bitfield;
if (indirect)
shader->info.outputs_accessed_indirectly |= bitfield;
shader->info.outputs_written_indirectly |= bitfield;
}
if (cross_invocation && shader->info.stage == MESA_SHADER_TESS_CTRL)
@ -176,11 +176,11 @@ set_io_mask(nir_shader *shader, nir_variable *var, int offset, int len,
if (is_patch_generic) {
shader->info.patch_outputs_written |= bitfield;
if (indirect)
shader->info.patch_outputs_accessed_indirectly |= bitfield;
shader->info.patch_outputs_written_indirectly |= bitfield;
} else if (!var->data.read_only) {
shader->info.outputs_written |= bitfield;
if (indirect)
shader->info.outputs_accessed_indirectly |= bitfield;
shader->info.outputs_written_indirectly |= bitfield;
if (cross_invocation && shader->info.stage == MESA_SHADER_TESS_CTRL)
shader->info.tess.tcs_cross_invocation_outputs_written |= bitfield;
@ -585,13 +585,13 @@ gather_intrinsic_info(nir_intrinsic_instr *instr, nir_shader *shader,
!is_patch_special) {
shader->info.patch_outputs_read |= slot_mask;
if (!nir_src_is_const(*nir_get_io_offset_src(instr)))
shader->info.patch_outputs_accessed_indirectly |= slot_mask;
shader->info.patch_outputs_read_indirectly |= slot_mask;
} else {
shader->info.outputs_read |= slot_mask;
shader->info.outputs_read_16bit |= slot_mask_16bit;
if (!nir_src_is_const(*nir_get_io_offset_src(instr))) {
shader->info.outputs_accessed_indirectly |= slot_mask;
shader->info.outputs_accessed_indirectly_16bit |= slot_mask_16bit;
shader->info.outputs_read_indirectly |= slot_mask;
shader->info.outputs_read_indirectly_16bit |= slot_mask_16bit;
}
}
@ -621,15 +621,15 @@ gather_intrinsic_info(nir_intrinsic_instr *instr, nir_shader *shader,
!is_patch_special) {
shader->info.patch_outputs_written |= slot_mask;
if (!nir_src_is_const(*nir_get_io_offset_src(instr)))
shader->info.patch_outputs_accessed_indirectly |= slot_mask;
shader->info.patch_outputs_written_indirectly |= slot_mask;
} else {
shader->info.outputs_written |= slot_mask;
shader->info.outputs_written_16bit |= slot_mask_16bit;
if (instr->intrinsic == nir_intrinsic_store_per_primitive_output)
shader->info.per_primitive_outputs |= slot_mask;
if (!nir_src_is_const(*nir_get_io_offset_src(instr))) {
shader->info.outputs_accessed_indirectly |= slot_mask;
shader->info.outputs_accessed_indirectly_16bit |= slot_mask_16bit;
shader->info.outputs_written_indirectly |= slot_mask;
shader->info.outputs_written_indirectly_16bit |= slot_mask_16bit;
}
}
@ -999,15 +999,18 @@ nir_shader_gather_info(nir_shader *shader, nir_function_impl *entrypoint)
shader->info.outputs_written_16bit = 0;
shader->info.outputs_read_16bit = 0;
shader->info.inputs_read_indirectly_16bit = 0;
shader->info.outputs_accessed_indirectly_16bit = 0;
shader->info.outputs_read_indirectly_16bit = 0;
shader->info.outputs_written_indirectly_16bit = 0;
shader->info.patch_outputs_read = 0;
shader->info.patch_inputs_read = 0;
shader->info.patch_outputs_written = 0;
BITSET_ZERO(shader->info.system_values_read);
shader->info.inputs_read_indirectly = 0;
shader->info.outputs_accessed_indirectly = 0;
shader->info.outputs_read_indirectly = 0;
shader->info.outputs_written_indirectly = 0;
shader->info.patch_inputs_read_indirectly = 0;
shader->info.patch_outputs_accessed_indirectly = 0;
shader->info.patch_outputs_read_indirectly = 0;
shader->info.patch_outputs_written_indirectly = 0;
shader->info.per_primitive_inputs = 0;
shader->info.per_primitive_outputs = 0;

9
src/compiler/nir/nir_print.c
View file

@ -2600,16 +2600,19 @@ print_shader_info(const struct shader_info *info, FILE *fp)
print_nz_x16(fp, "outputs_written_16bit", info->outputs_written_16bit);
print_nz_x16(fp, "outputs_read_16bit", info->outputs_read_16bit);
print_nz_x16(fp, "inputs_read_indirectly_16bit", info->inputs_read_indirectly_16bit);
print_nz_x16(fp, "outputs_accessed_indirectly_16bit", info->outputs_accessed_indirectly_16bit);
print_nz_x16(fp, "outputs_read_indirectly_16bit", info->outputs_read_indirectly_16bit);
print_nz_x16(fp, "outputs_written_indirectly_16bit", info->outputs_written_indirectly_16bit);
print_nz_x32(fp, "patch_inputs_read", info->patch_inputs_read);
print_nz_x32(fp, "patch_outputs_written", info->patch_outputs_written);
print_nz_x32(fp, "patch_outputs_read", info->patch_outputs_read);
print_nz_x64(fp, "inputs_read_indirectly", info->inputs_read_indirectly);
print_nz_x64(fp, "outputs_accessed_indirectly", info->outputs_accessed_indirectly);
print_nz_x64(fp, "outputs_read_indirectly", info->outputs_read_indirectly);
print_nz_x64(fp, "outputs_written_indirectly", info->outputs_written_indirectly);
print_nz_x64(fp, "patch_inputs_read_indirectly", info->patch_inputs_read_indirectly);
print_nz_x64(fp, "patch_outputs_accessed_indirectly", info->patch_outputs_accessed_indirectly);
print_nz_x64(fp, "patch_outputs_read_indirectly", info->patch_outputs_read_indirectly);
print_nz_x64(fp, "patch_outputs_written_indirectly", info->patch_outputs_written_indirectly);
print_nz_bitset(fp, "textures_used", info->textures_used, ARRAY_SIZE(info->textures_used));
print_nz_bitset(fp, "textures_used_by_txf", info->textures_used_by_txf, ARRAY_SIZE(info->textures_used_by_txf));

9
src/compiler/shader_info.h
View file

@ -101,7 +101,8 @@ typedef struct shader_info {
uint16_t outputs_written_16bit;
uint16_t outputs_read_16bit;
uint16_t inputs_read_indirectly_16bit;
uint16_t outputs_accessed_indirectly_16bit;
uint16_t outputs_read_indirectly_16bit;
uint16_t outputs_written_indirectly_16bit;
/* Which patch inputs are actually read */
uint32_t patch_inputs_read;
@ -113,11 +114,13 @@ typedef struct shader_info {
/* Which inputs are read indirectly (subset of inputs_read) */
uint64_t inputs_read_indirectly;
/* Which outputs are read or written indirectly */
uint64_t outputs_accessed_indirectly;
uint64_t outputs_read_indirectly;
uint64_t outputs_written_indirectly;
/* Which patch inputs are read indirectly (subset of patch_inputs_read) */
uint64_t patch_inputs_read_indirectly;
/* Which patch outputs are read or written indirectly */
uint64_t patch_outputs_accessed_indirectly;
uint64_t patch_outputs_read_indirectly;
uint64_t patch_outputs_written_indirectly;
/** Bitfield of which textures are used */
BITSET_DECLARE(textures_used, 128);

3
src/gallium/auxiliary/nir/nir_to_tgsi_info.c
View file

@ -611,7 +611,8 @@ void nir_tgsi_scan_shader(const struct nir_shader *nir,
info->output_usagemask[i] = 0xf;
}
num_outputs = util_bitcount64(nir->info.outputs_written);
if (nir->info.outputs_accessed_indirectly)
if (nir->info.outputs_read_indirectly ||
nir->info.outputs_written_indirectly)
info->indirect_files |= 1 << TGSI_FILE_OUTPUT;
}

8
src/gallium/drivers/zink/zink_compiler.c
View file

@ -5472,7 +5472,8 @@ rework_io_vars(nir_shader *nir, nir_variable_mode mode, struct zink_shader *zs)
uint64_t inputs_read = nir->info.inputs_read;
uint64_t inputs_read_indirectly = nir->info.inputs_read_indirectly;
uint64_t outputs_accessed = nir->info.outputs_written | nir->info.outputs_read;
uint64_t outputs_accessed_indirectly = nir->info.outputs_accessed_indirectly;
uint64_t outputs_accessed_indirectly = nir->info.outputs_read_indirectly |
nir->info.outputs_written_indirectly;
/* fragment outputs are special: handle separately */
if (mode == nir_var_shader_out && nir->info.stage == MESA_SHADER_FRAGMENT) {
@ -5620,7 +5621,10 @@ rework_io_vars(nir_shader *nir, nir_variable_mode mode, struct zink_shader *zs)
if ((nir->info.stage == MESA_SHADER_TESS_CTRL && mode == nir_var_shader_out) ||
(nir->info.stage == MESA_SHADER_TESS_EVAL && mode == nir_var_shader_in)) {
uint64_t patch_outputs_accessed = nir->info.patch_outputs_read | nir->info.patch_outputs_written;
uint64_t indirect_patch_mask = mode == nir_var_shader_in ? nir->info.patch_inputs_read_indirectly : nir->info.patch_outputs_accessed_indirectly;
uint64_t indirect_patch_mask =
mode == nir_var_shader_in ? nir->info.patch_inputs_read_indirectly
: (nir->info.patch_outputs_read_indirectly |
nir->info.patch_outputs_written_indirectly);
uint64_t patch_mask = mode == nir_var_shader_in ? nir->info.patch_inputs_read : patch_outputs_accessed;
loop_io_var_mask(nir, mode, true, true, indirect_patch_mask);

11
src/panfrost/compiler/bifrost_compile.c
View file

@ -5384,11 +5384,12 @@ bi_optimize_nir(nir_shader *nir, unsigned gpu_id, bool is_blend)
/* We might lower attribute, varying, and image indirects. Use the
* gathered info to skip the extra analysis in the happy path. */
bool any_indirects = nir->info.inputs_read_indirectly ||
nir->info.outputs_accessed_indirectly ||
nir->info.patch_inputs_read_indirectly ||
nir->info.patch_outputs_accessed_indirectly ||
nir->info.images_used[0];
bool any_indirects =
nir->info.inputs_read_indirectly || nir->info.outputs_read_indirectly ||
nir->info.outputs_written_indirectly ||
nir->info.patch_inputs_read_indirectly ||
nir->info.patch_outputs_read_indirectly ||
nir->info.patch_outputs_written_indirectly || nir->info.images_used[0];
if (any_indirects) {
nir_divergence_analysis(nir);