Commit graph

56642 commits

Author SHA1 Message Date
Kenneth Graunke
bd44ac8b5c i965: Don't _swrast_BlitFramebuffer when doing CopyTexSubImage.
The point of copytexsubimage_using_blit_framebuffer is to use a hardware
accelerated BlitFramebuffer path.  If that fails, we shouldn't do a
swrast blit---we should try our CTSI fallback code.

This is especially important for i965 and GLES, where we don't even
create a swrast context.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=77705
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Cc: "10.2" <mesa-stable@lists.freedesktop.org>
2014-05-13 15:32:16 -07:00
Jordan Justen
c51c192891 i965/gen8: Set depth extent field
The depth extent field is used to limit the allowed slice range that
can be rendered to.

With the previous setting, only slice 0 could be rendered.

This fixes piglit amd_vertex_shader_layer-layered-depth-texture-render.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2014-05-13 14:26:41 -07:00
Jordan Justen
294ada2fef i965/gen8 depth: Set depth size based on LOD0 for 3D textures
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2014-05-13 14:25:58 -07:00
Jordan Justen
e6d6ed55ab i965/gen7 depth: Set depth size based on LOD0 for 3D textures
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2014-05-13 14:25:58 -07:00
Jordan Justen
e47d08adef i965/gen8 renderbuffer: Set depth size based on LOD0 for 3D textures
Fixes piglit's
'gl-3.2-layered-rendering-clear-color-all-types 3d mipmapped'

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2014-05-13 14:25:58 -07:00
Jordan Justen
b875f39e29 i965/gen7 renderbuffer: Set depth size based on LOD0 for 3D textures
If blorp is disabled for color clears, then piglit's
'gl-3.2-layered-rendering-clear-color-all-types 3d mipmapped'
will fail.

Currently, gen8 fails similarly on this test because gen8
does not use blorp.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
2014-05-13 14:25:57 -07:00
Rob Clark
521ee86db7 freedreno/a3xx: add point-size
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-05-13 16:54:37 -04:00
Rob Clark
a13a798926 freedreno: update generated headers
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-05-13 16:54:20 -04:00
Bryan Cain
4e974a9cf3 glsl_to_tgsi: remove unnecessary dead code elimination pass
With the more advanced dead code elimination pass already being run,
eliminate_dead_code was making no difference in instruction count, and had
an undesirable O(n^2) runtime. So remove it and rename
eliminate_dead_code_advanced to eliminate_dead_code.

Reviewed-by: Marek Olšák <marek.olsak at amd.com>
2014-05-13 14:57:55 -05:00
José Fonseca
1646f4d0fb ralloc: Omit detailed license information about talloc.
That information misleads source code auditing tools to think that
ralloc itself is released under LGPL v3.

Instead, simply state talloc is not licensed under a permissive license.

v2: Use wording suggested by Kenneth.

Reviewed-by: Brian Paul <brianp@vmware.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
2014-05-13 12:48:38 +01:00
Iago Toral Quiroga
5421617325 i965: Avoid redundant call to brw_merge_inputs() in brw_try_draw_prims()
We always call brw_merge_inputs() right before looping over the primitives but
this can be called inside the loop for each primitive too. In the case we do it
for the first primitive the call is redundant and can be skipped.

Reviewed-by: Eric Anholt <eric@anholt.net>
2014-05-13 10:09:35 +02:00
Iago Toral Quiroga
a143fbb322 glsl: Do not call lhs->variable_referenced() multiple times
Instead take the result from the first call and use it where needed.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-05-13 10:01:02 +02:00
Topi Pohjolainen
2a549c43a8 meta: Refactor state save/restore for framebuffer texture blits
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2014-05-13 10:04:25 +03:00
Kristian Høgsberg
06842d436e wayland: Move version 2 request to end of interface specification
We're moving towards requiring interface additions to be appended to the
end of the interface block.  No functional change, opcodes are assigned as
before, but version 2 additions are now grouped together, which prevents
a scanner warning.

Cc: "10.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
2014-05-12 15:55:21 -07:00
Timothy Arceri
9c9dd8ca93 glsl: the number of samplers is already calculated so use it
Signed-off-by: Timothy Arceri <t_arceri@yahoo.com.au>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2014-05-13 07:40:08 +10:00
Eric Anholt
afe3d1556f i965: Stop doing remapping of "special" regs.
Now that we aren't using pixel_[xy] in live variables, nothing is looking
at these regs after the visitor stage.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-05-12 09:50:32 -07:00
Eric Anholt
66f5c8df06 i965: Generalize the pixel_x/y workaround for all UW types.
This is the only case where a fs_reg in brw_fs_visitor is used during
optimization/code generation, and it meant that optimizations had to be
careful to not move pixel_x/y's register number without updating it.

Additionally, it turns out we had a couple of other UW values that weren't
getting this treatment (like gl_SampleID), so this more general fix is
probably a good idea (though I wasn't able to replicate problems with
either pixel_[xy]'s values or gl_SampleID, even when telling the register
allocator to reuse registers immediately)

Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-05-12 09:49:27 -07:00
Eric Anholt
11bef60d09 i965: Move has_hiz from the slice to the level.
The value depends only on the level, so no need to store the bool per slice.
Shrinks intel_mipmap_slice from 24 bytes to 16, while slotting into an
existing hole in intel_mipmap_level.

Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
2014-05-12 09:49:18 -07:00
Topi Pohjolainen
4dc9c314c8 meta: Refactor configuration of renderbuffer sampling
Cc: "10.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-05-12 17:48:45 +03:00
Topi Pohjolainen
a2952315ac meta: Refactor binding of renderbuffer as texture image
Cc: "10.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-05-12 17:48:45 +03:00
Topi Pohjolainen
ac4db0aa55 meta: Merge compiling and linking of blit program
Cc: "10.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-05-12 17:48:45 +03:00
Topi Pohjolainen
3a43cd0c3e i965/blorp: Expose coordinate scissoring and mirroring
Cc: "10.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-05-12 17:48:45 +03:00
Topi Pohjolainen
4a92ad5531 i965/gen8: Use helper variables for surface parameters
Cc: "10.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-05-12 17:48:45 +03:00
Ilia Mirkin
8baed87212 nv50,nvc0: fix blit 3d path for 1d array textures
Need to adjust coordinates since the shader receives the array index as
depth in z, but the TEX instruction expects it to be the second
coordinate for a 1D array texture. This fixes fbo-generatemipmap-array.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Ben Skeggs <bskeggs@redhat.com>
Cc: "10.2" <mesa-stable@lists.freedesktop.org>
2014-05-11 19:26:31 -04:00
Ilia Mirkin
4467c0c9fb nv50,nvc0: leave queries on during blit, turn them on for 2d engine
Fixes the new logic of the conditional rendering piglit test.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Ben Skeggs <bskeggs@redhat.com>
Cc: "10.2" <mesa-stable@lists.freedesktop.org>
2014-05-11 19:26:31 -04:00
Ilia Mirkin
64a7ddf40d mesa/st: leave current query enabled during glBlitFramebuffer
Also make sure that pipe_blit_info gets zero'd out so that query isn't
accidentally left enabled.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "10.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2014-05-11 19:26:31 -04:00
Ilia Mirkin
752ce0affb gallium: add bit to pipe_blit_info to leave current query enabled
Previously the implication was that queries should be disabled during
blits. However glBlitFramebuffer() is supposed to obey the current
query, and this new bit will indicate that to the driver.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "10.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2014-05-11 19:26:31 -04:00
Ilia Mirkin
863573b9cb nv50: fix setting of texture ms info to be per-stage
Different textures may be bound to each slot for each stage. So we need
to be able to upload ms parameters for each one without stages
overwriting each other.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Ben Skeggs <bskeggs@redhat.com>
Cc: "10.1 10.2" <mesa-stable@lists.freedesktop.org>
2014-05-11 19:26:31 -04:00
Ilia Mirkin
68f47cad0d nv50/ir: make sure to reverse cond codes on all the OP_SET variants
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Ben Skeggs <bskeggs@redhat.com>
Cc: "10.2 10.1" <mesa-stable@lists.freedesktop.org>
2014-05-11 19:26:31 -04:00
Rob Clark
83b4ec03e7 freedreno/a2xx: fix compiler warning
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-05-11 08:58:20 -04:00
Marek Olšák
d9e102b220 radeonsi: prepare depth export registers at compile time
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2014-05-10 13:58:46 +02:00
Marek Olšák
9baaa5dd4f radeonsi: simplify depth/stencil export code
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2014-05-10 13:58:46 +02:00
Marek Olšák
bd2df40a84 radeon/llvm: add support for non-scalar system values
The sample position is one of them.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2014-05-10 13:58:46 +02:00
Marek Olšák
250aa93e23 radeonsi: add and use a helper function for loading constants
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2014-05-10 13:58:46 +02:00
Marek Olšák
86035cd88d radeonsi: only count CS space for state atoms if we're going to draw
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2014-05-10 13:58:46 +02:00
Marek Olšák
023d367ae6 radeonsi: remove unused variable exports_ps in si_pipe_shader_ps
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2014-05-10 13:58:46 +02:00
Marek Olšák
315f3c171d radeonsi: use DRAW_PREAMBLE on CIK
It's the same as setting the 3 regs separately, but shorter, and it also
seems to be required on GFX7.2 and later. This doesn't fix Hawaii.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2014-05-10 13:58:46 +02:00
Marek Olšák
58c659703b r600g: simplify framebuffer state size computation
Take the upper bound. The number doesn't have to absolutely correct, only safe.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2014-05-10 13:58:46 +02:00
Kenneth Graunke
155f98d49f Revert "i965: Fix depth (array slices) computation for 1D_ARRAY render targets."
This reverts commit e6967270c7.

Chris Forbes pointed out that this is broken for texture views which
restrict the number of slices.  He committed a better fix which makes
this unnecessary.

Cc: "10.2" <mesa-stable@lists.freedesktop.org>
2014-05-09 20:08:38 -07:00
Emil Velikov
a3e78bab7f egl_dri2: cleanup memory leak in dri2_create_context()
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
2014-05-10 02:09:02 +01:00
Emil Velikov
42770ff94e ilo: destroy the mutex, if winsys creation fails
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
2014-05-10 02:09:02 +01:00
Emil Velikov
326b8e253e glx/tests: Partially revert commit 51e3569573
C++ does not support designated initializers, thus compilation
is not guaranteed to succeed. Surprisingly gcc 4.6.3 fails to
build the code, while version 4.9.0 compiles it without a hitch.

Cc: "10.2" <mesa-stable@lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78403
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Tested-by: Vinson Lee <vlee@freedesktop.org>
2014-05-10 02:08:36 +01:00
Chia-I Wu
510465016b mesa: propagate FragDepthLayout to gl_program
The information was lost during linking, causing the layout to be treated as
FRAG_DEPTH_LAYOUT_NONE.

Signed-off-by: Chia-I Wu <olv@lunarg.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-05-09 17:21:53 -07:00
Chris Forbes
417f5ea00d glsl: Rename linker's is_varying_var
Both the ast->IR and linker have functions with this name, but different
behavior.

Rename the linker's version to var_counts_against_varying_limit to be
closer to what it is actually used for.

Suggested by Ian a while back.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
2014-05-10 09:29:13 +12:00
Kenneth Graunke
9584959123 i965: Fix GPU hangs on Broadwell in shaders with some control flow.
According to the documentation, we need to set the source 0 register
type to IMM for flow control instructions that have both JIP and UIP.

Fixes GPU hangs in approximately 10 Piglit tests, 5 es3conform tests,
Unigine Crypt, a WebGL raytracer demo, and several Steam titles.

Cc: "10.2" <mesa-stable@lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=75478
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=75878
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=76939
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Tested-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Tested-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-05-09 14:18:13 -07:00
Tom Stellard
93c2ebbd83 radeonsi: Enable geometry shaders with LLVM 3.4.1
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

CC: "10.1 10.2" <mesa-stable@lists.freedesktop.org>
2014-05-09 12:16:05 -04:00
Thomas Hellstrom
9306b7c171 st/xa: Fix performance regression introduced by commit "Cache render target surface"
The mentioned commit has the nasty side-effect of turning off accelerated
copies.

Cc: "10.1 10.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Jakob Bornecrantz <jakob@vmware.com>
Reviewed-by: Rob Clark <robdclark@gmail.com>
2014-05-09 08:40:12 +02:00
Tom Stellard
c5f0c98c49 clover: Destory pipe_screen when device does not support compute v2
v2:
  - Make sure screen was successfully created before destroying it.

Cc: "10.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
2014-05-09 04:33:03 -04:00
Tom Stellard
c650033b86 pipe-loader: Don't destroy the winsys in the sw loader
The screen takes ownership of the winsys, and is responsible for
destroying it.  Users of pipe-loader should make sure they destory
and  screens they've created to avoid memory leaks.

This fixes a crash in clover introduced by
ce6c17c083 where the pipe-loader was
destroying the winsys while a screen was still using it.

Cc: "10.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
2014-05-09 04:32:54 -04:00
Chris Forbes
23e9f06569 i965/Gen8: Set up layer constraints properly for depth buffers
Same issues as the previous commit fixed for Gen7:
- Bogus physical->logical layer conversion; depth/stencil surfaces
  are still IMS layout on Gen8.
- mt_layer ignored in layered rendering case, which breaks handling
  of views with MinLayer.
- Render target array extent not set correctly for arrays.

I'm not able to test this one since I can't get a Broadwell yet, but
it's the same set of fixes as for Gen7.

V2: Restore the MAX2() to account for zero depth/layer_count.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-05-09 09:46:20 +12:00