Commit graph

24349 commits

Author SHA1 Message Date
Kenneth Graunke
36478b9f77 iris: Enable the dual_color_blend_by_location driconf option.
This fixes rendering in Unigine Valley 1.0 and Heaven 4.0.
2019-04-22 09:36:36 -07:00
Kenneth Graunke
faa52e328e iris: Add mechanism for iris-specific driconf options
Based on Nicolai's 0f8c5de869.

Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
2019-04-22 09:35:36 -07:00
Icenowy Zheng
3e91c7d544 lima: add Android build
Currently only meson build supported is added for lima driver.

Add Android build support for lima.

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Acked-by: Qiang Yu <yuq825@gmail.com>
2019-04-21 01:05:19 +00:00
Alyssa Rosenzweig
648cda258b panfrost/mdg: Use shared fsign lowering
Fixes failures in shaders.operator.common_functions.sign.*

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-04-19 23:15:57 +00:00
Alyssa Rosenzweig
31d9caa239 panfrost: Fixup vertex offsets to prevent shadow copy
Mali attribute buffers have to be 64-byte aligned. However, Gallium
enforces no such requirement; for unaligned buffers, we were previously
forced to create a shadow copy (slow!). To prevent this, we instead use
the offseted buffer's address with the lower bits masked off, and then
add those masked off bits to the src_offset. Proof of correctness
included, possibly for the opportunity to say "QED" unironically.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-04-19 22:50:20 +00:00
Alyssa Rosenzweig
e008d4f011 panfrost: Track BO lifetime with jobs and reference counts
This (fairly large) patch continues work surrounding the panfrost_job
abstraction to improve job lifetime management. In particular, we add
infrastructure to track which BOs are used by a particular job
(currently limited to the vertex buffer BOs), to reference count these
BOs, and to automatically manage the BOs memory based on the reference
count. This set of changes serves as a code cleanup, as a way of future
proofing for allowing flushing BOs, and immediately as a bugfix to
workaround the missing reference counting for vertex buffer BOs.
Meanwhile, there are a few cleanups to vertex buffer handling code
itself, so in the short-term, this allows us to remove the costly VBO
staging workaround, since this patch addresses the underlying causes.

v2: Use pipe_reference for BO reference counting, rather than managing
it ourselves. Don't duplicate hash-table key removal. Fix vertex buffer
counting.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-04-19 22:50:20 +00:00
Erico Nunes
2288b59ddc lima: enable nir fsign lowering in ppir
The mali utgard pp doesn't support a sign instruction.
Use the nir lowering function for fsign to implement fsign in ppir.

Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-04-19 15:42:23 +00:00
Erico Nunes
56230f0428 lima/ppir: support ppir_op_ceil
Add a few missing ppir_op_ceil enum handling entries to implement
nir_op_fceil in lima ppir.

Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
2019-04-19 10:22:03 +00:00
Kenneth Graunke
a913fbf124 iris: Be less aggressive at postdraw work skipping
We empty the cache sets when flushing the batch, at which point we need
to add any framebuffer related BOs even though the bindings haven't
changed.  So, we now do the cache set tracking unconditionally.

For now, we continue skipping resolve work based on the same conditions
in the predraw functions - the thinking is if we didn't trigger
resolves, there's nothing to update here.  Time will tell if this works.

Partly reverts commit 365886ebe1, and
fixes Unigine Valley rendering on Gen9+.  Drops drawoverhead scores
by about 10-12%.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110353
2019-04-18 18:51:58 -07:00
Gurchetan Singh
599d55371c virgl: wait after a flush
We really need to wait under certain circumstances, or we can end
up writing to memory the same time the host is reading.

Partial revert of d6dc68 ("virgl: use uint16_t mask instead of separate booleans").

Test cases:
   - dEQP-GLES31.functional.texture.texture_buffer.render_modify.as_vertex_array.bufferdata
     on vtest protocol version 2
   - Flickering during Alien Isolation
Fixes: d6dc68 ("virgl: use uint16_t mask instead of separate booleans")

Signed-off-by: Gurchetan Singh <gurchetansingh@chromium.org>
Reviewed-By: Gert Wollny <gert.wollny@collabora.com>
Reviewed-By: Piotr Rak <p.rak@samsung.com>
2019-04-18 15:38:04 -07:00
Marek Olšák
7bc33a5cd5 radeonsi/gfx9: use the correct condition for the DPBB + QUANT_MODE workaround
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2019-04-18 15:58:45 -04:00
Kristian H. Kristensen
a90aa14f5a freedreno: Fix format string warning
Modifiers are uin64_t.

Signed-off-by: Kristian H. Kristensen <hoegsberg@google.com>
2019-04-18 11:46:13 -07:00
Kristian H. Kristensen
9c82a55efc freedreno/a6xx: Add helper for incrementing regid
Increments the regid by specified amount unless regid is is
r63.x (invalid).

Signed-off-by: Kristian H. Kristensen <hoegsberg@google.com>
2019-04-18 11:46:13 -07:00
Kristian H. Kristensen
6aa211b316 freedreno: Use enum values from matching enum
We get a couple of warnings from using mismatched enum values. This
fixes that.

Signed-off-by: Kristian H. Kristensen <hoegsberg@google.com>
2019-04-18 11:46:13 -07:00
Kristian H. Kristensen
c34b285b38 freedreno/a2xx: Fix redundant if statement
We test the condition, declare a few variables, then test the exact
same condition again. Let's not do that.

Signed-off-by: Kristian H. Kristensen <hoegsberg@chromium.org>
2019-04-18 11:46:13 -07:00
Lionel Landwerlin
d1be67db39 iris: implement WaEnableStateCacheRedirectToCS
This 3d performance workaround was initially put in the kernel but the
media driver requires different settings so the register has been
whitelisted in i915 [1] and userspace drivers are left initializing it as
they wish.

[1] : https://patchwork.freedesktop.org/series/59494/

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
2019-04-18 17:43:08 +01:00
Erik Faye-Lund
ce1761edab virgl: document potentially failing blit
This blit can fail, but this is not new; in the old version we
didn't even try to blit in this case. So let's just document the
limitation for now, and leave this for another day.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
2019-04-17 07:27:08 +00:00
Erik Faye-Lund
3fdacf1c39 virgl: do color-conversion during when mapping transfer
When running on OpenGL ES, we can't just map any format for reading,
because of limitations on glReadPixels. So let's fall back to the
blit code-path, and translate the pixels to the correct format in the
end.

This fixes the remaining failures of KHR-GL32.packed_pixels.* apart
from the sRGB tests.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
2019-04-17 07:27:08 +00:00
Erik Faye-Lund
9e9d9b352e virgl: only blit if resource is read
Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
2019-04-17 07:27:08 +00:00
Erik Faye-Lund
fba03322a2 virgl: get readback-formats from host
Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
2019-04-17 07:27:08 +00:00
Erik Faye-Lund
f31b65f1c1 virgl: make sure bind is set for non-buffers
Otherwise, virglrenderer will reject the resource.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
2019-04-17 07:27:08 +00:00
Erik Faye-Lund
afbd68378a virgl: support write-back with staged transfers
We currently don't support writing to resources that uses a temporary
staging-resource to resolve the pixels. If a write-bit was set, we
forgot to perform a blit back to the old resource, followed by trying to
update the wrong resource, which lacks backing-storage. The end-result
would be that nothing useful happened.

This approach also fixes a few smaller bugs, like using the wrong box
(without x y and z zeroed out), which means a partial update of a
multisampled texture could result in the wrong part of the texture being
updated.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
2019-04-17 07:27:08 +00:00
Erik Faye-Lund
0bc8683ffa virgl: use pipe_box for blit dst-rect
Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
2019-04-17 07:27:08 +00:00
Erik Faye-Lund
121e366632 virgl: rewrite core of virgl_texture_transfer_map
Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
2019-04-17 07:27:08 +00:00
Erik Faye-Lund
1f27bd3f2b virgl: return error if allocating resolve_tmp fails
Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
2019-04-17 07:27:08 +00:00
Erik Faye-Lund
fc8b1ca33a virgl: wait for the right resource
In case we're resolving, we need to wait for the resolved resource
instead of the original one.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
2019-04-17 07:27:08 +00:00
Erik Faye-Lund
6263304b2d virgl: check for readback on correct resource
Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
2019-04-17 07:27:08 +00:00
Erik Faye-Lund
ac932ff822 virgl: make unmap queuing a bit more straight-forward
It's hard to read the code that decides if we want to queue up an unmap
or destroy the transfer right away. So let's make it a bit simpler, by
setting a bool in case we want to queue it.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
2019-04-17 07:27:08 +00:00
Erik Faye-Lund
b08e73308e virgl: simplify virgl_texture_transfer_unmap logic
There's no reason to keep an extra indentation level here, let's merge
the two if-conditions.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
2019-04-17 07:27:08 +00:00
Erik Faye-Lund
7dd601a399 virgl: track full virgl_resource instead of just virgl_hw_res
Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
2019-04-17 07:27:08 +00:00
Erik Faye-Lund
c62434f106 virgl: tmp_resource -> templ
This isn't the temporary resource itself, it's the template that we'll
create the resource from. So let's name it appropriately.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
2019-04-17 07:27:08 +00:00
Erik Faye-Lund
18a721fd56 virgl: remove pointless transfer-counter
This is only written to, never read. Let's just get rid of it.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
2019-04-17 07:27:07 +00:00
Timothy Arceri
3c5a9ab9f0 radeonsi/nir: fix scanning of bindless images
Fixes: d62d434fe9 ("ac/nir_to_llvm: add image bindless support")
2019-04-17 09:56:56 +10:00
Kenneth Graunke
c4478889b7 iris: Add texture cache flushing hacks for blit and resource_copy_region
This is a port of Jason's 8379bff6c4
from i965 to iris.  We can't find anything relevant in the documentation
and no one we've talked to has been able to help us pin down a solution.

Unfortunately, we have to put the hack in both iris_blit() and
iris_copy_region().  st/mesa's CopyImage() implementation sometimes
chooses to use pipe->blit() instead of pipe->resource_copy_region().
For blits, we only do the hack if the blit source format doesn't match
the underlying resource (i.e. it's reinterpreting the bits).  Hopefully
this should not be too common.
2019-04-16 13:04:22 -07:00
Kenneth Graunke
33314cf410 iris: Change vendor and renderer strings
This patch changes the GL_VENDOR string from "Mesa Project" to "Intel".
This makes GLX_MESA_query_renderer report "Vendor: Intel (0x8086)"
instead of "Vendor: Mesa Project (0x8086)" which is arguably wrong.
We now also use a consistent vendor string across Windows and Linux.

It also prepends "Mesa" to the GL_RENDERER string, both to credit the
community and have a distinguishing mark between the two drivers.  We
drop "DRI" compared to i965, as it's not really that important.

Improves performance in Portal by 1.8x.  Iris is now 3.86% faster
than i965 at the portal-d1.dem timedemo on my Kabylake laptop.  One
change is that Portal selects the MapBufferRange path based on the
vendor string, and iris's BufferSubData path is still missing the
storage invalidation optimization.
2019-04-16 10:27:20 -07:00
Kenneth Graunke
4c3c417b00 iris: Move iris_debug_recompile calls before uploading.
Order of operations is important, otherwise we'll find the program we
just uploaded as the "old" compile and get confused why nothing is
different between the two keys.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2019-04-16 09:01:20 -07:00
Kenneth Graunke
04f97eefa3 iris: Print the reason for shader recompiles.
I was lazy earlier and hadn't bothered typing / refactoring this.
Now I'm hitting some extra recompiles and would like to see why.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2019-04-16 09:01:18 -07:00
Marek Olšák
d3ce8a7f6b nir: optimize gl_SampleMaskIn to gl_HelperInvocation for radeonsi when possible
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
2019-04-16 10:24:19 -04:00
suresh guttula
05cc018ae6 radeon/vce:Add support for frame_cropping_flag of VAEncSequenceParameterBufferH264
This patch will add support for frame_cropping when the input size is not
matched with aligned size. Currently vaapi driver ignores frame cropping
values provided by client. This change will update SPS nalu with proper
cropping values.

v2: Moving default crop setting to else when enc_frame_cropping_flag is not set.

Signed-off-by: Satyajit Sahu <satyajit.sahu@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
2019-04-16 10:15:09 -04:00
Kenneth Graunke
024a57d23c iris: Make shader_perf_log print to stderr if INTEL_DEBUG=perf is set
This matches i965's behavior, and makes sure that shader compiler
messages are visible when setting INTEL_DEBUG=perf.
2019-04-15 23:33:03 -07:00
Chia-I Wu
334103efbf virgl: hide fence internals from the driver
Fence fds are cheaper than resources.  We want to let winsys make the
decision and use fence fds whenever they are supported.  This commit
prepares the work.

For the moment, we create a resource _and_ a fence fd when
supports_fences is true.  This will be fixed such that we create a
resource _or_ a fence fd.  (And because of a version check bug that we
will fix later, supports_fences is actually never true).

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2019-04-15 23:25:47 +00:00
Chia-I Wu
a23c091988 virgl: handle fence_server_sync in winsys
It does not need help from the driver.  This also fixes one issue where
the fence is ignored when the transfer queue is full.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2019-04-15 23:25:47 +00:00
Rhys Perry
6281517f3e vc4: fix build
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Fixes: 5131b7a43f ('gallium: add support for formatted image loads')
2019-04-15 23:27:21 +01:00
Kenneth Graunke
0f3dc832bc iris: Fix FLUSH_EXPLICIT handling with staging buffers.
I neglected to blit the staging buffer back to the real one at
transfer_flush_region (FlushMappedBufferRange) time.
2019-04-15 14:51:01 -07:00
Kenneth Graunke
62b2ce0592 iris: Preserve all PIPE_TRANSFER flags in xfer->usage
We need to preserve PIPE_TRANSFER_FLUSH_EXPLICIT, DISCARD_RANGE, and
so on, but don't want to pass them to iris_bo_map().  So, keep them all,
but mask them off when calling map.

Chris Wilson told me to do this a long time ago and he was right.
2019-04-15 14:51:01 -07:00
Kenneth Graunke
9c52dce6a9 iris: Actually mark blorp_copy_buffer destinations as written. 2019-04-15 14:51:01 -07:00
Dylan Baker
95aefc94a9 Delete autotools
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Acked-by: Matt Turner <mattst88@gmail.com>
2019-04-15 13:44:29 -07:00
Marek Olšák
de0c97c817 radeonsi: enable GL_EXT_shader_image_load_formatted
no changes - the driver doesn't use the format

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-04-15 16:18:07 -04:00
Rhys Perry
5131b7a43f gallium: add support for formatted image loads
v3: rebase
v3: make use of u_pipe_screen_get_param_defaults

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2019-04-15 16:18:07 -04:00
Kenneth Graunke
8bf9b7b5b6 intel: Emit 3DSTATE_VF_STATISTICS dynamically
Pipeline statistics queries should not count BLORP's rectangles.

    (23) How do operations like Clear, TexSubImage, etc. affect the
         results of the newly introduced queries?

      DISCUSSION: Implementations might require "helper" rendering
      commands be issued to implement certain operations like Clear,
      TexSubImage, etc.

      RESOLVED: They don't. Only application submitted rendering
      commands should have an effect on the results of the queries.

Piglit's arb_pipeline_statistics_query-vert_adj exposes this bug when
the driver is hacked to always perform glBufferData via a GPU staging
copy (for debugging purposes).

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-04-14 19:58:04 -07:00