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iris: Be less aggressive at postdraw work skipping

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We empty the cache sets when flushing the batch, at which point we need
to add any framebuffer related BOs even though the bindings haven't
changed.  So, we now do the cache set tracking unconditionally.

For now, we continue skipping resolve work based on the same conditions
in the predraw functions - the thinking is if we didn't trigger
resolves, there's nothing to update here.  Time will tell if this works.

Partly reverts commit 365886ebe1, and
fixes Unigine Valley rendering on Gen9+.  Drops drawoverhead scores
by about 10-12%.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110353
This commit is contained in:
Kenneth Graunke 2019-04-18 14:35:26 -07:00
parent cd4ffb376f
commit a913fbf124
1 changed files with 35 additions and 27 deletions
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62
src/gallium/drivers/iris/iris_resolve.c
View file

@ -248,50 +248,58 @@ iris_postdraw_update_resolve_tracking(struct iris_context *ice,
// XXX: front buffer drawing?
if (ice->state.dirty & (IRIS_DIRTY_DEPTH_BUFFER |
IRIS_DIRTY_WM_DEPTH_STENCIL)) {
struct pipe_surface *zs_surf = cso_fb->zsbuf;
if (zs_surf) {
struct iris_resource *z_res, *s_res;
iris_get_depth_stencil_resources(zs_surf->texture, &z_res, &s_res);
unsigned num_layers =
zs_surf->u.tex.last_layer - zs_surf->u.tex.first_layer + 1;
bool may_have_resolved_depth =
ice->state.dirty & (IRIS_DIRTY_DEPTH_BUFFER |
IRIS_DIRTY_WM_DEPTH_STENCIL);
if (z_res) {
struct pipe_surface *zs_surf = cso_fb->zsbuf;
if (zs_surf) {
struct iris_resource *z_res, *s_res;
iris_get_depth_stencil_resources(zs_surf->texture, &z_res, &s_res);
unsigned num_layers =
zs_surf->u.tex.last_layer - zs_surf->u.tex.first_layer + 1;
if (z_res) {
if (may_have_resolved_depth) {
iris_resource_finish_depth(ice, z_res, zs_surf->u.tex.level,
zs_surf->u.tex.first_layer, num_layers,
ice->state.depth_writes_enabled);
if (ice->state.depth_writes_enabled)
iris_depth_cache_add_bo(batch, z_res->bo);
}
if (s_res) {
if (ice->state.depth_writes_enabled)
iris_depth_cache_add_bo(batch, z_res->bo);
}
if (s_res) {
if (may_have_resolved_depth) {
iris_resource_finish_write(ice, s_res, zs_surf->u.tex.level,
zs_surf->u.tex.first_layer, num_layers,
ISL_AUX_USAGE_NONE);
if (ice->state.stencil_writes_enabled)
iris_depth_cache_add_bo(batch, s_res->bo);
}
if (ice->state.stencil_writes_enabled)
iris_depth_cache_add_bo(batch, s_res->bo);
}
}
if (ice->state.dirty & (IRIS_DIRTY_BINDINGS_FS | IRIS_DIRTY_BLEND_STATE)) {
for (unsigned i = 0; i < cso_fb->nr_cbufs; i++) {
struct iris_surface *surf = (void *) cso_fb->cbufs[i];
if (!surf)
continue;
bool may_have_resolved_color =
ice->state.dirty & (IRIS_DIRTY_BINDINGS_FS | IRIS_DIRTY_BLEND_STATE);
struct iris_resource *res = (void *) surf->base.texture;
for (unsigned i = 0; i < cso_fb->nr_cbufs; i++) {
struct iris_surface *surf = (void *) cso_fb->cbufs[i];
if (!surf)
continue;
struct iris_resource *res = (void *) surf->base.texture;
enum isl_aux_usage aux_usage = ice->state.draw_aux_usage[i];
iris_render_cache_add_bo(batch, res->bo, surf->view.format,
aux_usage);
if (may_have_resolved_color) {
union pipe_surface_desc *desc = &surf->base.u;
unsigned num_layers =
desc->tex.last_layer - desc->tex.first_layer + 1;
enum isl_aux_usage aux_usage = ice->state.draw_aux_usage[i];
iris_render_cache_add_bo(batch, res->bo, surf->view.format,
aux_usage);
iris_resource_finish_render(ice, res, desc->tex.level,
desc->tex.first_layer, num_layers,
aux_usage);