Commit graph

162712 commits

Author SHA1 Message Date
Rohan Garg
fa4a0b7f63 anv: Ensure we clear ANV_PIPE_PSS_STALL_SYNC_BIT on flush
Add the PSS stall bit to ANV_PIPE_STALL_BITS so that it get's cleared on
flush.

Fixes: f3c62973 ("anv,iris: PSS Stall Sync around color fast clears")

Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20317>
(cherry picked from commit ad9c0e8cd9)
2022-12-29 19:25:30 +00:00
Friedrich Vock
192b312550 radv/rt: Refactor exiting PLOC
The previous approach was susceptible to sync hazards, causing hangs in Doom Eternal.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7897
Fixes: 271865373 ("radv: Add PLOC shader")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20377>
(cherry picked from commit f0f5d5c5e5)
2022-12-29 19:25:30 +00:00
Friedrich Vock
9b1d9d169b radv/rt: Execute memory barrier before updating the phase end count
We want to be sure that the values were updated before letting other invocations continue.

Fixes: 271865373 ("radv: Add PLOC shader")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20377>
(cherry picked from commit 54ca0665c8)
2022-12-29 19:25:30 +00:00
Friedrich Vock
b65b1a782c radv/rt: PLOC fixes for active_leaf_count
Fixes: 271865373 ("radv: Add PLOC shader")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20377>
(cherry picked from commit 0e0f42723e)
2022-12-29 19:25:30 +00:00
Marek Vasut
20dd926bea etnaviv: Do expose 2D texture support on pre-halti GPUs
Commit d08bd9a8d8 ("etnaviv: don't expose array and 3D texture support on pre-halti GPUs")
started returning 0 from PIPE_CAP_MAX_TEXTURE_2D_SIZE as well due to switch
case fallthrough. Reinstate the behavior of PIPE_CAP_MAX_TEXTURE_2D_SIZE,
while at the same time, retain the new behavior introduced by commit
d08bd9a8d8 , Otherwise not even kmscube displays the spinning cube,
weston does not display desktop and so on.

Triggered on "Vivante GC600 rev 4653" , i.MX8M Mini .

Fixes: d08bd9a8d8 ("etnaviv: don't expose array and 3D texture support on pre-halti GPUs")
Closes: #7898
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Signed-off-by: Marek Vasut <marex@denx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20373>
(cherry picked from commit 18f4dc6b75)
2022-12-29 19:25:30 +00:00
Alyssa Rosenzweig
1fa1009ef2 panfrost: Align WSI strides for tiled AFBC
When calculating legacy WSI strides for tiled AFBC, we need to account for the
greater alignment requirement of tiled AFBC, or importing resources will fail
later.

Since tiled AFBC is only supported on v7 and later, and AFBC of window surfaces
isn't being used on Linux on v7 and later, this probably hasn't been hit in
practice. Probably.

We're about to fix AFBC of window surfaces so we need to fix this side first.

Fixes: 0255f554f3 ("panfrost: Advertise 16x16 tiled AFBC")
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20311>
(cherry picked from commit a3f9aa3b3e)
2022-12-29 19:25:30 +00:00
pal1000
3cfe9bb623 OpenCL/draw module: Support linking with LLVM and clang 15 static libraries
Cc: mesa-stable

Closes: #7243

Closes: #7487

Reviewed-by: Karol Herbst <kherbst@redhat.com>

Reviewed-by: Yonggang Luo <luoyonggang@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19009>
(cherry picked from commit f69b43ae3e)
2022-12-29 19:25:30 +00:00
Rhys Perry
d03c94fa82 radv/gfx11: disable mesh shaders
Even if the perftest is used, these should be disabled on GFX11. We
don't implement it yet

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Cc: 22.3 <mesa-stable>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20358>
(cherry picked from commit 74ceff1816)
2022-12-29 19:25:30 +00:00
Rhys Perry
e6e692e19a aco/gfx11: export mrtz in discard early exit for non-color shaders
If a shader doesn't export any color targets and instead only exports
mrtz, the discard early exit block should match.

Fixes artifacts on Lara in Rise of the Tomb Raider benchmark and hair in
The Witcher 3 (classic).

https://reviews.llvm.org/D128185

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Fixes: bc8da20dda ("aco: export MRT0 instead of NULL on GFX11")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20345>
(cherry picked from commit 192486b7aa)
2022-12-29 19:25:30 +00:00
Iago Toral Quiroga
7a9c1e17fe v3dv: be more careful when restoring dirty state after meta operations
So far we have been only restoring dirty dynamic states used by meta
pipelines however, static state from meta pipelines will also clear
dirty flags, preventing follow-up draw calls in the command buffer
to honor these if they are flagged as dynamic states in their
pipelines. Fix this by always resetting all dirty state flags after
a meta operation so we re-emit all the state we need with the next draw
call.

Fixes:
dEQP-VK.dynamic_state.monolithic.image.clear

cc: mesa-stable

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20356>
(cherry picked from commit df8611e816)
2022-12-29 19:25:30 +00:00
Iago Toral Quiroga
538a66b027 v3dv: pipeline creation feedback may not request all stages
Nothing in the spec seems to require that the number of stages for
which creation feedback is requested must match the number of stages
available in the pipeline. In fact, the spec explicitly mentions
that this number could be 0:

   "If pipelineStageCreationFeedbackCount is not 0,
    pPipelineStageCreationFeedbacks must be a valid pointer to an
    array of pipelineStageCreationFeedbackCount
    VkPipelineCreationFeedback structures"

Fixes an assert crash in:
dEQP-VK.pipeline.monolithic.creation_feedback.graphics_tests.vertex_stage_fragment_stage_no_cache_zero_out_feedback_cout

cc: mesa-stable

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20352>
(cherry picked from commit 3cc863649f)
2022-12-29 19:25:29 +00:00
Pavel Ondračka
edb0e10b5a r300: be more careful with presubtract and non-native swizzles
The problematic scenario is when we have the same source used by both
normal and presubtract argument. We check that case currently and count
the source only once. However if one of the arguments uses a non-native
swizzle, we have to rewrite it later and the source changes. Therefore
we end with too many sources and fail later during pair translation.

Example:
ADD temp[21].xy, temp[20].xy__, temp[17].xy__;
MAD temp[22].xy, temp[17].zw__, temp[11].xy__, temp[21].xy__;

will get converted to

MAD temp[22].xy, temp[17].zw__, temp[11].xy__, (temp[17] + temp[20]).xy__;

however after dataflow swizzles pass we end with

MOV temp[3].x, temp[17].z___;
MOV temp[3].y, temp[17]._w__;
MAD temp[22].xy, temp[3].xy__, temp[11].xy__, (temp[17] + temp[20]).xy__;

Just skip the "don't count the same source twice" optimization when a
non-native swizzle is used to fix 2 dEQP atan2 tests.

Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Reviewed-by: Filip Gawin <filip@gawin.net>
Tested-by: Filip Gawin <filip@gawin.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19764>
(cherry picked from commit 6738a7b5b4)
2022-12-29 19:25:29 +00:00
Iago Toral Quiroga
49d8af74ed v3dv: honor render area in subpass resolve fallback
When falling back to handling subpass resolves via separate
image resolves we were resolving the entire attachment instead
of limiting the resolve to the render area defined for the render
pass.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20331>
(cherry picked from commit ce94d3e48d)
2022-12-29 19:25:29 +00:00
Iago Toral Quiroga
4847a0845c v3dv: handle depth/stencil resolves we can't implement via TLB
If we can't use the TLB to do a subpass resolve we have a fallaback
that emits separate image resolves, but this fallback was only
handling color resolves. This adds depth/stencil as well.

Fixes some of the issues we have with CTS 1.3.4 in:
dEQP-VK.pipeline.monolithic.multisample.misc.*

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20331>
(cherry picked from commit 9ac053e0a2)
2022-12-29 19:25:29 +00:00
Iago Toral Quiroga
c92aaf6d09 v3dv: don't resolve by averaging samples on depth/stencil resolves
For these we always want to use sample_0, averaging is reserved for
color formats. We were already doing this correctly for depth/stencil
resolved in render passes, but not for those happening through
vkCmdResolveImage.

Fixes some of the issues we have with CTS 1.3.4 in:
dEQP-VK.pipeline.monolithic.multisample.misc.*

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20331>
(cherry picked from commit 284285376b)
2022-12-29 19:25:29 +00:00
Iago Toral Quiroga
02b95befed v3dv: always store/restore attachment state during meta operations
attachment state is only relevant during render passes, however,
there is a corner case: if we can't resolve an attachment in a
subpass using the hardware, we emit a manual image resolve in the
driver which can trigger a meta operation via blit. In this case,
we pretend we are not in a render pass (since vulkan disallows
blits/resolves in a render pass) but we really want to keep the
attachment state after the meta operation.

Fixes some of the issues we have with CTS 1.3.4 in:
dEQP-VK.pipeline.monolithic.multisample.misc.*

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20331>
(cherry picked from commit 6117f855ee)
2022-12-29 19:25:29 +00:00
Lionel Landwerlin
9c1899e93f anv: fixup another dirty issue with gpu_memcpy
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20335>
(cherry picked from commit b21cd1ee1b)
2022-12-29 19:25:29 +00:00
Konstantin Seurer
ae0c9ee7e1 radv/rra: Emit leaf node ids for leaf nodes instead of internal nodes
Fixes: e4283d8 ("radv/rra: Handle box16 nodes")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20184>
(cherry picked from commit ab8777b384)
2022-12-29 19:25:29 +00:00
Timur Kristóf
da887a635b aco: Don't accept constants on p_bpermute.
The sequence emitted for this pseudo instruction is not ready
to handle constants or literals at all.

Cc: mesa-stable
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20293>
(cherry picked from commit 614348f28b)
2022-12-29 19:25:29 +00:00
Emma Anholt
02d32bac72 zink: Fix reversed cap declarations for ImageBuffer
Fixes validation fails on
KHR-GLES31.core.texture_buffer.texture_buffer_texture_buffer_range.

Fixes: f55a4407ef ("zink: more accurately set {Sampled,Image}Buffer caps")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20308>
(cherry picked from commit 9dedbf66f6)
2022-12-29 19:25:29 +00:00
Eric Engestrom
c4843e4ab4 .pick_status.json: Update to def474e916 2022-12-29 19:25:25 +00:00
Eric Engestrom
6db008a8bb docs/relnotes: add 22.3.1 to index 2022-12-14 22:40:29 +00:00
Eric Engestrom
c20f1fc62e docs/relnotes: add sha256sum for 22.3.1 2022-12-14 22:34:47 +00:00
Eric Engestrom
c36706142b VERSION: bump for 22.3.1 2022-12-14 21:06:11 +00:00
Eric Engestrom
840eef75bd docs: add release notes for 22.3.1 2022-12-14 21:05:30 +00:00
Sathishkumar S
9b02e5c023 gallium/vl: return the buffer plane order for yuv444p format
plane order is expected when trying to render yuv surfaces, update it for yuv444p

Signed-off-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19445>
(cherry picked from commit f1ea0bc18a)
2022-12-14 20:56:55 +00:00
Sathishkumar S
cdbba253c2 frontends/va: fix crash during grayscale rendering
crash is observed as format is assumed to be yuv and buffer plane
order is undefined for monochrome. luma only format is not to be
considered yuv format. It has to be rendered with rgb=rrr.

Signed-off-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Reviewed-by: Thong Thai <thong.thai@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20165>
(cherry picked from commit 6a3179c5a9)
2022-12-14 20:56:54 +00:00
Lionel Landwerlin
a60641d132 anv: disable Wa_1806565034 when robustImageAccess is enabled
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5711
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7859
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20280>
(cherry picked from commit a921486e2a)
2022-12-14 20:56:54 +00:00
Lionel Landwerlin
fcb34f031c intel/fs: make Wa_1806565034 conditional to non robust access
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20280>
(cherry picked from commit 94bb4a13fa)
2022-12-14 20:56:54 +00:00
Lionel Landwerlin
b5820a84a2 isl: make Wa_1806565034 conditional to non robust access
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20280>
(cherry picked from commit 89a550a37b)
2022-12-14 20:56:54 +00:00
Ian Romanick
c1fad08d69 glsl_to_nir: Fix NIR bit-size of ir_triop_bitfield_extract and ir_quadop_bitfield_insert
Previously these would return result->bit_size of 32 even though the
type might have been int16_t or uint16_t.  This prevents many assertion
failures in "glsl: Use nir_type_convert instead of
nir_type_conversion_op" on zink.

Fixes: 5e922fbc16 ("glsl_to_nir: fix bitfield_extract with 16-bit operands")
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15121>
(cherry picked from commit 43da822312)
2022-12-14 20:56:54 +00:00
Eric Engestrom
ae1fa524c4 v3dv: skip some invalid tests
Cc: mesa-stable
Signed-off-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20305>
(cherry picked from commit 408f1c689c)
2022-12-14 20:56:54 +00:00
Sathishkumar S
74d17cba5c radeonsi/vcn: fix regression in yuv422 jpeg decode
- yuv422 decode was blocked in 12acee17fa, enable it back.
- nv12 yuv422 and grayscale decode is supported on all versions.
- JPEG2 and higher versions supports 444p decode.
- add l8_unorm to supported formats, can be used for grayscale.

Fixes: 12acee17fa (frontends/va: reallocate surface for yuv400/yuv444 picture)

v2: indent the switch case correctly (Thong Thai)

Signed-off-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Reviewed-by: Thong Thai <thong.thai@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20165>
(cherry picked from commit 7ad4a5079e)
2022-12-14 20:56:53 +00:00
Sathishkumar S
0565b834b6 radeonsi/vcn: enable yuv422 jpeg decode
add yuv422 to supported decode format on asics that support it.

Signed-off-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19445>
(cherry picked from commit 581220aa54)
2022-12-14 20:56:02 +00:00
Samuel Pitoiset
a8911c50c8 radv: do not remove the PointSize built-in for polygon mode as points
Determine if it can be removed when generating the graphics pipeline
key because of dynamic states.

Fixes new CTS dEQP-VK.rasterization.polygon_as_large_points.* and also
spec@!opengl 1.1@polygon-offset with Zink/RADV.

Cc: 22.3 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20073>
(cherry picked from commit b4f940913d)
2022-12-14 20:47:02 +00:00
Jan Palus
a9b3fee4b0 vdpau: allow building vdpau st with virgl only
Fixes: 6b5aecb195 ("virgl: add support for hardware video acceleration")

Signed-off-by: Jan Palus <jpalus@fastmail.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20108>
(cherry picked from commit 8560ce28c2)
2022-12-14 20:47:02 +00:00
Friedrich Vock
63e1ccd598 radv: Handle NULL miss shaders
Fixes reflections in DOOM Eternal.

Fixes: 85580faa ("radv: Add ray traversal loop.")
Closes: #6210
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20270>
(cherry picked from commit 568fa71ef8)
2022-12-14 20:47:02 +00:00
Peng Huang
3e3def9620 intel: Fix crashes for importing drm buffer
image_aspect_to_binding() converts aspect to index by subrracting
VK_IMAGE_ASPECT_MEMORY_PLANE_0_BIT_EXT, however these enum values
are bitfields, not consecutive numbers, so comparing and subtracting
them won't work.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20269>
(cherry picked from commit 7642f3b99c)
2022-12-14 20:47:02 +00:00
Lionel Landwerlin
0c7a3133ac anv: fixup descriptor copies
I did not properly understood that we cannot access the views written
to the descriptor sets because they might have been destroyed after
the write operation and the copy operation is allowed to copy what is
invalid data. The shader just can't access it.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 03e1e19246 ("anv: Refactor descriptor copy")
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20222>
(cherry picked from commit a0991c7c79)
2022-12-14 20:47:02 +00:00
Iván Briano
dc889d95bc hasvk: pipelineStageCreationFeedbackCount is allowed to be 0
Fixes: 6601e5d6fc ("anv: implement VK_EXT_pipeline_creation_feedback")

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20216>
(cherry picked from commit 68b546ec3d)
2022-12-14 20:47:02 +00:00
Lionel Landwerlin
bf1d05b8e4 intel/nir/rt: fixup primitive id
There is a delta index value in the hit structure, we forgot to add it
to the base value.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 0465714790 ("intel/nir/rt: add more helpers for ray queries")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7565
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19346>
(cherry picked from commit 6106396825)
2022-12-14 20:47:02 +00:00
Samuel Pitoiset
5e0dfcb9c7 radv: fix hashing descriptor set layout
Shouldn't have pointers.

Fixes: 19f8d33876 ("radv: Use vk_descriptor_set_layout")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20250>
(cherry picked from commit 13f39da71a)
2022-12-14 20:47:02 +00:00
Friedrich Vock
57827e6903 nir: Do not consider phis with incompatible dests equal
CSE tries to collapse equal instructions, and collapsing two phis with incompatible dests is illegal.

Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Fixes: 6bdce55c ("nir: Add a basic CSE pass")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19960>
(cherry picked from commit a54c2c8289)
2022-12-14 20:47:01 +00:00
Lionel Landwerlin
68fece9af5 Revert "anv: compile anv_acceleration_structure.c"
This reverts commit 74d0be27ae.

Also remove anv_acceleration_structure.c, it was meant to be removed
earlier. There was probably a rebase issue somewhere.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20248>
(cherry picked from commit d608706875)
2022-12-14 20:47:01 +00:00
Rhys Perry
2c73855937 aco/ra: don't swap p_create_vector operand with definition blocker for scc
SCC is 1-bit, and we can't copy a 32-bit value into it.

Fixes dEQP-VK.spirv_assembly.type.scalar.i32.iequal_tesse with
ACO_DEBUG=noopt.

No fossil-db changes.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Fixes: 9476986e6f ("aco/ra: special-case get_reg_for_create_vector_copy()")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20240>
(cherry picked from commit a05dd58309)
2022-12-14 20:47:01 +00:00
Ruijing Dong
6922882d8f frontends/va: fix gst videotestsrc h264 enc fail issue.
problem:
when doing "gst-launch-1.0 -v videotestsrc num-buffer=10 !
   vaapih264enc ! fakeink"

The command will fail due to gst will fetch the first
available supported format in the list, it becomes P010_LE
due to the commit in

[0b02db3007]
frontends/va: fixed av1 decoding 10bit ffmpeg output YUV issue

fix:
move the P010_LE code block to the end of the function, the sequence
of the supported formats restored to its original.

cc: mesa-stable

Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20242>
(cherry picked from commit a73e86e0a5)
2022-12-14 20:47:01 +00:00
Tapani Pälli
e17740493f anv: emit sample mask state independent of fragment stage
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7861
Fixes: 9f6af43743 ("anv: dynamic multisample sample mask")
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20221>
(cherry picked from commit 68ef0d8448)
2022-12-14 20:47:01 +00:00
Boyuan Zhang
bcc73ba6f7 radeonsi: disable av1 decode for navi24
Disable AV1 decode for Navi24 since hardware doesn't support.

fixed: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7855

cc: mesa-stable

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20230>
(cherry picked from commit 5233551e19)
2022-12-14 20:47:01 +00:00
Tapani Pälli
5b6718728b intel/fs: implement Wa_14017989577
The first instruction of any kernel should have non-zero emask. This
restriction needs to be obeyed to avoid GPU hangs.

Patch adds a function to insert dummy mov as first instruction
to make sure this requirement is fulfilled.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20194>
(cherry picked from commit bc4b7de0d0)
2022-12-14 20:47:01 +00:00
Kenneth Graunke
d936394cf4 intel/compiler: Set NoMask on cr0 access for float controls mode
This is trying to clear a bit in the control register.  However, it's
executing with whatever channel mask happens to be active.  Typically
this is the one at the start of the program, so at least some channels
will be active.  Typically the first channel will be active due to
packed dispatch, but that's not always guaranteed.  Without NoMask,
the float controls writes may randomly not happen.

Recent GPUs also seem to have a hang issue when the first instruction in
the shader doesn't have any active channels.  Having an instruction with
NoMask at the start of the program works around the issue.  See HSD bug
14017989577.  In our case, the float controls preamble was breaking that
restriction every time, causing us to run into this problem frequently.

Thanks to Tapani Pälli for finding this hang issue, and Francisco
Jerez and Lionel Landwerlin for helping pinpoint this issue during
review of a workaround patch in !20194.

Fixes GPU hangs in Elder Scrolls Online, Witcher 3, and likely more.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7639
Fixes: 9da56ffc52 ("i965/fs: add emit_shader_float_controls_execution_mode() and aux functions")
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20214>
(cherry picked from commit bafbe7c23a)
2022-12-14 20:47:01 +00:00