Commit graph

12836 commits

Author SHA1 Message Date
Caio Oliveira
b9787fcc80 intel/brw: Move emit_scan/emit_scan_step near its usage
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30496>
2024-10-11 06:40:29 +00:00
Caio Oliveira
0ba1159b0a intel/brw: Add SHADER_OPCODE_*_SCAN
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30496>
2024-10-11 06:40:29 +00:00
Caio Oliveira
9537b62759 intel/brw: Add SHADER_OPCODE_REDUCE
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30496>
2024-10-11 06:40:29 +00:00
Caio Oliveira
4361a08254 intel/brw: Reduce scope of has_source_and_destination_hazard
This predicate at the moment is only relevant during register
allocation, so move it there and the code can ignore virtual
instructions that were already lowered previously.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30496>
2024-10-11 06:40:29 +00:00
Caio Oliveira
bf9456753d intel/brw: Validate some instructions exists only up until some phases
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30496>
2024-10-11 06:40:29 +00:00
Caio Oliveira
affa7567c2 intel/brw: Add phases to backend
The general idea is to be able to validate that certain instructions
were lowered and certain restrictions were already handled.  Passes can
now assert their expectations, i.e. if a pass is mean to run after
certain lowerings or not.

The actual phases are a initial stab and as we re-organized the passes,
we may remove/add phases.

This commit just add some phase steps, later commits will make use of
them.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30496>
2024-10-11 06:40:29 +00:00
Caio Oliveira
21f78454bf intel/brw: Fix Gfx9 3-src validation to handle FIXED_GRF
Note this validation path is not being used at the moment, but will in a
later commit.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30496>
2024-10-11 06:40:29 +00:00
Caio Oliveira
3e8796b677 intel/brw: Print Non-SSA regs after NIR in debug output
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30496>
2024-10-11 06:40:29 +00:00
Caio Oliveira
2811cb2923 intel: Add statistic for Non SSA registers after NIR to BRW
This is going to be useful while we convert the NIR to BRW to produce
SSA definitions.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30496>
2024-10-11 06:40:29 +00:00
Caio Oliveira
6db7d1af16 intel/compiler: Rename shader_stats structs
Add the `brw_` and `elk_` prefixes to the structs to avoid compilation
failure building with LTO ("violates the C++ One Definition Rule") when
the structs diverge.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30496>
2024-10-11 06:40:29 +00:00
Caio Oliveira
13d99979d2 intel/brw: Remove the remaining DO_SRC macro from EU validation
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31296>
2024-10-11 04:13:48 +00:00
Caio Oliveira
f1036da345 intel/brw: Add vstride/width/hstride to brw_hw_decoded_inst
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31296>
2024-10-11 04:13:48 +00:00
Caio Oliveira
2251748aad intel/brw: Add dst/srcs register numbers to brw_hw_decoded_inst
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31296>
2024-10-11 04:13:48 +00:00
Caio Oliveira
808b8b65b6 intel/brw: Add abs/negate to brw_hw_decoded_inst
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31296>
2024-10-11 04:13:48 +00:00
Caio Oliveira
f6dbb72219 intel/brw: Add dst/src0 address_mode to brw_hw_decoded_inst
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31296>
2024-10-11 04:13:48 +00:00
Caio Oliveira
e4440df2d8 intel/brw: Add pred/cmod/sat to brw_hw_decoded_inst
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31296>
2024-10-11 04:13:48 +00:00
Caio Oliveira
be70d1f9b1 intel/brw: Add dst/srcs type to brw_hw_decoded_inst
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31296>
2024-10-11 04:13:48 +00:00
Caio Oliveira
e0ba4ca166 intel/brw: Add dst/srcs reg file to brw_hw_decoded_inst
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31296>
2024-10-11 04:13:48 +00:00
Caio Oliveira
3db1c3fc0e intel/brw: Add access_mode to brw_hw_decoded_inst
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31296>
2024-10-11 04:13:48 +00:00
Caio Oliveira
3dc1f64e51 intel/brw: Add exec_size to brw_hw_decoded_inst
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31296>
2024-10-11 04:13:48 +00:00
Caio Oliveira
853fe03470 intel/brw: Add has_dst to brw_hw_decoded_inst
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31296>
2024-10-11 04:13:48 +00:00
Caio Oliveira
c394eb3111 intel/brw: Add num_sources to brw_hw_decoded_inst
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31296>
2024-10-11 04:13:48 +00:00
Caio Oliveira
9cdb90e787 intel/brw: Add opcode to brw_hw_decoded_inst
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31296>
2024-10-11 04:13:48 +00:00
Caio Oliveira
76e177d87d intel/brw: Create a struct to hold a decoded brw_inst in eu_validation
For now it contains only the "raw" brw_inst.  Later patches will add
useful fields to it.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31296>
2024-10-11 04:13:48 +00:00
Caio Oliveira
382bd4ce36 intel/brw: Add ERROR helper variant that returns to EU validation
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31296>
2024-10-11 04:13:48 +00:00
Tapani Pälli
e4fcbe8d6f anv: set StackIDControlOverride_RTGlobals for 2 workarounds
GFX_VER block matches both workarounds and while these workarounds are
almost about the same cause, other one applies only for LNL and other
one for BMG, need to check for both.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31571>
2024-10-10 10:20:56 +00:00
Tapani Pälli
b8fc0288af intel/dev: update mesa_defs.json from workaround database
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31571>
2024-10-10 10:20:56 +00:00
Guilherme Gallo
59d909eb56 ci/lava: Make perf jobs use pyutils artifact
Following the merge of Merge Request #31151, we encountered an issue
where the performance jobs were failing silently. Although these
failures did not cause the pipeline to fail, they resulted in warnings
for all merge requests that ran the .*-traces-performance jobs, putting
critical performance data for the [Mesa Performance Driver
dashboard](https://ci-stats-grafana.freedesktop.org/goto/G3xkvykHg?orgId=1)
at risk.

To resolve this issue, this commit updates the LAVA performance jobs to
utilize the Pyutils artifact package, which is now the only required
artifact for the jobs that run the LAVA job submitter.

Fixes: dd5d737e6c ("ci/lava: Use new pyutils container")

Signed-off-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31553>
2024-10-10 01:33:16 +00:00
Lionel Landwerlin
624d83bfd1 isl: add support of aux disable bit on hiz
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31579>
2024-10-09 23:38:19 +00:00
Lionel Landwerlin
1a72fc013c isl: Tile W memcpy support
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31579>
2024-10-09 23:38:19 +00:00
Lionel Landwerlin
c0e98d2c89 isl/tests: rename span variable to xt_sub_range_alignment
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31579>
2024-10-09 23:38:19 +00:00
Lionel Landwerlin
e44249af5d isl/tests: add more coordinates for full tiles testing
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31579>
2024-10-09 23:38:19 +00:00
Lionel Landwerlin
52263413f4 isl: remove duplicated copy for tileX/TileY
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31579>
2024-10-09 23:38:19 +00:00
Tapani Pälli
78b614b333 anv: add depth, DC and L3 fabric flush for aux map invalidation
These should be included according to table in Bspec 43904.

Patch removes PIPE_CONTROL_STATE_CACHE_INVALIDATE based on HSDES.

Cc: mesa-stable
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29764>
2024-10-08 08:45:40 +00:00
Tapani Pälli
e3814dee1a anv: add plumbing/support for L3 fabric flush
Cc: mesa-stable
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29764>
2024-10-08 08:45:40 +00:00
Tapani Pälli
03f762f90c intel/ds: add L3 fabric flush support
Cc: mesa-stable
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29764>
2024-10-08 08:45:40 +00:00
Tapani Pälli
8cb08830e6 intel/genxml: introduce L3 Fabric Flush for gfx12
Cc: mesa-stable
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29764>
2024-10-08 08:45:40 +00:00
Carlos Santa
39e3015c36 intel/hang_replay: remove EXEC_OBJECT_WRITE
This flag causes the following failure:

total_vma: 0x0000000071c9d000
fail to set context hw img: Invalid argument

Fixes: bab52763f4 ("intel/hang_replay: fix batch address")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11959
Signed-off-by: Carlos Santa <carlos.santa@intel.corp-partner.google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31494>
2024-10-04 21:37:41 +00:00
Carlos Santa
700141da43 intel/hang_replay: fix the typo in the ioctl call
What we really want to pass is DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM
vs DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM

Fixes: a9f1151de2 ("intel/hang_replay: use hw image param")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11959
Signed-off-by: Carlos Santa <carlos.santa@intel.corp-partner.google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31494>
2024-10-04 21:37:41 +00:00
Mike Blumenkrantz
5ba00df1f9 anv: add VK_FORMAT_G10X6_B10X6R10X6_2PLANE_420_UNORM_3PACK16 to modifier exceptions
this is implemented

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31516>
2024-10-04 13:22:08 +00:00
Danylo Piliaiev
e5d3eba096 u_trace: Fix trace_payload_as_extra_func desync between drivers
Buffer with indirect args wasn't passed to the function which
adds extra event args. Since function definition depends on the
common code, the definition is moved to a single place.

Fixes: 0a17035b5c
("u_trace: add support for indirect data")

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31090>
2024-10-03 20:25:48 +00:00
Nanley Chery
26692deefc anv: Delete stale comment for BLORP clear color addr
It looks like this comment attempted to describe all the reasons we need
to pass the clear color address to BLORP. This comment actually isn't
exhaustive and some bits are out of date (e.g., BLORP no longer updates
the clear color address for us). Let's just delete it.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31136>
2024-10-03 19:41:31 +00:00
Nanley Chery
10bcfb63d5 anv: Prevent clear color modifier corruption with views
If a dmabuf is shared with a clear color, the raw clear color channels
generally won't be interpreted correctly during format reinterpretation.
So, prevent Vulkan apps from trying to use such dmabufs as mutable
format render targets. Also, prevent such apps from using such dmabufs
as blorp_copy() destinations if doing so would require format
reinterpretation.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31136>
2024-10-03 19:41:31 +00:00
Nanley Chery
edfb33efdd intel/blorp: Use original surface format for some copies
In iris, this should avoid some partial resolves when copying between
images. In anv, this will reduce restrictions on dmabufs which have
clear color support in the next patch.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31136>
2024-10-03 19:41:31 +00:00
Nanley Chery
73637dbce4 intel/blorp: Choose some copy formats independently
blorp_copy_get_formats() tries to make the source and destination view
formats match as much as possible. This avoids some casting in the copy
shader, but it makes determining the format that will be used for a
surface impossible without having the ISL surface for both that surface
and a source or destination.

We'd like to enable the Vulkan driver to know as early as possible what
format an image may be reinterpreted as for correctness. So, determine
the copy formats more independently and expose a helper which does so
for drivers.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31136>
2024-10-03 19:41:31 +00:00
Nanley Chery
6721064939 anv: Use image formats when copying to/from buffers
blorp_copy() will sometimes use a complex shader if the source and
destination surface formats differ. For example, it will do this when
both formats support CCS_E, but have differing numbers of
bits-per-channel.

To reduce the chance of using this complex shader during transfers
between images and buffers, ensure the same format is used. We can't
completely prevent the complex shader because a copy may happen between
surface formats that have a different number of bits-per-pixel.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31136>
2024-10-03 19:41:31 +00:00
Tapani Pälli
ac00d97e31 anv: use mi_builder in CmdBeginTransformFeedbackEXT
Patch converts MI_LOAD_REGISTER_MEM, MI_LOAD_REGISTER_IMM to use
mi_builder in CmdBeginTransformFeedbackEXT.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31502>
2024-10-03 16:20:40 +00:00
Lionel Landwerlin
1f2ad64b63 anv: optimize WA 16011107343/22018402687
No need to emit the instruction twice.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Backport-to: 24.2
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31481>
2024-10-02 17:27:55 +00:00
Lionel Landwerlin
4cdb5de163 anv: consolidate pre/post draw workaround in helpers
This avoids sprinkling those all over the code base. Debug breakpoints
are put in there too.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Backport-to: 24.2
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31481>
2024-10-02 17:27:55 +00:00
Lionel Landwerlin
18e2c25dad anv: limit 22018402687 to impacted platforms
ARL is impacted, but LNL is not.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Backport-to: 24.2
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31481>
2024-10-02 17:27:55 +00:00