intel: Add statistic for Non SSA registers after NIR to BRW

This is going to be useful while we convert the NIR to BRW to produce
SSA definitions.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30496>

src/intel/compiler/brw_compiler.h

@@ -1311,6 +1311,7 @@ struct brw_compile_stats {
    uint32_t spills;
    uint32_t fills;
    uint32_t max_live_registers;
+   uint32_t non_ssa_registers_after_nir;
 };
 
 /** @} */

src/intel/compiler/brw_def_analysis.cpp

@@ -193,8 +193,8 @@ def_analysis::validate(const fs_visitor *v) const
    return true;
 }
 
-void
-def_analysis::print_stats(const fs_visitor *v) const
+unsigned
+def_analysis::ssa_count() const
 {
    unsigned defs = 0;
 
@@ -203,6 +203,14 @@ def_analysis::print_stats(const fs_visitor *v) const
          ++defs;
    }
 
+   return defs;
+}
+
+void
+def_analysis::print_stats(const fs_visitor *v) const
+{
+   const unsigned defs = ssa_count();
+
    fprintf(stderr, "DEFS: %u registers, %u SSA, %u non-SSA => %.1f SSA\n",
            def_count, defs, def_count - defs,
            100.0f * float(defs) / float(def_count));

src/intel/compiler/brw_fs.h

@@ -97,6 +97,7 @@ namespace brw {
       }
 
       unsigned count() const { return def_count; }
+      unsigned ssa_count() const;
 
       void print_stats(const fs_visitor *) const;
 
@@ -148,6 +149,7 @@ struct brw_shader_stats {
    unsigned spill_count;
    unsigned fill_count;
    unsigned max_register_pressure;
+   unsigned non_ssa_registers_after_nir;
 };
 
 /** Register numbers for thread payload fields. */

src/intel/compiler/brw_fs_generator.cpp

@@ -1487,6 +1487,7 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width,
       stats->spills = shader_stats.spill_count;
       stats->fills = shader_stats.fill_count;
       stats->max_live_registers = shader_stats.max_register_pressure;
+      stats->non_ssa_registers_after_nir = shader_stats.non_ssa_registers_after_nir;
    }
 
    return start_offset;

src/intel/compiler/brw_fs_opt.cpp

@@ -19,6 +19,13 @@ brw_fs_optimize(fs_visitor &s)
    /* Start by validating the shader we currently have. */
    brw_fs_validate(s);
 
+   /* Track how much non-SSA at this point. */
+   {
+      const brw::def_analysis &defs = s.def_analysis.require();
+      s.shader_stats.non_ssa_registers_after_nir =
+         defs.count() - defs.ssa_count();
+   }
+
    bool progress = false;
    int iteration = 0;
    int pass_num = 0;

src/intel/vulkan/anv_pipeline.c

@@ -4490,6 +4490,13 @@ VkResult anv_GetPipelineExecutableStatisticsKHR(
       stat->value.u64 = hash;
    }
 
+   vk_outarray_append_typed(VkPipelineExecutableStatisticKHR, &out, stat) {
+      WRITE_STR(stat->name, "Non SSA regs after NIR");
+      WRITE_STR(stat->description, "Non SSA regs after NIR translation to BRW.");
+      stat->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
+      stat->value.u64 = exe->stats.non_ssa_registers_after_nir;
+   }
+
    return vk_outarray_status(&out);
 }