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https://gitlab.freedesktop.org/mesa/mesa.git
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intel/brw: Add exec_size to brw_hw_decoded_inst
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31296>
This commit is contained in:
Caio Oliveira
Marge Bot
parent
853fe03470
commit
3dc1f64e51
1 changed files with 53 additions and 55 deletions
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@ -47,6 +47,8 @@ typedef struct brw_hw_decoded_inst {
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enum opcode opcode;
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unsigned exec_size;
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bool has_dst;
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unsigned num_sources;
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} brw_hw_decoded_inst;
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@ -232,30 +234,13 @@ invalid_values(const struct brw_isa_info *isa, const brw_hw_decoded_inst *inst)
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struct string error_msg = { .str = NULL, .len = 0 };
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switch ((enum brw_execution_size) brw_inst_exec_size(devinfo, inst->raw)) {
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case BRW_EXECUTE_1:
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case BRW_EXECUTE_2:
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case BRW_EXECUTE_4:
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case BRW_EXECUTE_8:
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case BRW_EXECUTE_16:
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case BRW_EXECUTE_32:
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break;
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default:
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ERROR("invalid execution size");
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break;
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}
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if (error_msg.str)
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return error_msg;
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if (devinfo->ver >= 12) {
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unsigned group_size = 1 << brw_inst_exec_size(devinfo, inst->raw);
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unsigned qtr_ctrl = brw_inst_qtr_control(devinfo, inst->raw);
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unsigned nib_ctrl =
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devinfo->ver == 12 ? brw_inst_nib_control(devinfo, inst->raw) : 0;
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unsigned chan_off = (qtr_ctrl * 2 + nib_ctrl) << 2;
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ERROR_IF(chan_off % group_size != 0,
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ERROR_IF(chan_off % inst->exec_size != 0,
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"The execution size must be a factor of the chosen offset");
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}
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@ -651,7 +636,6 @@ general_restrictions_based_on_operand_types(const struct brw_isa_info *isa,
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{
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const struct intel_device_info *devinfo = isa->devinfo;
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unsigned exec_size = 1 << brw_inst_exec_size(devinfo, inst->raw);
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struct string error_msg = { .str = NULL, .len = 0 };
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if (inst_is_send(inst))
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@ -751,7 +735,7 @@ general_restrictions_based_on_operand_types(const struct brw_isa_info *isa,
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if (inst->num_sources == 3)
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return error_msg;
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if (exec_size == 1)
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if (inst->exec_size == 1)
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return error_msg;
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if (!inst->has_dst)
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@ -800,7 +784,7 @@ general_restrictions_based_on_operand_types(const struct brw_isa_info *isa,
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inst_dst_type(isa, inst) == BRW_TYPE_UB;
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if (dst_type_is_byte) {
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if (is_packed(exec_size * dst_stride, exec_size, dst_stride)) {
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if (is_packed(inst->exec_size * dst_stride, inst->exec_size, dst_stride)) {
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if (!inst_is_raw_move(isa, inst))
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ERROR("Only raw MOV supports a packed-byte destination");
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return error_msg;
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@ -969,7 +953,6 @@ general_restrictions_on_region_parameters(const struct brw_isa_info *isa,
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{
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const struct intel_device_info *devinfo = isa->devinfo;
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unsigned exec_size = 1 << brw_inst_exec_size(devinfo, inst->raw);
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struct string error_msg = { .str = NULL, .len = 0 };
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if (inst->num_sources == 3)
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@ -1030,13 +1013,13 @@ general_restrictions_on_region_parameters(const struct brw_isa_info *isa,
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#undef DO_SRC
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/* ExecSize must be greater than or equal to Width. */
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ERROR_IF(exec_size < width, "ExecSize must be greater than or equal "
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"to Width");
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ERROR_IF(inst->exec_size < width, "ExecSize must be greater than or equal "
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"to Width");
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/* If ExecSize = Width and HorzStride ≠ 0,
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* VertStride must be set to Width * HorzStride.
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*/
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if (exec_size == width && hstride != 0) {
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if (inst->exec_size == width && hstride != 0) {
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ERROR_IF(vstride != width * hstride,
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"If ExecSize = Width and HorzStride ≠ 0, "
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"VertStride must be set to Width * HorzStride");
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@ -1052,7 +1035,7 @@ general_restrictions_on_region_parameters(const struct brw_isa_info *isa,
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}
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/* If ExecSize = Width = 1, both VertStride and HorzStride must be 0. */
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if (exec_size == 1 && width == 1) {
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if (inst->exec_size == 1 && width == 1) {
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ERROR_IF(vstride != 0 || hstride != 0,
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"If ExecSize = Width = 1, both VertStride "
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"and HorzStride must be 0");
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@ -1075,7 +1058,7 @@ general_restrictions_on_region_parameters(const struct brw_isa_info *isa,
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assert(util_is_power_of_two_nonzero(reg_unit(devinfo)));
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unsigned grf_size_shift = ffs(REG_SIZE * reg_unit(devinfo)) - 1;
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for (int y = 0; y < exec_size / width; y++) {
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for (int y = 0; y < inst->exec_size / width; y++) {
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bool spans_grfs = false;
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unsigned offset = rowbase;
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unsigned first_grf = offset >> grf_size_shift;
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@ -1123,7 +1106,6 @@ special_restrictions_for_mixed_float_mode(const struct brw_isa_info *isa,
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if (!is_mixed_float(isa, inst))
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return error_msg;
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unsigned exec_size = 1 << brw_inst_exec_size(devinfo, inst->raw);
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bool is_align16 = brw_inst_access_mode(devinfo, inst->raw) == BRW_ALIGN_16;
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enum brw_reg_type src0_type = brw_inst_src0_type(devinfo, inst->raw);
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@ -1132,7 +1114,7 @@ special_restrictions_for_mixed_float_mode(const struct brw_isa_info *isa,
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enum brw_reg_type dst_type = brw_inst_dst_type(devinfo, inst->raw);
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unsigned dst_stride = STRIDE(brw_inst_dst_hstride(devinfo, inst->raw));
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bool dst_is_packed = is_packed(exec_size * dst_stride, exec_size, dst_stride);
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bool dst_is_packed = is_packed(inst->exec_size * dst_stride, inst->exec_size, dst_stride);
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/* From the SKL PRM, Special Restrictions for Handling Mixed Mode
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* Float Operations:
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@ -1152,7 +1134,7 @@ special_restrictions_for_mixed_float_mode(const struct brw_isa_info *isa,
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* "No SIMD16 in mixed mode when destination is f32. Instruction
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* execution size must be no more than 8."
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*/
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ERROR_IF(exec_size > 8 && devinfo->ver < 20 &&
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ERROR_IF(inst->exec_size > 8 && devinfo->ver < 20 &&
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dst_type == BRW_TYPE_F &&
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opcode != BRW_OPCODE_MOV,
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"Mixed float mode with 32-bit float destination is limited "
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@ -1210,7 +1192,7 @@ special_restrictions_for_mixed_float_mode(const struct brw_isa_info *isa,
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* Since oword-aligned packed f16 data would cross oword boundaries when
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* the execution size is larger than 8.
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*/
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ERROR_IF(exec_size > 8, "Align16 mixed float mode is limited to SIMD8");
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ERROR_IF(inst->exec_size > 8, "Align16 mixed float mode is limited to SIMD8");
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/* From the SKL PRM, Special Restrictions for Handling Mixed Mode
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* Float Operations:
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@ -1228,7 +1210,7 @@ special_restrictions_for_mixed_float_mode(const struct brw_isa_info *isa,
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* "No SIMD16 in mixed mode when destination is packed f16 for both
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* Align1 and Align16."
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*/
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ERROR_IF(exec_size > 8 && dst_is_packed &&
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ERROR_IF(inst->exec_size > 8 && dst_is_packed &&
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dst_type == BRW_TYPE_HF &&
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opcode != BRW_OPCODE_MOV,
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"Align1 mixed float mode is limited to SIMD8 when destination "
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@ -1272,7 +1254,7 @@ special_restrictions_for_mixed_float_mode(const struct brw_isa_info *isa,
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ERROR_IF(subreg % 16 != 0,
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"Align1 mixed mode packed half-float output must be "
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"oword aligned");
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ERROR_IF(exec_size > 8,
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ERROR_IF(inst->exec_size > 8,
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"Align1 mixed mode packed half-float output must not "
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"cross oword boundaries (max exec size is 8)");
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@ -1419,7 +1401,6 @@ region_alignment_rules(const struct brw_isa_info *isa,
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const brw_hw_decoded_inst *inst)
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{
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const struct intel_device_info *devinfo = isa->devinfo;
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unsigned exec_size = 1 << brw_inst_exec_size(devinfo, inst->raw);
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uint8_t dst_access_mask[32], src0_access_mask[32], src1_access_mask[32];
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struct string error_msg = { .str = NULL, .len = 0 };
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@ -1460,7 +1441,7 @@ region_alignment_rules(const struct brw_isa_info *isa,
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element_size = brw_type_size_bytes(type); \
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subreg = brw_inst_src ## n ## _da1_subreg_nr(devinfo, inst->raw); \
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grfs_accessed(devinfo, src ## n ## _access_mask, \
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exec_size, element_size, subreg, \
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inst->exec_size, element_size, subreg, \
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vstride, width, hstride)
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if (i == 0) {
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@ -1470,7 +1451,7 @@ region_alignment_rules(const struct brw_isa_info *isa,
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}
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#undef DO_SRC
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unsigned num_vstride = exec_size / width;
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unsigned num_vstride = inst->exec_size / width;
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unsigned num_hstride = width;
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unsigned vstride_elements = (num_vstride - 1) * vstride;
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unsigned hstride_elements = (num_hstride - 1) * hstride;
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@ -1487,17 +1468,17 @@ region_alignment_rules(const struct brw_isa_info *isa,
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enum brw_reg_type dst_type = inst_dst_type(isa, inst);
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unsigned element_size = brw_type_size_bytes(dst_type);
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unsigned subreg = brw_inst_dst_da1_subreg_nr(devinfo, inst->raw);
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unsigned offset = ((exec_size - 1) * stride * element_size) + subreg;
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unsigned offset = ((inst->exec_size - 1) * stride * element_size) + subreg;
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ERROR_IF(offset >= 64 * reg_unit(devinfo),
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"A destination cannot span more than 2 adjacent GRF registers");
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if (error_msg.str)
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return error_msg;
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grfs_accessed(devinfo, dst_access_mask, exec_size, element_size, subreg,
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exec_size == 1 ? 0 : exec_size * stride,
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exec_size == 1 ? 1 : exec_size,
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exec_size == 1 ? 0 : stride);
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grfs_accessed(devinfo, dst_access_mask, inst->exec_size, element_size, subreg,
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inst->exec_size == 1 ? 0 : inst->exec_size * stride,
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inst->exec_size == 1 ? 1 : inst->exec_size,
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inst->exec_size == 1 ? 0 : stride);
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unsigned dst_regs = registers_read(dst_access_mask);
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@ -1513,7 +1494,7 @@ region_alignment_rules(const struct brw_isa_info *isa,
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if (dst_regs == 2) {
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unsigned upper_reg_writes = 0, lower_reg_writes = 0;
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for (unsigned i = 0; i < exec_size; i++) {
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for (unsigned i = 0; i < inst->exec_size; i++) {
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if (dst_access_mask[i] == 2) {
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upper_reg_writes++;
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} else {
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@ -1802,7 +1783,7 @@ special_requirements_for_handling_double_precision_data_types(
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ERROR_IF(brw_inst_access_mode(devinfo, inst->raw) == BRW_ALIGN_16 &&
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dst_type_size == 8 &&
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(src0_type_size != 8 || src1_type_size != 8) &&
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brw_inst_exec_size(devinfo, inst->raw) > BRW_EXECUTE_2,
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inst->exec_size > 2,
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"In Align16 exec size cannot exceed 2 with a QWord destination "
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"and a non-QWord source");
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}
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@ -2214,26 +2195,22 @@ instruction_restrictions(const struct brw_isa_info *isa,
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MAX2(1, 32 / MAX2(src1_bits_per_element, src2_bits_per_element));
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if (devinfo->ver < 20) {
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ERROR_IF(brw_inst_exec_size(devinfo, inst->raw) != BRW_EXECUTE_8,
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"DPAS execution size must be 8.");
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ERROR_IF(inst->exec_size != 8, "DPAS execution size must be 8.");
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} else {
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ERROR_IF(brw_inst_exec_size(devinfo, inst->raw) != BRW_EXECUTE_16,
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"DPAS execution size must be 16.");
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ERROR_IF(inst->exec_size != 16, "DPAS execution size must be 16.");
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}
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const unsigned exec_size = devinfo->ver < 20 ? 8 : 16;
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const unsigned dst_subnr = brw_inst_dpas_3src_dst_subreg_nr(devinfo, inst->raw);
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const unsigned src0_subnr = brw_inst_dpas_3src_src0_subreg_nr(devinfo, inst->raw);
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const unsigned src1_subnr = brw_inst_dpas_3src_src1_subreg_nr(devinfo, inst->raw);
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const unsigned src2_subnr = brw_inst_dpas_3src_src2_subreg_nr(devinfo, inst->raw);
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/* Until HF is supported as dst type, this is effectively subnr == 0. */
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ERROR_IF(dst_subnr % exec_size != 0,
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ERROR_IF(dst_subnr % inst->exec_size != 0,
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"Destination subregister offset must be a multiple of ExecSize.");
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/* Until HF is supported as src0 type, this is effectively subnr == 0. */
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ERROR_IF(src0_subnr % exec_size != 0,
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ERROR_IF(src0_subnr % inst->exec_size != 0,
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"Src0 subregister offset must be a multiple of ExecSize.");
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ERROR_IF(src1_subnr != 0,
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@ -2348,7 +2325,7 @@ send_descriptor_restrictions(const struct brw_isa_info *isa,
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ERROR_IF(lsc_opcode_has_transpose(lsc_msg_desc_opcode(devinfo, desc)) &&
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lsc_msg_desc_transpose(devinfo, desc) &&
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brw_inst_exec_size(devinfo, inst->raw) != BRW_EXECUTE_1,
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inst->exec_size != 1,
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"Transposed vectors are restricted to Exec_Mask = 1.");
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break;
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@ -2386,11 +2363,14 @@ send_descriptor_restrictions(const struct brw_isa_info *isa,
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return error_msg;
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}
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static void
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static struct string
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brw_hw_decode_inst(const struct brw_isa_info *isa,
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brw_hw_decoded_inst *inst,
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const brw_inst *raw)
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{
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const struct intel_device_info *devinfo = isa->devinfo;
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struct string error_msg = { .str = NULL, .len = 0 };
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inst->raw = raw;
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inst->opcode = brw_inst_opcode(isa, raw);
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inst->num_sources = brw_num_sources_from_inst(isa, raw);
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@ -2398,6 +2378,23 @@ brw_hw_decode_inst(const struct brw_isa_info *isa,
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const struct opcode_desc *desc = brw_opcode_desc(isa, inst->opcode);
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assert(desc->ndst == 0 || desc->ndst == 1);
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inst->has_dst = desc->ndst == 1;
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enum brw_execution_size exec_size = brw_inst_exec_size(devinfo, raw);
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switch (exec_size) {
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case BRW_EXECUTE_1:
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case BRW_EXECUTE_2:
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case BRW_EXECUTE_4:
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case BRW_EXECUTE_8:
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case BRW_EXECUTE_16:
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case BRW_EXECUTE_32:
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inst->exec_size = 1 << exec_size;
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break;
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default:
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RETURN_ERROR("invalid execution size");
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break;
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}
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return error_msg;
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}
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bool
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@ -2412,7 +2409,7 @@ brw_validate_instruction(const struct brw_isa_info *isa,
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ERROR("Instruction not supported on this Gen");
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} else {
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brw_hw_decoded_inst decoded = {};
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brw_hw_decode_inst(isa, &decoded, inst);
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error_msg = brw_hw_decode_inst(isa, &decoded, inst);
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#define CHECK(func, args...) \
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do { \
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@ -2423,7 +2420,8 @@ brw_validate_instruction(const struct brw_isa_info *isa,
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} \
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} while (0)
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CHECK(invalid_values);
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if (error_msg.str == NULL)
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CHECK(invalid_values);
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if (error_msg.str == NULL) {
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CHECK(sources_not_null);
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