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Author SHA1 Message Date
Alyssa Rosenzweig
0255f554f3 panfrost: Advertise 16x16 tiled AFBC 
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16697>
 2022-05-26 15:56:32 +00:00
Alyssa Rosenzweig
3fbfd356af panfrost: Add helper checking tiled AFBC support 
Tiled AFBC support was introduced with v7. Add a helper encoding this fact.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16697>
 2022-05-26 15:56:32 +00:00
Alyssa Rosenzweig
5fa274fee4 panfrost: Handle AFBC Tiled 
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16697>
 2022-05-26 15:56:32 +00:00
Alyssa Rosenzweig
b63dad3ce5 panfrost: Put comment in correct #ifdef 
Minor fix to make the code less confusing.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16697>
 2022-05-26 15:56:32 +00:00
Alyssa Rosenzweig
bd529b7983 panfrost: Fix AFBC flags on v6 
Tiled headers and bounds checking were introduced with v7. The flags don't exist
on v6. Fix the XML accordingly so we don't accidentally use features too new for
the hardware.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16697>
 2022-05-26 15:56:32 +00:00
Alyssa Rosenzweig
166d879ff0 panfrost: Add 1x1 layout unit tests 
These check the alignments are correct. Of course, ideally these cases aren't
hit in practice, since it's a waste of memory.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16697>
 2022-05-26 15:56:32 +00:00
Alyssa Rosenzweig
65ba39f84c panfrost: Add a tiled 16x16 layout unit test 
To exercise the layout code introduced in this series.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16697>
 2022-05-26 15:56:32 +00:00
Alyssa Rosenzweig
d11945cd85 panfrost: Calculate header_size based on row_stride 
The header size is the header stride times the number of rows in the header
(number of tiles of superblocks). We already calculate the header stride, so
eliminate the separate header size calculation.

Delete the old header size calculation. It has no notion of wide blocks, let
alone tiled AFBC headers.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16697>
 2022-05-26 15:56:32 +00:00
Alyssa Rosenzweig
0cf6091bd0 panfrost: Add 3D texture layout unit test 
3D AFBC is pretty subtle, let's make sure we have adequate unit test coverage.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16697>
 2022-05-26 15:56:32 +00:00
Alyssa Rosenzweig
5944bbfa94 panfrost: Add AFBC stride unit tests 
Demonstrating correctness of the low level calculations.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16697>
 2022-05-26 15:56:32 +00:00
Alyssa Rosenzweig
544a8894fc panfrost: Align layouts to tiles of superblocks 
Required to satisfy the alignment constraints on tiled AFBC.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16697>
 2022-05-26 15:56:32 +00:00
Alyssa Rosenzweig
9c9b7f7a42 panfrost: Support tiled AFBC in stride helpers 
Part 1 of tiled AFBC. This requires modifier information.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16697>
 2022-05-26 15:56:32 +00:00
Alyssa Rosenzweig
5c86f53112 panfrost: Add pan_afbc_tile_size helper 
To unify calculations with linear and tiled AFBC formats.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16697>
 2022-05-26 15:56:32 +00:00
Alyssa Rosenzweig
b7c18160d3 panfrost: Fix is_wide return type 
By inspection.

Fixes: e4ee2c213a ("panfrost: Extract panfrost_afbc_is_wide helper")
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16697>
 2022-05-26 15:56:32 +00:00
Alyssa Rosenzweig
6b0ff7da48 panfrost: Extract pan_afbc_row_stride helper 
Extract a helper for calculating AFBC strides. This is used in two places in
pan_layout. It will need extension for tiled AFBC, and the extended version
could benefit from unit testing.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16697>
 2022-05-26 15:56:32 +00:00
Alyssa Rosenzweig
d8a4c9b505 panfrost: Extract afbc_stride_blocks helper 
Let's keep all the AFBC computations inside the layout code, to keep pan_cs
dumb. This helper will need some extension for tiled AFBC.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16697>
 2022-05-26 15:56:32 +00:00
Alyssa Rosenzweig
96d9093c19 pan/bi: Allow CSEing LEA_BUF_IMM 
Cleans up the code gen a lot in varying shaders. Instruction count regression
due to how we handle 64-bit on Valhall. (TODO: A better solution for that...)

total instructions in shared programs: 2730186 -> 2736193 (0.22%)
instructions in affected programs: 775825 -> 781832 (0.77%)
helped: 2010
HURT: 4433
helped stats (abs) min: 1.0 max: 18.0 x̄: 2.16 x̃: 2
helped stats (rel) min: 0.16% max: 26.67% x̄: 3.75% x̃: 2.22%
HURT stats (abs)   min: 1.0 max: 10.0 x̄: 2.33 x̃: 2
HURT stats (rel)   min: 0.20% max: 23.08% x̄: 4.79% x̃: 2.79%
95% mean confidence interval for instructions value: 0.87 1.00
95% mean confidence interval for instructions %-change: 1.98% 2.27%
Instructions are HURT.

total cycles in shared programs: 161178.77 -> 144303.77 (-10.47%)
cycles in affected programs: 85720 -> 68845 (-19.69%)
helped: 6910
HURT: 0
helped stats (abs) min: 1.0 max: 18.0 x̄: 2.44 x̃: 2
helped stats (rel) min: 1.05% max: 41.18% x̄: 19.72% x̃: 20.00%
95% mean confidence interval for cycles value: -2.48 -2.41
95% mean confidence interval for cycles %-change: -19.86% -19.58%
Cycles are helped.

total cvt in shared programs: 13655.45 -> 14013 (2.62%)
cvt in affected programs: 2978.06 -> 3335.61 (12.01%)
helped: 381
HURT: 5242
helped stats (abs) min: 0.015625 max: 0.0625 x̄: 0.02 x̃: 0
helped stats (rel) min: 0.37% max: 50.00% x̄: 7.61% x̃: 3.85%
HURT stats (abs)   min: 0.015625 max: 0.296875 x̄: 0.07 x̃: 0
HURT stats (rel)   min: 0.00% max: 400.00% x̄: 28.51% x̃: 16.00%
95% mean confidence interval for cvt value: 0.06 0.06
95% mean confidence interval for cvt %-change: 25.13% 27.00%
Cvt are HURT.

total ls in shared programs: 147856 -> 130980 (-11.41%)
ls in affected programs: 85725 -> 68849 (-19.69%)
helped: 6911
HURT: 0
helped stats (abs) min: 1.0 max: 18.0 x̄: 2.44 x̃: 2
helped stats (rel) min: 1.05% max: 41.18% x̄: 19.72% x̃: 20.00%
95% mean confidence interval for ls value: -2.48 -2.41
95% mean confidence interval for ls %-change: -19.86% -19.58%
Ls are helped.

total quadwords in shared programs: 1483576 -> 1486872 (0.22%)
quadwords in affected programs: 73816 -> 77112 (4.47%)
helped: 286
HURT: 698
helped stats (abs) min: 8.0 max: 8.0 x̄: 8.00 x̃: 8
helped stats (rel) min: 2.38% max: 50.00% x̄: 16.83% x̃: 16.67%
HURT stats (abs)   min: 8.0 max: 8.0 x̄: 8.00 x̃: 8
HURT stats (rel)   min: 2.78% max: 100.00% x̄: 37.38% x̃: 16.67%
95% mean confidence interval for quadwords value: 2.89 3.80
95% mean confidence interval for quadwords %-change: 19.02% 24.22%
Quadwords are HURT.

total threads in shared programs: 53186 -> 53189 (<.01%)
threads in affected programs: 3 -> 6 (100.00%)
helped: 3
HURT: 0
helped stats (abs) min: 1.0 max: 1.0 x̄: 1.00 x̃: 1
helped stats (rel) min: 100.00% max: 100.00% x̄: 100.00% x̃: 100.00%

total fills in shared programs: 2172 -> 2163 (-0.41%)
fills in affected programs: 11 -> 2 (-81.82%)
helped: 1
HURT: 0

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16710>
 2022-05-25 15:51:15 +00:00
Alyssa Rosenzweig
569e5dc745 pan/bi: Schedule for pressure pre-RA 
Add a bottom-up pre-RA list scheduler that aims to reduce register pressure,
roughly the same as we use on Midgard to great effect. It uses a simple
heuristic: greedily select instructions that have reduce liveness.  To avoid
regressions, the algorithm throws away schedules that increase maximum number of
lives (used as an estimate of register pressure -- if we had SSA form, this
would be exact).

We might be better off using Sarkar. But for something I could type out in an
afternoon, I'll happily accept a >50% reduction in spills. Instruction count is
regressed due to extra moves around the blend shader ABI in some cases, at least
on Bifrost this is mostly hidden by the clause scheduler. Thread count and
spills/fills are both much improved here.

There are numerous opportunities for future improvements to pre-RA scheduling:

* Better heuristics? (Something more global than liveness alone)
* Reducing false dependencies with memory access
* Improve ILP for message-passing instructions? This is a tradeoff.
* Simplify the code if we have SSA in the future.

But for now, I think this is well worth it already.

v2: Various clean-ups and memory leak fix (Icecream95). Reduce false
dependencies to eliminate spilling in more shaders.

shader-db stats on Mali-G52:

total instructions in shared programs: 2438841 -> 2439698 (0.04%)
instructions in affected programs: 1206421 -> 1207278 (0.07%)
helped: 3113
HURT: 4011
helped stats (abs) min: 1.0 max: 50.0 x̄: 3.25 x̃: 2
helped stats (rel) min: 0.13% max: 44.83% x̄: 4.09% x̃: 2.11%
HURT stats (abs)   min: 1.0 max: 18.0 x̄: 2.73 x̃: 2
HURT stats (rel)   min: 0.11% max: 57.14% x̄: 3.86% x̃: 2.07%
95% mean confidence interval for instructions value: 0.02 0.22
95% mean confidence interval for instructions %-change: 0.23% 0.54%
Instructions are HURT.

total tuples in shared programs: 1927077 -> 1946583 (1.01%)
tuples in affected programs: 1118627 -> 1138133 (1.74%)
helped: 2874
HURT: 6295
helped stats (abs) min: 1.0 max: 82.0 x̄: 3.51 x̃: 2
helped stats (rel) min: 0.17% max: 33.33% x̄: 4.60% x̃: 3.57%
HURT stats (abs)   min: 1.0 max: 47.0 x̄: 4.70 x̃: 3
HURT stats (rel)   min: 0.20% max: 50.00% x̄: 5.16% x̃: 4.32%
95% mean confidence interval for tuples value: 2.00 2.25
95% mean confidence interval for tuples %-change: 1.97% 2.23%
Tuples are HURT.

total clauses in shared programs: 356053 -> 357793 (0.49%)
clauses in affected programs: 151578 -> 153318 (1.15%)
helped: 2196
HURT: 3813
helped stats (abs) min: 1.0 max: 49.0 x̄: 2.16 x̃: 1
helped stats (rel) min: 0.18% max: 69.01% x̄: 10.26% x̃: 8.33%
HURT stats (abs)   min: 1.0 max: 25.0 x̄: 1.70 x̃: 1
HURT stats (rel)   min: 0.57% max: 66.67% x̄: 10.64% x̃: 8.33%
95% mean confidence interval for clauses value: 0.22 0.36
95% mean confidence interval for clauses %-change: 2.68% 3.33%
Clauses are HURT.

total cycles in shared programs: 167761.17 -> 167922.04 (0.10%)
cycles in affected programs: 24494.21 -> 24655.08 (0.66%)
helped: 862
HURT: 3054
helped stats (abs) min: 0.041665999999999315 max: 53.0 x̄: 0.69 x̃: 0
helped stats (rel) min: 0.28% max: 76.81% x̄: 5.65% x̃: 3.03%
HURT stats (abs)   min: 0.041665999999999315 max: 2.0416659999999993 x̄: 0.25 x̃: 0
HURT stats (rel)   min: 0.26% max: 41.18% x̄: 4.91% x̃: 3.92%
95% mean confidence interval for cycles value: -0.04 0.12
95% mean confidence interval for cycles %-change: 2.36% 2.81%
Inconclusive result (value mean confidence interval includes 0).

total arith in shared programs: 73875.37 -> 74393.17 (0.70%)
arith in affected programs: 43142.42 -> 43660.21 (1.20%)
helped: 3632
HURT: 5443
helped stats (abs) min: 0.041665999999999315 max: 1.2083360000000027 x̄: 0.15 x̃: 0
helped stats (rel) min: 0.22% max: 100.00% x̄: 6.70% x̃: 4.76%
HURT stats (abs)   min: 0.041665999999999315 max: 2.0416659999999993 x̄: 0.19 x̃: 0
HURT stats (rel)   min: 0.00% max: 166.67% x̄: 5.91% x̃: 4.08%
95% mean confidence interval for arith value: 0.05 0.06
95% mean confidence interval for arith %-change: 0.65% 1.07%
Arith are HURT.

total texture in shared programs: 11936 -> 11936 (0.00%)
texture in affected programs: 0 -> 0
helped: 0
HURT: 0

total vary in shared programs: 4180.88 -> 4180.88 (0.00%)
vary in affected programs: 0 -> 0
helped: 0
HURT: 0

total ldst in shared programs: 137551 -> 137028 (-0.38%)
ldst in affected programs: 834 -> 311 (-62.71%)
helped: 13
HURT: 0
helped stats (abs) min: 15.0 max: 53.0 x̄: 40.23 x̃: 53
helped stats (rel) min: 19.15% max: 100.00% x̄: 68.11% x̃: 76.81%
95% mean confidence interval for ldst value: -50.49 -29.98
95% mean confidence interval for ldst %-change: -84.37% -51.84%
Ldst are helped.

total quadwords in shared programs: 1684883 -> 1692021 (0.42%)
quadwords in affected programs: 949463 -> 956601 (0.75%)
helped: 3981
HURT: 5098
helped stats (abs) min: 1.0 max: 86.0 x̄: 3.53 x̃: 3
helped stats (rel) min: 0.18% max: 33.33% x̄: 5.82% x̃: 4.48%
HURT stats (abs)   min: 1.0 max: 50.0 x̄: 4.15 x̃: 3
HURT stats (rel)   min: 0.17% max: 50.00% x̄: 5.11% x̃: 3.85%
95% mean confidence interval for quadwords value: 0.67 0.90
95% mean confidence interval for quadwords %-change: 0.17% 0.47%
Quadwords are HURT.

total threads in shared programs: 53276 -> 53653 (0.71%)
threads in affected programs: 581 -> 958 (64.89%)
helped: 445
HURT: 68
helped stats (abs) min: 1.0 max: 1.0 x̄: 1.00 x̃: 1
helped stats (rel) min: 100.00% max: 100.00% x̄: 100.00% x̃: 100.00%
HURT stats (abs)   min: 1.0 max: 1.0 x̄: 1.00 x̃: 1
HURT stats (rel)   min: 50.00% max: 50.00% x̄: 50.00% x̃: 50.00%
95% mean confidence interval for threads value: 0.68 0.79
95% mean confidence interval for threads %-change: 75.70% 84.53%
Threads are helped.

total preloads in shared programs: 116312 -> 116312 (0.00%)
preloads in affected programs: 0 -> 0
helped: 0
HURT: 0

total loops in shared programs: 128 -> 128 (0.00%)
loops in affected programs: 0 -> 0
helped: 0
HURT: 0

total spills in shared programs: 92 -> 37 (-59.78%)
spills in affected programs: 55 -> 0
helped: 13
HURT: 0

total fills in shared programs: 658 -> 190 (-71.12%)
fills in affected programs: 468 -> 0
helped: 13
HURT: 0

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16378>
 2022-05-25 14:40:12 +00:00
Alyssa Rosenzweig
2fb5ceab7a pan/bi: Recoalesce tied operands after spilling 
Otherwise we can fail to allocate tied operands if we spill the tied operand.
Seen in shaders/android/com.miHoYo.GenshinImpact/16.shader_test with a
particularly bad scheduling causing excessive spilling.

No shader-db changes.

Fixes: bc17288697 ("pan/bi: Lower split/collect before RA")
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16378>
 2022-05-25 14:40:12 +00:00
Icecream95
a4323b0979 panfrost: Only write depth / stencil once if MRT is used 
We can't assume that RT0 will be written, so this has to be based on
whether a combined store has already been emitted, not the location of
the store.

Emit a non-special combined_store intrinsic that only writes colour
for the other RTs, as reordering stores breaks the Midgard compiler.

Fixes: d37e901e35 ("pan/mdg: Add new depth store lowering")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6527
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16685>
 2022-05-24 16:13:33 +00:00
Icecream95
0a53ebabcd pan/mdg: Read base for combined stores 
Fixes depth/stencil writes with MRT.

Fixes: b3d7272753 ("pan/mdg: Don't read base for combined stores")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16685>
 2022-05-24 16:13:33 +00:00
Icecream95
f1a226dd24 pan/bi: Read base for combined stores 
Fixes depth/stencil writes with MRT.

Fixes: 996645e479 ("pan/bi: Don't read base for combined stores")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16685>
 2022-05-24 16:13:33 +00:00
Icecream95
9f9ed959bd nir: Add store_combined_output_pan BASE back 
It's meaningful for this intrinsic and so does not add noise to the
lowering pass.

(Although dual-source writes must be to RT 0, depth and stencil
writes, which store_combined_output_pan is also used for, can still be
done with MRT enabled.)

Fixes: 5c168f09eb ("nir: Eliminate store_combined_output_pan BASE")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16685>
 2022-05-24 16:13:33 +00:00
Icecream95
2f2ddfa0ac panfrost: Move patched_s out of the pan_blitter_views struct 
The struct is returned from a function, so in debug builds the address
may change after returning, and pointers to patched_s will be broken.

Pass the pointer to the patched stencil view as a parameter to
pan_preload_get_views to avoid this.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16343>
 2022-05-20 23:17:07 +00:00
Icecream95
f1f39fa645 panfrost: Increase the limit for blend shader variants 
Qt uses blend constants to set text colour, this will allow more
colours onscreen before thrashing happens.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16343>
 2022-05-20 23:17:07 +00:00
Icecream95
80404c8b64 panfrost: Copy blend constant into variant even when reusing it 
Otherwise future lookups will match searches for the old constant.

Fixes: bbff09b952 ("panfrost: Move the blend shader cache at the device level")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6355
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16343>
 2022-05-20 23:17:07 +00:00
Alyssa Rosenzweig
d6ece34d0c pan/va: Use ^ instead of ` to indicate last-use 
This syncs the ISA syntax with other Valhall ISA users. It's also somewhat
easier to read.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585>
 2022-05-19 16:08:26 +00:00
Alyssa Rosenzweig
9fb8ca1851 pan/va: Remove DISCARD.f32 destination 
It doesn't actually write anything. This is a pointless divergence from Bifrost.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585>
 2022-05-19 16:08:26 +00:00
Alyssa Rosenzweig
444469d64e pan/va: Handle 2-src blend in lower_split_src 
Fixes assertion fail in shaders/dolphin/smg.1.shader_test

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585>
 2022-05-19 16:08:26 +00:00
Alyssa Rosenzweig
0576cad958 pan/bi: Validate vector widths 
Now that our IR is much more strongly typed, and RA code quality depends on
correct typing, add a validation pass to make sure we didn't screw it up. This
pass found a massive number of bugs in early versions of this series.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585>
 2022-05-19 16:08:26 +00:00
Alyssa Rosenzweig
4c1bb23a86 pan/bi: Validate preload constraints are satisfied 
We tightened the rules around preloading substantially and take advantage of the
rules in RA. The safe helpers it introduced should ensure the rules are
followed, but just in case, add a validation pass to check our work. This pass
found (multiple) bugs in early versions of this series.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585>
 2022-05-19 16:08:26 +00:00
Alyssa Rosenzweig
3636cddde1 pan/bi: See through splits for var_tex fusion 
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585>
 2022-05-19 16:08:26 +00:00
Alyssa Rosenzweig
1f25f78a9f pan/bi: Optimize split of collect 
Required to get decent codegen from UBO pushing.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585>
 2022-05-19 16:08:26 +00:00
Alyssa Rosenzweig
4a8bde2190 pan/bi: Don't propagate discard 
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585>
 2022-05-19 16:08:26 +00:00
Alyssa Rosenzweig
d81b872465 pan/bi: Remove liveness metadata tracking 
We don't use it for anything, and with no pass infrastructure it's just an
accident waiting to happen.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585>
 2022-05-19 16:08:26 +00:00
Alyssa Rosenzweig
3df5446cbd pan/bi: Simplify register precolouring in the IR 
In the current IR, any register may be preloaded by reading it anywhere, and any
register may be precoloured by writing it anywhere. This is convenient for
instruction selection, but requires the register allocator to do considerable
gymnastics to ensure it doesn't clobber precoloured registers. It also breaks
the purity of our SSA representation, which complicates optimization passes
(e.g. copyprop).

Let's trade some instruction selection complexity for simplifying register
allocation by constraining how register precolouring works. Under the new model:

* Registers may only be preloaded at the start of the program.
* Precoloured destinations are handled explicitly by RA.

Internally, a stronger invariant is placed for preloading: registers may only be
preloaded by MOV.i32 instructions at the beginning of the block, and these moves
must be unique. These invariants ensure RA can trivially coalesce the moves.

A bi_preload helper is added as a safe version of bi_register respecting these
invariants, allowing a smooth transition for instruction selection.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585>
 2022-05-19 16:08:26 +00:00
Alyssa Rosenzweig
dab5b62ecf pan/bi: Remove bi_word and bi_word_node 
They are no longer used, as offsets are no longer used for normal values (only for
FAU). Keep it like that.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585>
 2022-05-19 16:08:26 +00:00
Alyssa Rosenzweig
f0184cf218 pan/bi: Scalarize copyprop 
Reduces memory footprint.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585>
 2022-05-19 16:08:26 +00:00
Alyssa Rosenzweig
c6349278f9 pan/bi: Scalarize modifier propagation 
Reduces memory footprint.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585>
 2022-05-19 16:08:26 +00:00
Alyssa Rosenzweig
e332e2edc1 pan/bi: Scalarize bi_opt_cse 
Reduces memory footprint.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585>
 2022-05-19 16:08:26 +00:00
Alyssa Rosenzweig
187dd382cb pan/bi: Scalarize bi_lower_swizzle 
Reduces memory footprint.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585>
 2022-05-19 16:08:26 +00:00
Alyssa Rosenzweig
5b1c642cee pan/va: Don't use bi_word in FAU unit test 
It will be removed shortly, as the FAU construction helper should be used
instead.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585>
 2022-05-19 16:08:26 +00:00
Alyssa Rosenzweig
67569b3c23 pan/va: Use split for 64-bit lowering 
Written in this way, this pass looks pretty silly...

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585>
 2022-05-19 16:08:26 +00:00
Alyssa Rosenzweig
5febeae58e pan/bi: Emit collect and split 
..Rather than using offsets during instruction selection.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585>
 2022-05-19 16:08:26 +00:00
Alyssa Rosenzweig
4731e9e55a pan/bi: Simplfy BLEND emit 
We don't need to collect anything, now that Valhall handles this case correctly.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585>
 2022-05-19 16:08:26 +00:00
Alyssa Rosenzweig
7bfaa119f4 pan/bi: Lift split/collect cache from AGX 
Design based on ACO (and fruitful discussions with Daniel).

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585>
 2022-05-19 16:08:26 +00:00
Alyssa Rosenzweig
8fdb01b96f pan/bi: Create COLLECT during isel 
This transitions us away from the fake SSA we currently use for vectors.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585>
 2022-05-19 16:08:26 +00:00
Alyssa Rosenzweig
5c0977d230 pan/bi: Expand MAX_DESTS to 4 
For splits.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585>
 2022-05-19 16:08:26 +00:00
Alyssa Rosenzweig
9924e6f291 pan/bi: Fix mov and pack_32_2x16 
Move can take in a vector and write a scalar, depending on the swizzle. We need
to handle this case. Split out mov and pack_32_2x16 so we can specify correct
behaviour for both. Also drop unused 1-bit boolean stuff which obscured the fix.

Fixes: 76cea8e27b ("panfrost: Fix pack_32_2x16 implementation")
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585>
 2022-05-19 16:08:26 +00:00
Alyssa Rosenzweig
bc17288697 pan/bi: Lower split/collect before RA 
For transitioning to the new scalarized IR.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585>
 2022-05-19 16:08:26 +00:00