Commit graph

88844 commits

Author SHA1 Message Date
Ilia Mirkin
ab00a41a6e nvc0/ir: make it possible to have the flags def in def0
There's all kinds of logic that doesn't like there being holes in defs
or srcs lists. Avoid them. This also fixes the sched logic for maxwell.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2017-02-09 12:57:48 -05:00
Ilia Mirkin
61d7676df7 nvc0/ir: add support for 64-bit shift lowering on SM20/SM30
Unfortunately there is no SHF.L/SHF.R instruction pre-SM35. So we have
to do a bit more work to get the job done.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2017-02-09 12:57:48 -05:00
Ilia Mirkin
1aefd6159c nvc0/ir: add support for all the new int64 tgsi opcodes
A few thoughts:
 - Some of that LegalizeSSA logic should really live much earlier and be
   subject to the likes of DCE and other useful passes
 - Some of the "lowering" done in from_tgsi should be done later so that
   proper optimization might be done.

However this all works and the above can be improved upon later.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2017-02-09 12:57:48 -05:00
Pierre Moreau
009c54aa7a nv50/ir: Split 64-bit integer MAD/MUL operations
Hardware does not support 64-bit integers MAD and MUL operations, so we need
to transform them in 32-bit operations.

Signed-off-by: Pierre Moreau <pierre.morrow@free.fr>
2017-02-09 12:57:48 -05:00
Ilia Mirkin
22c705ea8c nvc0/ir: add a "high" subop for shifts, emit shf.l/shf.r for 64-bit
Note that this is not available for SM20/SM30.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2017-02-09 12:57:48 -05:00
Ilia Mirkin
2e986fa806 nvc0/ir: fix SET and SLCT emission
We were never emitting a .X flag for consuming condition code on SET,
and weren't emitting a signed type for SLCT comparison. Discovered while
working on int64 logic.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2017-02-09 12:57:48 -05:00
Ilia Mirkin
eac5099c11 nvc0/ir: add support for emitting partial min/max ops for int64
These operations allow you to compute min/max on arbitrary-width
integers, 32 bits at a time.

Note that the low/med ops implicitly set the condition code, and the
med/high ops implicitly consume it.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2017-02-09 12:57:48 -05:00
Ilia Mirkin
b090033087 gallium: add separate PIPE_CAP_INT64_DIVMOD
Nouveau does not currently have logic to implement this as a library
function. Even though such a library could be written, there's no big
advantage to do it that way for now given that int64 is a very uncommon
use-case. Allow a driver to expose INT64 without supporting division and
modulo operations.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-02-09 12:57:21 -05:00
Eric Engestrom
6a71a69a12 docs: improve the list of gl implementations
Suggested-by: Emil Velikov <emil.l.velikov@gmail.com>
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
2017-02-09 15:45:08 +00:00
Eric Engestrom
8278f1ec35 docs: improve the list of implemented APIs
Suggested-by: Emil Velikov <emil.l.velikov@gmail.com>
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
2017-02-09 15:44:51 +00:00
Matt Turner
d7a0486a9e glsl: Allow compatibility shaders with MESA_GL_VERSION_OVERRIDE=...
Previously if you used MESA_GL_VERSION_OVERRIDE=3.3COMPAT, Mesa exposed
an OpenGL 3.3 compatibility profile context (with various unimplemented
features and bugs), but still refused to compile shaders with

   #version 330 compatibility

This patch simply adds a small bit of plumbing to let that through.

Of course the same caveats apply: compatibility profile is still not
supported (and will not be supported), so there are no guarantees that
anything will work.

Tested-by: Dylan Baker <dylan@pnwbakers.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2017-02-09 15:14:43 +00:00
Eric Engestrom
89b4176eb1 docs: reword sentence that my brain can't parse
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Elie Tournier <tournier.elie@gmail.com>
2017-02-09 13:04:16 +00:00
Eric Engestrom
30cf9ffb59 docs: https all the links \o/
Most of them already redirected to https anyway, so we might as well
avoid the redirection and the security implications by linking directly
to the right protocol.

Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Brian Paul <brianp@vmware.com>
2017-02-09 11:28:15 +00:00
Eric Engestrom
2b0fe3cff7 docs: fix gallium wiki link in relnotes
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Brian Paul <brianp@vmware.com>
2017-02-09 11:28:10 +00:00
Eric Engestrom
9f8a6a5b79 docs: update 'thanks' for hosting
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Brian Paul <brianp@vmware.com>
2017-02-09 11:26:22 +00:00
Samuel Iglesias Gonsálvez
ca16f0a282 i965/fs: add support for int64 to bool conversion
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99660
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2017-02-09 10:18:34 +01:00
Samuel Iglesias Gonsálvez
824e1bb078 nir: add opcode to perform int64 to bool conversions
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99660
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2017-02-09 10:18:34 +01:00
Samuel Iglesias Gonsálvez
7ab26613db i965/fs: Add support for nir_op_[iu]2[iu]32
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99660
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2017-02-09 10:18:34 +01:00
Samuel Iglesias Gonsálvez
7b5834ff54 i965/fs: Add support for nir_op_[iu]642f
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99660
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2017-02-09 10:18:34 +01:00
Samuel Iglesias Gonsálvez
b115407d75 i965/fs: legalize [u]int64 to 32-bit data conversions in lower_d2x
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99660
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2017-02-09 10:18:34 +01:00
Jason Ekstrand
8734461c58 i965/fs: Add support for nir_op_[iu]642d
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
2017-02-09 10:18:34 +01:00
Jason Ekstrand
91d2d26f33 i965: Allow int64 conversion operations in channel_expressions
This fixes 143 of the new piglit tests added by Nicolai

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
2017-02-09 10:18:34 +01:00
Timothy Arceri
f3d911463e util/disk_cache: stop using ralloc_asprintf() unnecessarily
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
2017-02-09 14:11:24 +11:00
Timothy Arceri
0bf21519b7 glsl: add param to force shader recompile
This will be used to skip checking the cache and force a recompile.

Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
2017-02-09 12:22:56 +11:00
Timothy Arceri
4026b45bbc util: add a disk_cache_remove() function
This will be used to remove cache items created with old versions
of Mesa or other invalid cache items from the cache.

V2: rename stub function (cache_* funtions were renamed disk_cache_*)
in master.

Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
2017-02-09 12:22:56 +11:00
Timothy Arceri
a3fd8bb8c5 st/mesa/i965: create link status enum
For the on-disk shader cache we want to be able to differentiate
between a program that was linked and one that was loaded from cache.

V2:
 - don't return the new enum directly to the application when queried,
   instead return GL_TRUE or GL_FALSE as required. Fixes google-chrome
   corruptions when using cache.

Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
2017-02-09 12:22:56 +11:00
Brian Paul
ac5845453c docs: update intro.html to mention new APIs, etc
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
2017-02-09 00:02:20 +00:00
Brian Paul
b2722a8970 docs: the site is now hosted by freedesktop.org
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
2017-02-09 00:02:13 +00:00
Bas Nieuwenhuizen
f22836dbdd radv: Add CPU color packing for VK_FORMAT_A2B10G10R10_UNORM_PACK32.
For allowing fast color clears in the main render targets of dota2.

[airlied: fix clear_vals[1] as suggested by Andres.

Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-02-08 22:43:11 +00:00
Roland Scheidegger
f64d74aa19 mesa: (trivial) include <inttypes.h> for PRIx64 macros
Fixes a compile error with mingw.
2017-02-08 21:56:16 +01:00
Tim Rowley
c1aa444a3e swr: [rasterizer jitter] Pass LLVM-IR size into jitter
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2017-02-08 13:58:13 -06:00
Tim Rowley
e0a829d320 swr: [rasterizer core] Frontend SIMD16 WIP
Removed temporary scafolding in PA, widended the PA_STATE interface
for SIMD16, and implemented PA_STATE_CUT and PA_TESS for SIMD16.

PA_STATE_CUT and PA_TESS now work in SIMD16.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2017-02-08 13:58:06 -06:00
Tim Rowley
79174e52b5 swr: [rasterizer jitter] Disable unsafe FP optimizations in the jitter
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2017-02-08 13:58:00 -06:00
Tim Rowley
db599e316a swr: [rasterizer core] Frontend SIMD16 WIP
Widen simdvertex to SIMD16/simd16vertex in frontend for passing VS
attributes from VS to PA.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2017-02-08 13:57:52 -06:00
Tim Rowley
09c54cfd2d swr: [rasterizer jitter] Add DEBUGTRAP jit builder function
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2017-02-08 13:57:47 -06:00
Tim Rowley
b01f26e005 swr: [rasterizer jitter] Multisample blend jit fix
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2017-02-08 13:57:41 -06:00
Tim Rowley
8780706c62 swr: [rasterizer jitter] Change SimdVector representation to array
Make all SimdVectors in LLVM represented as simdscalar[4] rather
than a struct.

Fixes issues with promotion of values from i32 to i64 to match
register width.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2017-02-08 13:57:33 -06:00
Tim Rowley
d159b0bf34 swr: [rasterizer jitter] Fix issues with stream-out on llvm>=3.8
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2017-02-08 13:57:27 -06:00
Tim Rowley
8423ad437b swr: [rasterizer jitter] Adjust jitter header includes
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2017-02-08 13:57:20 -06:00
Tim Rowley
feecd7dcf5 swr: [rasterizer core] Frontend SIMD16 WIP
SIMD16 Primitive Assembly (PA) only supports TriList and RectList.

CUT_AWARE_PA, TESS, GS, and SO disabled in the SIMD16 front end.

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
2017-02-08 13:57:10 -06:00
Eric Engestrom
a618d6c3e9 docs: update package contents
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
2017-02-08 12:00:28 -07:00
Eric Engestrom
06e40dc671 docs: fix unpacking instructions
File names were wrong, file formats were wrong, bunzip command was
wrong...

I also removed all but the simplest example; people who use pipes already
know how to untar, so let's simplify and remove potential confusion for
non-tech-savvy users.

Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
2017-02-08 12:00:24 -07:00
Eric Engestrom
d7e1a16f1a docs: remove dead 'beta' link
Release candidates haven't been in a 'beta' subdir in a long time, so let's
replace the dead link with an explanation instead.

Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
2017-02-08 12:00:19 -07:00
Eric Engestrom
5b10c362de docs: add a note about the new version scheme
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
2017-02-08 12:00:14 -07:00
Bartosz Tomczyk
94262e5f5d r600/sb: Fix memory leak
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2017-02-08 17:36:05 +01:00
Timothy Arceri
90014d0766 mesa: use PRId64/PRIu64 when printing 64-bit ints
V2: actually use PRIu64

Reviewed-by: Dave Airlie <airlied@redhat.com>
2017-02-08 13:50:01 +11:00
Dave Airlie
c674f11e42 mesa/st: fix strict aliasing issue in int64 code.
This fixes the int64 code same as the double code.

Reviewed-by: Timothy Arceri <t_arceri@yahoo.com.au>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-02-08 02:13:07 +00:00
Dave Airlie
30cff4f5f7 mesa/uniform: fix strict aliasing issues with int64 code.
This fixes these like the double version does.

Reviewed-by: Timothy Arceri <t_arceri@yahoo.com.au>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-02-08 02:12:31 +00:00
Dave Airlie
6d5d6dad20 radv: handle dcc in explicit image resolve path. (v2)
We need to initialize dcc like we do in the subpass path.

v2: fix initial/final layouts
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-02-07 23:31:08 +00:00
Bas Nieuwenhuizen
0d1283850b radv: Enable fast clears by default.
Works for me on dota2 and talos now.

Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Andres Rodriguez <andresx7@gmail.com>
2017-02-07 22:58:06 +01:00