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nvc0/ir: make it possible to have the flags def in def0

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There's all kinds of logic that doesn't like there being holes in defs
or srcs lists. Avoid them. This also fixes the sched logic for maxwell.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
This commit is contained in:
Ilia Mirkin 2017-02-05 18:09:02 -05:00
parent 61d7676df7
commit ab00a41a6e
5 changed files with 15 additions and 12 deletions
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2
src/gallium/drivers/nouveau/codegen/nv50_ir.h
View file

@ -662,7 +662,7 @@ public:
inline const Symbol *asSym() const;
inline const ImmediateValue *asImm() const;
inline bool inFile(DataFile f) { return reg.file == f; }
inline bool inFile(DataFile f) const { return reg.file == f; }
static inline Value *get(Iterator&);

6
src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp
View file

@ -198,7 +198,7 @@ void CodeEmitterGK110::srcAddr32(const ValueRef& src, const int pos)
void CodeEmitterGK110::defId(const ValueDef& def, const int pos)
{
code[pos / 32] |= (def.get() ? DDATA(def).id : GK110_GPR_ZERO) << (pos % 32);
code[pos / 32] |= (def.get() && def.getFile() != FILE_FLAGS ? DDATA(def).id : GK110_GPR_ZERO) << (pos % 32);
}
bool CodeEmitterGK110::isLIMM(const ValueRef& ref, DataType ty, bool mod)
@ -703,7 +703,7 @@ CodeEmitterGK110::emitUADD(const Instruction *i)
if (addOp & 2)
code[1] |= 1 << 27;
assert(!i->defExists(1));
assert(i->flagsDef < 0);
assert(i->flagsSrc < 0);
SAT_(39);
@ -714,7 +714,7 @@ CodeEmitterGK110::emitUADD(const Instruction *i)
code[1] |= addOp << 19;
if (i->defExists(1))
if (i->flagsDef >= 0)
code[1] |= 1 << 18; // write carry
if (i->flagsSrc >= 0)
code[1] |= 1 << 14; // add carry

3
src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp
View file

@ -252,7 +252,8 @@ CodeEmitterGM107::emitInsn(uint32_t hi, bool pred)
void
CodeEmitterGM107::emitGPR(int pos, const Value *val)
{
emitField(pos, 8, val ? val->reg.data.id : 255);
emitField(pos, 8, val && !val->inFile(FILE_FLAGS) ?
val->reg.data.id : 255);
}
void

14
src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp
View file

@ -195,13 +195,15 @@ CodeEmitterNVC0::srcAddr32(const ValueRef& src, int pos, int shr)
void CodeEmitterNVC0::defId(const ValueDef& def, const int pos)
{
code[pos / 32] |= (def.get() ? DDATA(def).id : 63) << (pos % 32);
code[pos / 32] |= (def.get() && def.getFile() != FILE_FLAGS ? DDATA(def).id : 63) << (pos % 32);
}
void CodeEmitterNVC0::defId(const Instruction *insn, int d, int pos)
void CodeEmitterNVC0::defId(const Instruction *insn, int d, const int pos)
{
int r = insn->defExists(d) ? DDATA(insn->def(d)).id : 63;
code[pos / 32] |= r << (pos % 32);
if (insn->defExists(d))
defId(insn->def(d), pos);
else
code[pos / 32] |= 63 << (pos % 32);
}
bool CodeEmitterNVC0::isLIMM(const ValueRef& ref, DataType ty)
@ -716,11 +718,11 @@ CodeEmitterNVC0::emitUADD(const Instruction *i)
if (i->encSize == 8) {
if (isLIMM(i->src(1), TYPE_U32)) {
emitForm_A(i, HEX64(08000000, 00000002));
if (i->defExists(1))
if (i->flagsDef >= 0)
code[1] |= 1 << 26; // write carry
} else {
emitForm_A(i, HEX64(48000000, 00000003));
if (i->defExists(1))
if (i->flagsDef >= 0)
code[1] |= 1 << 16; // write carry
}
code[0] |= addOp;

2
src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
View file

@ -249,7 +249,7 @@ NVC0LegalizeSSA::handleSET(CmpInstruction *cmp)
bld.mkSplit(src0, 4, cmp->getSrc(0));
bld.mkSplit(src1, 4, cmp->getSrc(1));
bld.mkOp2(OP_SUB, hTy, NULL, src0[0], src1[0])
->setFlagsDef(1, (carry = bld.getSSA(1, FILE_FLAGS)));
->setFlagsDef(0, (carry = bld.getSSA(1, FILE_FLAGS)));
cmp->setFlagsSrc(cmp->srcCount(), carry);
cmp->setSrc(0, src0[1]);
cmp->setSrc(1, src1[1]);