We now require C11, and C++ supports static_assert just fine, which is
the only thing this header ever added support for. So let's get rid of
this needless header.
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16812>
For the sake of consistency, do not rely on a 1-dimensional
workgroup ID anymore.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16721>
Unfortunately, radv_lower_multiview is not suitable for mesh shaders
because it can't know the mapping between API mesh shader
invocations and output primitives.
Additionally, when lowering view id to layer, it must be created
as a per-primitive PS input.
Fixes: d32656bc65
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16504>
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Acked-by: Martin Roukala <martin.roukala@mupuf.org>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16702>
Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Acked-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Martin Roukala <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16604>
We can't use UINT16_ABGR for the alpha channel. Always use 32_ABGR.
Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16509>
Fixes: 3e85a0c90b ("ac/surface: define gfx11 modifiers")
../../src/amd/common/ac_surface.c: In function 'ac_get_supported_modifiers':
../../src/amd/common/ac_surface.c:421:47: error: 'AMD_FMT_MOD_TILE_GFX11_256K_R_X' undeclared (first use in this function); did you mean 'AMD_FMT_MOD_TILE_GFX9_64K_R_X'?
421 | unsigned swizzle_r_x = num_pipes > 16 ? AMD_FMT_MOD_TILE_GFX11_256K_R_X :
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
| AMD_FMT_MOD_TILE_GFX9_64K_R_X
../../src/amd/common/ac_surface.c:421:47: note: each undeclared identifier is reported only once for each function it appears in
In file included from ../../src/amd/common/ac_surface.c:31:
../../src/amd/common/ac_surface.c:424:61: error: 'AMD_FMT_MOD_TILE_VER_GFX11' undeclared (first use in this function); did you mean 'AMD_FMT_MOD_TILE_VER_GFX10'?
424 | AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX11) |
| ^~~~~~~~~~~~~~~~~~~~~~~~~~
../../src/amd/common/ac_drm_fourcc.h:75:21: note: in definition of macro 'AMD_FMT_MOD_SET'
75 | ((uint64_t)(value) << AMD_FMT_MOD_##field##_SHIFT)
| ^~~~~
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16373>
Fixes: b261ac1ab5 ("ac/gpu_info: print all IP versions reported by the kernel")
```
../../src/amd/common/ac_gpu_info.c
../../src/amd/common/ac_gpu_info.c: In function 'ac_query_gpu_info':
../../src/amd/common/ac_gpu_info.c:545:44: error: 'struct drm_amdgpu_info_hw_ip' has no member named 'hw_ip_version_major'
545 | info->ip[ip_type].ver_major = ip_info.hw_ip_version_major;
| ^
../../src/amd/common/ac_gpu_info.c:546:44: error: 'struct drm_amdgpu_info_hw_ip' has no member named 'hw_ip_version_minor'
546 | info->ip[ip_type].ver_minor = ip_info.hw_ip_version_minor;
| ^
```
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16373>
This is going to be used by both task and mesh shaders for
accessing the draw and payload ring buffers.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14929>
Task shaders store their output payload to VRAM where mesh
shaders read from. There are two ring buffers:
1. Draw ring: this is where mesh dispatch sizes and
the ready bit are stored.
2. Payload ring: this is where the optional payload
is stored (up to 16K per task workgroup).
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14929>
This was updated in
4e49a05e37 ("radeonsi: increase the tesselation factor ring size")
and
9fecac091f ("radeonsi/gfx11: scattered register deltas")
This will apply this to radv.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16415>
It's incorrect for GFX. This is what I get on Radeon 6800:
IP GFX 10.0 queues:1
IP COMP 10.0 queues:4
IP SDMA 5.2 queues:2
IP VCN_DEC 3.0 queues:1
IP VCN_ENC 3.0 queues:1
IP VCN_JPG 3.0 queues:1
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16360>
In gfx11, instruction cache line size is 128 bytes. This patch makes
the neccessary code changes.
v2: instruction store line size is 64 bytes (Marek Olšák)
Signed-off-by: Yogesh mohan marimuthu <yogesh.mohanmarimuthu@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
