fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-05-06 11:38:05 +02:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

radeonsi/gfx11: add assert in legacy vs path

Browse source 
Only ngg should be used.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
This commit is contained in:
Pierre-Eric Pelloux-Prayer 2021-07-27 13:40:28 +02:00 • committed by Marge Bot
parent 1005a2a25f
commit 3bdb3db5fa
4 changed files with 10 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
src/amd/common/ac_shader_util.c
View file

@ -89,6 +89,8 @@ uint32_t ac_vgt_gs_mode(unsigned gs_max_vert_out, enum chip_class chip_class)
{
unsigned cut_mode;
assert (chip_class < GFX11);
if (gs_max_vert_out <= 128) {
cut_mode = V_028A40_GS_CUT_128;
} else if (gs_max_vert_out <= 256) {

3
src/gallium/drivers/radeonsi/si_shader_llvm_gs.c
View file

@ -356,6 +356,9 @@ void si_preload_esgs_ring(struct si_shader_context *ctx)
void si_preload_gs_rings(struct si_shader_context *ctx)
{
if (ctx->ac.chip_class >= GFX11)
return;
const struct si_shader_selector *sel = ctx->shader->selector;
LLVMBuilderRef builder = ctx->ac.builder;
LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, SI_RING_GSVS, 0);

1
src/gallium/drivers/radeonsi/si_state_draw.cpp
View file

@ -1245,6 +1245,7 @@ static void gfx10_emit_ge_cntl(struct si_context *sctx, unsigned num_patches)
} else {
unsigned primgroup_size;
unsigned vertgroup_size;
assert(GFX_VERSION < GFX11);
if (HAS_TESS) {
primgroup_size = num_patches; /* must be a multiple of NUM_PATCHES */

4
src/gallium/drivers/radeonsi/si_state_shaders.cpp
View file

@ -1619,6 +1619,8 @@ static void si_shader_vs(struct si_screen *sscreen, struct si_shader *shader,
info->base.vs.window_space_position : 0;
bool enable_prim_id = shader->key.ge.mono.u.vs_export_prim_id || info->uses_primid;
assert(sscreen->info.chip_class < GFX11);
pm4 = si_get_shader_pm4_state(shader);
if (!pm4)
return;
@ -3676,6 +3678,8 @@ static void si_emit_vgt_flush(struct radeon_cmdbuf *cs)
/* Initialize state related to ESGS / GSVS ring buffers */
bool si_update_gs_ring_buffers(struct si_context *sctx)
{
assert(sctx->chip_class < GFX11);
struct si_shader_selector *es =
sctx->shader.tes.cso ? sctx->shader.tes.cso : sctx->shader.vs.cso;
struct si_shader_selector *gs = sctx->shader.gs.cso;