radeonsi/vcn: Add support of array_mode for gfx11

Update array_mode for gfx11 in vcn decoder.

Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Reviewed-by: James Zhu <James.Zhu@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16328>
This commit is contained in:
Ruijing Dong 2022-03-10 12:13:09 -05:00 committed by Marge Bot
parent 88075b7ea1
commit 62bb11a5a5
3 changed files with 11 additions and 1 deletions

View file

@ -114,6 +114,11 @@
#define RDECODE_ARRAY_MODE_MACRO_TILED_MICRO_LINEAR 0x00000004
#define RDECODE_ARRAY_MODE_MACRO_TILED_MICRO_TILED 0x00000005
#define RDECODE_ARRAY_MODE_ADDRLIB_SEL_GFX10 0x00000000
#define RDECODE_ARRAY_MODE_ADDRLIB_SEL_GFX9 0x00000001
#define RDECODE_ARRAY_MODE_ADDRLIB_SEL_GFX8 0x00000002
#define RDECODE_ARRAY_MODE_ADDRLIB_SEL_GFX11 0x00000003
#define RDECODE_H264_PROFILE_BASELINE 0x00000000
#define RDECODE_H264_PROFILE_MAIN 0x00000001
#define RDECODE_H264_PROFILE_HIGH 0x00000002

View file

@ -1788,6 +1788,7 @@ static struct pb_buffer *rvcn_dec_message_decode(struct radeon_decoder *dec,
decode->db_aligned_height = align(dec->base.height, 64);
decode->db_surf_tile_config = 0;
decode->db_array_mode = dec->addr_gfx_mode;
decode->dt_pitch = luma->surface.u.gfx9.surf_pitch * luma->surface.blk_w;
decode->dt_uv_pitch = chroma->surface.u.gfx9.surf_pitch * chroma->surface.blk_w;
@ -1799,7 +1800,7 @@ static struct pb_buffer *rvcn_dec_message_decode(struct radeon_decoder *dec,
decode->dt_tiling_mode = 0;
decode->dt_swizzle_mode = luma->surface.u.gfx9.swizzle_mode;
decode->dt_array_mode = RDECODE_ARRAY_MODE_LINEAR;
decode->dt_array_mode = dec->addr_gfx_mode;
decode->dt_field_mode = ((struct vl_video_buffer *)target)->base.interlaced;
decode->dt_surf_tile_config = 0;
decode->dt_uv_surf_tile_config = 0;
@ -2730,6 +2731,8 @@ struct pipe_video_codec *radeon_create_decoder(struct pipe_context *context,
}
si_vid_clear_buffer(context, &dec->sessionctx);
dec->addr_gfx_mode = RDECODE_ARRAY_MODE_LINEAR;
switch (sctx->family) {
case CHIP_RAVEN:
case CHIP_RAVEN2:
@ -2767,6 +2770,7 @@ struct pipe_video_codec *radeon_create_decoder(struct pipe_context *context,
case CHIP_GFX1100:
case CHIP_GFX1102:
dec->jpg.direct_reg = true;
dec->addr_gfx_mode = RDECODE_ARRAY_MODE_ADDRLIB_SEL_GFX11;
break;
default:
RVID_ERR("VCN is not supported.\n");

View file

@ -51,6 +51,7 @@ struct radeon_decoder {
unsigned dpb_size;
unsigned last_width;
unsigned last_height;
unsigned addr_gfx_mode;
struct pipe_screen *screen;
struct radeon_winsys *ws;