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ac: add ac_nir_optimize_outputs, a NIR version of ac_optimize_vs_outputs
ac_optimize_vs_outputs is an LLVM IR pass, and it will be replaced by this. Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14414>
This commit is contained in:
Marek Olšák
Marge Bot
parent
4e8b8555c6
commit
11c28d9798
4 changed files with 333 additions and 1 deletions
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@ -52,6 +52,10 @@ enum
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struct nir_builder;
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typedef struct nir_builder nir_builder;
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bool ac_nir_optimize_outputs(nir_shader *nir, bool sprite_tex_disallowed,
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int8_t slot_remap[NUM_TOTAL_VARYING_SLOTS],
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uint8_t param_export_index[NUM_TOTAL_VARYING_SLOTS]);
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void
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ac_nir_lower_ls_outputs_to_mem(nir_shader *ls,
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bool tcs_in_out_eq,
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328
src/amd/common/ac_nir_opt_outputs.c
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328
src/amd/common/ac_nir_opt_outputs.c
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@ -0,0 +1,328 @@
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/*
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* Copyright © 2021 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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/* This helps separate shaders because the next shader doesn't have to be known.
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*
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* It optimizes VS and TES outputs before FS as follows:
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* - Eliminate and merge equal outputs, and treat undef as equal to everything, e.g.
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* (x,y,undef,undef) == (undef,y,z,undef) --> (x,y,z,undef) regardless of the interpolation
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* qualifier (AMD can map 1 output to multiple PS inputs and interpolate each differently).
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* - Remove constant outputs that match AMD DEFAULT_VAL options, e.g. (0,0,0,1),
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* treat undef as whatever.
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*
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* It requires that there is no indirect indexing and all output stores must be scalar.
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*/
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#include "ac_nir.h"
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#include "nir_builder.h"
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struct ac_chan_info {
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nir_instr *value;
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nir_intrinsic_instr *store_intr; /* The intrinsic writing the value. */
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};
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struct ac_out_info {
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unsigned base; /* nir_intrinsic_base */
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nir_alu_type types;
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bool duplicated;
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bool constant;
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/* Channels 0-3 are 32-bit channels or low bits of 16-bit channels.
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* Channels 4-7 are high bits of 16-bit channels.
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*/
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struct ac_chan_info chan[8];
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};
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static void ac_remove_varying(struct ac_out_info *out)
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{
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/* Remove the output. (all channels) */
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for (unsigned i = 0; i < ARRAY_SIZE(out->chan); i++) {
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if (out->chan[i].store_intr) {
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nir_remove_varying(out->chan[i].store_intr);
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out->chan[i].store_intr = NULL;
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out->chan[i].value = NULL;
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}
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}
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}
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/* Return true if the output matches DEFAULT_VAL and has been eliminated. */
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static bool ac_eliminate_const_output(struct ac_out_info *out,
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gl_varying_slot semantic,
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uint8_t *param_export_index)
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{
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if (!(out->types & 32))
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return false;
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bool is_zero[4] = {0}, is_one[4] = {0};
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for (unsigned i = 0; i < 4; i++) {
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/* NULL means undef. */
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if (!out->chan[i].value) {
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is_zero[i] = true;
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is_one[i] = true;
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} else if (out->chan[i].value->type == nir_instr_type_load_const) {
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if (nir_instr_as_load_const(out->chan[i].value)->value[0].f32 == 0)
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is_zero[i] = true;
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else if (nir_instr_as_load_const(out->chan[i].value)->value[0].f32 == 1)
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is_one[i] = true;
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else
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return false; /* other constant */
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} else
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return false;
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}
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/* Only certain combinations of 0 and 1 are supported. */
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unsigned default_val; /* SPI_PS_INPUT_CNTL_i.DEFAULT_VAL */
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if (is_zero[0] && is_zero[1] && is_zero[2]) {
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if (is_zero[3])
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default_val = AC_EXP_PARAM_DEFAULT_VAL_0000;
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else if (is_one[3])
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default_val = AC_EXP_PARAM_DEFAULT_VAL_0001;
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else
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return false;
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} else if (is_one[0] && is_one[1] && is_one[2]) {
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if (is_zero[3])
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default_val = AC_EXP_PARAM_DEFAULT_VAL_1110;
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else if (is_one[3])
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default_val = AC_EXP_PARAM_DEFAULT_VAL_1111;
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else
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return false;
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} else {
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return false;
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}
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/* Change OFFSET to DEFAULT_VAL. */
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param_export_index[semantic] = default_val;
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out->constant = true;
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ac_remove_varying(out);
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return true;
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}
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static bool ac_eliminate_duplicated_output(struct ac_out_info *outputs,
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BITSET_DECLARE(outputs_optimized, NUM_TOTAL_VARYING_SLOTS),
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gl_varying_slot current, struct nir_builder *b,
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int8_t slot_remap[NUM_TOTAL_VARYING_SLOTS])
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{
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struct ac_out_info *cur = &outputs[current];
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unsigned p, copy_back_channels = 0;
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/* Check all outputs before current. */
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BITSET_FOREACH_SET(p, outputs_optimized, current) {
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struct ac_out_info *prev = &outputs[p];
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/* Only compare with real outputs. */
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if (prev->constant || prev->duplicated)
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continue;
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/* The types must match (only 16-bit and 32-bit types are allowed). */
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if ((prev->types & 16) != (cur->types & 16))
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continue;
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bool different = false;
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/* Iterate over all channels, including 16-bit channels in chan_hi. */
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for (unsigned j = 0; j < 8; j++) {
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nir_instr *prev_chan = prev->chan[j].value;
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nir_instr *cur_chan = cur->chan[j].value;
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/* Treat undef as a match. */
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if (!cur_chan)
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continue;
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/* If prev is undef but cur isn't, we can merge the outputs
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* and consider the output duplicated.
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*/
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if (!prev_chan) {
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copy_back_channels |= 1 << j;
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continue;
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}
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/* Test whether the values are different. */
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if (prev_chan != cur_chan &&
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(prev_chan->type != nir_instr_type_load_const ||
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cur_chan->type != nir_instr_type_load_const ||
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nir_instr_as_load_const(prev_chan)->value[0].u32 !=
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nir_instr_as_load_const(cur_chan)->value[0].u32)) {
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different = true;
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break;
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}
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}
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if (!different)
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break;
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copy_back_channels = 0;
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}
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if (p == current)
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return false;
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/* An equal output already exists. Make FS use the existing one instead.
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* This effectively disables the current output and the param export shouldn't
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* be generated.
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*/
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cur->duplicated = true;
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/* p is gl_varying_slot in addition to being an index into outputs. */
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slot_remap[current] = p;
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/* If the matching preceding output has undef where the current one has a proper value,
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* move the value to the preceding output.
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*/
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struct ac_out_info *prev = &outputs[p];
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while (copy_back_channels) {
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unsigned i = u_bit_scan(©_back_channels);
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struct ac_chan_info *prev_chan = &prev->chan[i];
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struct ac_chan_info *cur_chan = &cur->chan[i];
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b->cursor = nir_after_instr(&cur_chan->store_intr->instr);
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/* The store intrinsic doesn't exist for this channel. Create a new one. */
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nir_alu_type src_type = nir_intrinsic_src_type(cur_chan->store_intr);
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struct nir_io_semantics sem = nir_intrinsic_io_semantics(cur_chan->store_intr);
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struct nir_io_xfb xfb = nir_intrinsic_io_xfb(cur_chan->store_intr);
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struct nir_io_xfb xfb2 = nir_intrinsic_io_xfb2(cur_chan->store_intr);
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/* p is gl_varying_slot in addition to being an index into outputs. */
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sem.location = p;
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assert(sem.high_16bits == i / 4);
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/* If it's a sysval output (such as CLIPDIST), we move the varying portion but keep
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* the system value output. This is just the varying portion.
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*/
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sem.no_sysval_output = 1;
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/* Write just one component. */
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prev_chan->store_intr = nir_store_output(b, nir_instr_ssa_def(cur_chan->value),
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nir_imm_int(b, 0),
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.base = prev->base,
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.component = i % 4,
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.io_semantics = sem,
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.src_type = src_type,
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.write_mask = 0x1,
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.io_xfb = xfb,
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.io_xfb2 = xfb2);
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/* Update the undef channels in the output info. */
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assert(!prev_chan->value);
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prev_chan->value = cur_chan->value;
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/* Remove transform feedback info from the current instruction because
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* we moved it too. The instruction might not be removed if it's a system
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* value output.
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*/
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static struct nir_io_xfb zero_xfb;
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nir_intrinsic_set_io_xfb(cur->chan[i].store_intr, zero_xfb);
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nir_intrinsic_set_io_xfb2(cur->chan[i].store_intr, zero_xfb);
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}
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ac_remove_varying(cur);
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return true;
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}
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bool ac_nir_optimize_outputs(nir_shader *nir, bool sprite_tex_disallowed,
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int8_t slot_remap[NUM_TOTAL_VARYING_SLOTS],
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uint8_t param_export_index[NUM_TOTAL_VARYING_SLOTS])
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{
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nir_function_impl *impl = nir_shader_get_entrypoint(nir);
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assert(impl);
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if (nir->info.stage != MESA_SHADER_VERTEX &&
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nir->info.stage != MESA_SHADER_TESS_EVAL) {
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nir_metadata_preserve(impl, nir_metadata_all);
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return false;
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}
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struct ac_out_info outputs[NUM_TOTAL_VARYING_SLOTS] = {};
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BITSET_DECLARE(outputs_optimized, NUM_TOTAL_VARYING_SLOTS);
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BITSET_ZERO(outputs_optimized);
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/* Gather outputs. */
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nir_foreach_block(block, impl) {
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nir_foreach_instr_safe(instr, block) {
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if (instr->type != nir_instr_type_intrinsic)
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continue;
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nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
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if (intr->intrinsic != nir_intrinsic_store_output)
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continue;
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nir_io_semantics sem = nir_intrinsic_io_semantics(intr);
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/* Only process varyings that appear as param exports. */
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if (!nir_slot_is_varying(sem.location) || sem.no_varying)
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continue;
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/* We can't optimize texture coordinates if sprite_coord_enable can override them. */
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if (sem.location >= VARYING_SLOT_TEX0 && sem.location <= VARYING_SLOT_TEX7 &&
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!sprite_tex_disallowed)
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continue;
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BITSET_SET(outputs_optimized, sem.location);
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/* No indirect indexing allowed. */
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ASSERTED nir_src offset = *nir_get_io_offset_src(intr);
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assert(nir_src_is_const(offset) && nir_src_as_uint(offset) == 0);
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/* nir_lower_io_to_scalar is required before this */
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assert(intr->src[0].ssa->num_components == 1);
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/* No intrinsic should store undef. */
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assert(intr->src[0].ssa->parent_instr->type != nir_instr_type_ssa_undef);
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/* Gather the output. */
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struct ac_out_info *out_info = &outputs[sem.location];
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if (!out_info->types)
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out_info->base = nir_intrinsic_base(intr);
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else
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assert(out_info->base == nir_intrinsic_base(intr));
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out_info->types |= nir_intrinsic_src_type(intr);
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unsigned chan = sem.high_16bits * 4 + nir_intrinsic_component(intr);
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out_info->chan[chan].store_intr = intr;
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out_info->chan[chan].value = intr->src[0].ssa->parent_instr;
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}
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}
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unsigned i;
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bool progress = false;
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struct nir_builder b;
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nir_builder_init(&b, impl);
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/* Optimize outputs. */
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BITSET_FOREACH_SET(i, outputs_optimized, NUM_TOTAL_VARYING_SLOTS) {
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progress |=
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ac_eliminate_const_output(&outputs[i], i, param_export_index) ||
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ac_eliminate_duplicated_output(outputs, outputs_optimized, i, &b, slot_remap);
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}
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if (progress) {
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nir_metadata_preserve(impl, nir_metadata_dominance |
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nir_metadata_block_index);
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} else {
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nir_metadata_preserve(impl, nir_metadata_all);
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}
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return progress;
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}
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@ -90,6 +90,7 @@ amd_common_files = files(
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'ac_rgp_elf_object_pack.c',
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'ac_nir.c',
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'ac_nir.h',
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'ac_nir_opt_outputs.c',
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'ac_nir_cull.c',
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'ac_nir_lower_esgs_io_to_mem.c',
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'ac_nir_lower_global_access.c',
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@ -1502,7 +1502,6 @@ struct nir_shader *si_get_nir_shader(struct si_shader_selector *sel,
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* - Eliminated PS system values are disabled by LLVM
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* (FragCoord, FrontFace, barycentrics)
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* - VS/TES/GS outputs feeding PS are eliminated if outputs are undef.
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* (thanks to an LLVM pass in Mesa - TODO: move it to NIR)
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* The storage for eliminated outputs is also not allocated.
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* - VS/TCS/TES/GS/PS input loads are eliminated (VS relies on DCE in LLVM)
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* - TCS output stores are eliminated
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