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165 commits

Author SHA1 Message Date
Timothy Arceri
6b60cfd079 radeonsi: update function name in comment 
This was missed in 2361558eb7

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2019-07-09 10:00:23 +10:00
Marek Olšák
07aacdbfd5 radeonsi/gfx10: add a workaround for stencil HTILE with mipmapping 
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2019-07-03 15:51:13 -04:00
Marek Olšák
51db950419 radeonsi/gfx10: disable DCC with MSAA 
It was only enabled for 2x MSAA anyway.

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2019-07-03 15:51:13 -04:00
Marek Olšák
6eb219e963 radeonsi/gfx10: fix intensity formats 
move the ALPHA_IS_ON_MSB fixup into vi_alpha_is_on_msb

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2019-07-03 15:51:13 -04:00
Nicolai Hähnle
1666ee183e radeonsi/gfx10: implement hardware MSAA resolve 
MSAA is only supported for 64KB_{R,Z}_X modes, so the micro tile
optimization that we use on gfx9 and earlier does not work.

Be very explicit about how the swizzle mode of the temporary surface is
selected.

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2019-07-03 15:51:13 -04:00
Nicolai Hähnle
595a7f7c47 radeonsi/gfx10: add pipe_screen::make_texture_descriptor 
Texture descriptors in gfx10 are very different.

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2019-07-03 15:51:12 -04:00
Marek Olšák
c53e6ea05d radeonsi: use a fragment shader blit instead of DB->CB copy for ZS CPU mappings 
This mainly removes and simplifies code that is no longer needed.

There were some issues with the DB->CB stencil copy on gfx10, so let's
just use a fragment shader blit for all ZS mappings. It's more reliable.

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
 2019-07-03 15:51:12 -04:00
Michel Dänzer
11a3679e3a winsys/amdgpu: Make KMS handles valid for original DRM file descriptor 
Getting a DMA-buf fd and converting that to a handle using our duplicate
of that file descriptor (getting at which requires passing a
radeon_winsys pointer to the buffer_get_handle hook) makes sure of this,
since duplicated file descriptors reference the same file description
and therefore the same GEM handle namespace.

This is necessary because libdrm_amdgpu may use a different DRM file
descriptor with a separate handle namespace internally, e.g. because it
always reuses any existing amdgpu_device_handle for the same device.
amdgpu_bo_export returns a handle which is valid for that internal
file descriptor.

Bugzilla: https://bugs.freedesktop.org/110903
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
 2019-07-03 09:19:07 +00:00
Marek Olšák
aa8d6e0507 radeonsi: fix AMD_DEBUG=nofmask 
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2019-06-24 21:04:10 -04:00
Marek Olšák
eba932ea43 amd: update addrlib 
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2019-06-17 15:14:55 -04:00
Nicolai Hähnle
dc99a8cd9b radeonsi: cleanup some #includes 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
 2019-06-12 20:28:23 -04:00
Nicolai Hähnle
f480b8aaa4 amd/common: use generated register header 2019-06-03 20:05:20 -04:00
Marek Olšák
ccfcb9d818 ac: rename SI-CIK-VI to GFX6-GFX7-GFX8 
Acked-by: Dave Airlie <airlied@redhat.com>

We already use GFX9 and I don't want us to have confusing naming
in the driver. GFXn naming is better from the driver perspective,
because it's the real version of the gfx portion of the hw. Also,
CIK means Bonaire-Kaveri-Kabini, it doesn't mean CI.

It shouldn't confuse our SDMA, UVD, VCE etc. code much. Those have
nothing to do with GFXn and they have their own version numbers.
 2019-05-15 20:54:10 -04:00
Julien Isorce
1cec049d4d radeonsi: implement resource_get_info 
Re-use existing si_texture_get_offset.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110443
Signed-off-by: Julien Isorce <jisorce@oblong.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
 2019-04-30 17:53:12 +00:00
Marek Olšák
1f21396431 radeonsi: add support for displayable DCC for multi-RB chips 
A compute shader is used to reorder DCC data from aligned to unaligned.
 2019-04-04 09:53:24 -04:00
Marek Olšák
2c09eb4122 radeonsi: add support for displayable DCC for 1 RB chips 
This is the simpler codepath - just disable RB and pipe alignment for DCC.
 2019-04-04 09:53:24 -04:00
Marek Olšák
a1378639ab radeonsi: always use compute rings for clover on CI and newer (v2) 
initialize all non-compute context functions to NULL.

v2: fix SI
 2019-02-26 14:58:55 -05:00
Marek Olšák
7d4c935654 radeonsi: initialize textures using DCC to black when possible 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2019-02-06 11:17:21 -05:00
Marek Olšák
16672f16da radeonsi: unify error paths in si_texture_create_object 2019-01-30 12:35:22 -05:00
Marek Olšák
2361558eb7 radeonsi: merge & rename texture BO metadata functions 2019-01-30 12:35:22 -05:00
Marek Olšák
501ff90a95 radeonsi: rename r600_resource -> si_resource 
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2019-01-22 13:32:18 -05:00
Marek Olšák
96610f625d radeonsi: rename rscreen -> sscreen 
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2019-01-22 12:25:57 -05:00
Marek Olšák
3ae57957be radeonsi: always unmap texture CPU mappings on 32-bit CPU architectures 
Team Fortress 2 32-bit version runs out of the CPU address space.

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
 2019-01-02 15:01:59 -05:00
Nicolai Hähnle
e0f0d3675d radeonsi: factor si_query_buffer logic out of si_query_hw 
This is a move towards using composition instead of inheritance for
different query types.

This change weakens out-of-memory error reporting somewhat, though this
should be acceptable since we didn't consistently report such errors in
the first place.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
 2018-12-19 12:02:01 +01:00
Nicolai Hähnle
5c841a1b1e radeonsi: rename SI_RESOURCE_FLAG_FORCE_TILING to clarify its purpose 
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
 2018-12-19 12:01:39 +01:00
Marek Olšák
6b554d863f winsys/amdgpu,radeon: pass vm_alignment to buffer_from_handle 
Acked-by: Christian König <christian.koenig@amd.com>
 2018-11-28 20:20:27 -05:00
Marek Olšák
8ad12c8bec gallium: rework PIPE_HANDLE_USAGE_* flags 
Only radeonsi uses them, so adjust them to match its needs.
 2018-10-30 16:03:02 -04:00
Marek Olšák
a1b9a00f82 radeonsi: fix HTILE for NPOT textures with mipmapping on SI/CI 
VI uses addrlib so it's unaffected.

Cc: 18.1 18.2 <mesa-stable@lists.freedesktop.org>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
 2018-09-10 15:19:56 -04:00
Marek Olšák
20dd75a926 radeonsi: use storage_samples instead of color_samples in most places 
and use pipe_resource::nr_storage_samples instead of
r600_texture::num_color_samples.

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
 2018-07-31 18:28:41 -04:00
Marek Olšák
f8b0c54e3f radeonsi: simplify logic around vi_separate_dcc_try_enable 2018-06-28 22:27:25 -04:00
Marek Olšák
fb28bf23db radeonsi: remove references to Evergreen 2018-06-28 22:27:25 -04:00
Marek Olšák
bd963f8430 radeonsi: rename r600_transfer -> si_transfer 
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
 2018-06-25 18:33:58 -04:00
Marek Olšák
eabeeb86b2 radeonsi: properly set cmask_buffer in si_reallocate_texture_inplace 
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
 2018-06-25 18:33:58 -04:00
Marek Olšák
d4755ef389 radeonsi: remove redundant si_texture::cmask_size 
cmask_buffer and surface.cmask_size can replace its role.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
 2018-06-25 18:33:58 -04:00
Marek Olšák
2a8d1039b6 radeonsi: inline struct r600_cmask_info 
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
 2018-06-25 18:33:58 -04:00
Marek Olšák
166250f4e5 radeonsi: move CMASK size computation into ac_surface 
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
 2018-06-25 18:33:58 -04:00
Marek Olšák
3da693b7d9 ac/surface: move cmask_size/alignment into radeon_surf 
cmask_size is changed to uint32_t because it can't be greater than 4GB.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
 2018-06-25 18:33:58 -04:00
Marek Olšák
2d64a68c6f radeonsi: rename r600_surface -> si_surface 
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
 2018-06-25 18:33:58 -04:00
Marek Olšák
218e133695 radeonsi: rename r600_memory_object -> si_memory_object 
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
 2018-06-25 18:33:58 -04:00
Marek Olšák
e5df04f13d radeonsi: remove unused r600_memory_object::offset 
The real offset is passed through resource_from_memobj.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
 2018-06-25 18:33:58 -04:00
Marek Olšák
45004abfd5 radeonsi: unify duplicated texture_from_handle & texture_from_memobj 
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
 2018-06-25 18:33:58 -04:00
Marek Olšák
cac7ab1192 radeonsi: reorder and initialize more fields in si_reallocate_texture_inplace 
Some fields shouldn't be initialized, like framebuffers_bound and other stats.
It's hopefully complete now.

Cc: 18.1 <mesa-stable@lists.freedesktop.org>
 2018-06-25 18:33:58 -04:00
Marek Olšák
587e712eda radeonsi: disable DCC MSAA for 128bpp formats on Stoney 
Cc: 18.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2018-06-21 14:42:14 -04:00
Marek Olšák
1ba87f4438 radeonsi: rename r600_texture -> si_texture, rxxx -> xxx or sxxx 
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
 2018-06-19 13:08:50 -04:00
Dave Airlie
b7ac0779e0 gallium/winsys: rename DRM_API_HANDLE_* to WINSYS_HANDLE_* 
This just renames this as we want to add an shm handle which
isn't really drm related.

Originally by: Marc-André Lureau <marcandre.lureau@gmail.com>
(airlied: I used this sed script instead)
This was generated with:
 git grep -l 'DRM_API_' | xargs sed -i 's/DRM_API_/WINSYS_/g'

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
 2018-05-30 09:11:53 +10:00
Marek Olšák
3060f62340 ac/gpu_info: add has_bo_metadata 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2018-05-10 18:39:56 -04:00
Marek Olšák
8b58a14ef7 ac/gpu_info: add htile_cmask_support_1d_tiling 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2018-05-10 18:39:53 -04:00
Marek Olšák
a969f184cf radeonsi: add an environment variable that forces EQAA for MSAA allocations 
This is for testing and experiments.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2018-05-10 18:34:37 -04:00
Marek Olšák
9d00580e75 radeonsi: support creating EQAA color textures 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2018-05-10 18:34:32 -04:00
Marek Olšák
912b0163dc ac/surface: add EQAA support 
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
 2018-05-10 18:34:31 -04:00