Marek Olšák
|
835095973d
|
radeonsi: remove r600_fmask_info
radeon_surf contains almost everything.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
|
2018-05-10 18:26:33 -04:00 |
|
Marek Olšák
|
bdc3e410f7
|
ac/surface: unify common legacy and gfx9 fmask fields
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
|
2018-05-10 18:26:33 -04:00 |
|
Marek Olšák
|
9bf3570fed
|
ac/surface/gfx6: compute FMASK together with the color surface
instead of invoking FMASK computation separately.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
|
2018-05-10 18:26:33 -04:00 |
|
Marek Olšák
|
788d66553a
|
radeonsi: rename r600_texture::resource to buffer
r600_resource could be renamed to si_buffer.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
|
2018-04-27 17:56:04 -04:00 |
|
Marek Olšák
|
6fadfc01c6
|
radeonsi: use r600_resource() typecast helper
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
|
2018-04-27 17:56:04 -04:00 |
|
Marek Olšák
|
a8abbbb172
|
radeonsi: remove r600_pipe_common.h
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
|
2018-04-27 17:56:04 -04:00 |
|
Marek Olšák
|
2d69b485f5
|
radeonsi: rewrite DCC format compatibility checking code
It might be better to use a slow compressed clear when clearing to 1.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
|
2018-04-27 17:56:04 -04:00 |
|
Marek Olšák
|
1cc2e0cc6b
|
radeonsi: fully enable 2x DCC MSAA for array and non-array textures
The clear code is exactly the same as for 1 sample buffers -
just clear the whole thing.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
|
2018-04-27 17:56:04 -04:00 |
|
Nicolai Hähnle
|
e788b987d8
|
radeonsi: fix error paths of si_texture_transfer_map
trans is zero-initialized, but trans->resource is setup immediately so
needs to be dereferenced.
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
|
2018-04-20 09:21:33 +02:00 |
|
Marek Olšák
|
60299e9abe
|
radeonsi: don't emit partial flushes for internal CS flushes only
Tested-by: Benedikt Schemmer <ben@besd.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
|
2018-04-16 16:58:10 -04:00 |
|
Marek Olšák
|
1372ccfe6f
|
radeonsi: disable TC-compat HTILE on Tonga and Iceland
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
|
2018-04-13 12:31:04 -04:00 |
|
Marek Olšák
|
afe0bd2c55
|
radeonsi: force 2D tiling on VI only when TC-compat HTILE is really enabled
just pass the flag that indicates it.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
|
2018-04-13 12:31:04 -04:00 |
|
Marek Olšák
|
be4250aa88
|
radeonsi: remove more R600 references
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
|
2018-04-05 15:34:58 -04:00 |
|
Marek Olšák
|
6a93441295
|
radeonsi: remove r600_common_context
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
|
2018-04-05 15:34:58 -04:00 |
|
Marek Olšák
|
321bd6c280
|
radeonsi: move r600_buffer_common.c and r600_texture.c into radeonsi
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
|
2018-04-05 15:34:58 -04:00 |
|