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radeonsi: rename r600_texture -> si_texture, rxxx -> xxx or sxxx

Browse source 
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
This commit is contained in:
Marek Olšák 2018-06-18 21:34:57 -04:00
parent 6703fec58c
commit 1ba87f4438
16 changed files with 884 additions and 890 deletions
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8
src/gallium/drivers/radeon/radeon_vcn_dec.c
View file

@ -808,10 +808,10 @@ static struct pb_buffer *rvcn_dec_message_decode(struct radeon_decoder *dec,
struct pipe_video_buffer *target,
struct pipe_picture_desc *picture)
{
struct r600_texture *luma = (struct r600_texture *)
((struct vl_video_buffer *)target)->resources[0];
struct r600_texture *chroma = (struct r600_texture *)
((struct vl_video_buffer *)target)->resources[1];
struct si_texture *luma = (struct si_texture *)
((struct vl_video_buffer *)target)->resources[0];
struct si_texture *chroma = (struct si_texture *)
((struct vl_video_buffer *)target)->resources[1];
rvcn_dec_message_header_t *header;
rvcn_dec_message_index_t *index;
rvcn_dec_message_decode_t *decode;

130
src/gallium/drivers/radeonsi/cik_sdma.c
View file

@ -114,7 +114,7 @@ static unsigned minify_as_blocks(unsigned width, unsigned level, unsigned blk_w)
}
static unsigned encode_tile_info(struct si_context *sctx,
struct r600_texture *tex, unsigned level,
struct si_texture *tex, unsigned level,
bool set_bpp)
{
struct radeon_info *info = &sctx->screen->info;
@ -144,59 +144,59 @@ static bool cik_sdma_copy_texture(struct si_context *sctx,
const struct pipe_box *src_box)
{
struct radeon_info *info = &sctx->screen->info;
struct r600_texture *rsrc = (struct r600_texture*)src;
struct r600_texture *rdst = (struct r600_texture*)dst;
unsigned bpp = rdst->surface.bpe;
uint64_t dst_address = rdst->buffer.gpu_address +
rdst->surface.u.legacy.level[dst_level].offset;
uint64_t src_address = rsrc->buffer.gpu_address +
rsrc->surface.u.legacy.level[src_level].offset;
unsigned dst_mode = rdst->surface.u.legacy.level[dst_level].mode;
unsigned src_mode = rsrc->surface.u.legacy.level[src_level].mode;
unsigned dst_tile_index = rdst->surface.u.legacy.tiling_index[dst_level];
unsigned src_tile_index = rsrc->surface.u.legacy.tiling_index[src_level];
struct si_texture *ssrc = (struct si_texture*)src;
struct si_texture *sdst = (struct si_texture*)dst;
unsigned bpp = sdst->surface.bpe;
uint64_t dst_address = sdst->buffer.gpu_address +
sdst->surface.u.legacy.level[dst_level].offset;
uint64_t src_address = ssrc->buffer.gpu_address +
ssrc->surface.u.legacy.level[src_level].offset;
unsigned dst_mode = sdst->surface.u.legacy.level[dst_level].mode;
unsigned src_mode = ssrc->surface.u.legacy.level[src_level].mode;
unsigned dst_tile_index = sdst->surface.u.legacy.tiling_index[dst_level];
unsigned src_tile_index = ssrc->surface.u.legacy.tiling_index[src_level];
unsigned dst_tile_mode = info->si_tile_mode_array[dst_tile_index];
unsigned src_tile_mode = info->si_tile_mode_array[src_tile_index];
unsigned dst_micro_mode = G_009910_MICRO_TILE_MODE_NEW(dst_tile_mode);
unsigned src_micro_mode = G_009910_MICRO_TILE_MODE_NEW(src_tile_mode);
unsigned dst_tile_swizzle = dst_mode == RADEON_SURF_MODE_2D ?
rdst->surface.tile_swizzle : 0;
sdst->surface.tile_swizzle : 0;
unsigned src_tile_swizzle = src_mode == RADEON_SURF_MODE_2D ?
rsrc->surface.tile_swizzle : 0;
unsigned dst_pitch = rdst->surface.u.legacy.level[dst_level].nblk_x;
unsigned src_pitch = rsrc->surface.u.legacy.level[src_level].nblk_x;
uint64_t dst_slice_pitch = ((uint64_t)rdst->surface.u.legacy.level[dst_level].slice_size_dw * 4) / bpp;
uint64_t src_slice_pitch = ((uint64_t)rsrc->surface.u.legacy.level[src_level].slice_size_dw * 4) / bpp;
unsigned dst_width = minify_as_blocks(rdst->buffer.b.b.width0,
dst_level, rdst->surface.blk_w);
unsigned src_width = minify_as_blocks(rsrc->buffer.b.b.width0,
src_level, rsrc->surface.blk_w);
unsigned dst_height = minify_as_blocks(rdst->buffer.b.b.height0,
dst_level, rdst->surface.blk_h);
unsigned src_height = minify_as_blocks(rsrc->buffer.b.b.height0,
src_level, rsrc->surface.blk_h);
unsigned srcx = src_box->x / rsrc->surface.blk_w;
unsigned srcy = src_box->y / rsrc->surface.blk_h;
ssrc->surface.tile_swizzle : 0;
unsigned dst_pitch = sdst->surface.u.legacy.level[dst_level].nblk_x;
unsigned src_pitch = ssrc->surface.u.legacy.level[src_level].nblk_x;
uint64_t dst_slice_pitch = ((uint64_t)sdst->surface.u.legacy.level[dst_level].slice_size_dw * 4) / bpp;
uint64_t src_slice_pitch = ((uint64_t)ssrc->surface.u.legacy.level[src_level].slice_size_dw * 4) / bpp;
unsigned dst_width = minify_as_blocks(sdst->buffer.b.b.width0,
dst_level, sdst->surface.blk_w);
unsigned src_width = minify_as_blocks(ssrc->buffer.b.b.width0,
src_level, ssrc->surface.blk_w);
unsigned dst_height = minify_as_blocks(sdst->buffer.b.b.height0,
dst_level, sdst->surface.blk_h);
unsigned src_height = minify_as_blocks(ssrc->buffer.b.b.height0,
src_level, ssrc->surface.blk_h);
unsigned srcx = src_box->x / ssrc->surface.blk_w;
unsigned srcy = src_box->y / ssrc->surface.blk_h;
unsigned srcz = src_box->z;
unsigned copy_width = DIV_ROUND_UP(src_box->width, rsrc->surface.blk_w);
unsigned copy_height = DIV_ROUND_UP(src_box->height, rsrc->surface.blk_h);
unsigned copy_width = DIV_ROUND_UP(src_box->width, ssrc->surface.blk_w);
unsigned copy_height = DIV_ROUND_UP(src_box->height, ssrc->surface.blk_h);
unsigned copy_depth = src_box->depth;
assert(src_level <= src->last_level);
assert(dst_level <= dst->last_level);
assert(rdst->surface.u.legacy.level[dst_level].offset +
assert(sdst->surface.u.legacy.level[dst_level].offset +
dst_slice_pitch * bpp * (dstz + src_box->depth) <=
rdst->buffer.buf->size);
assert(rsrc->surface.u.legacy.level[src_level].offset +
sdst->buffer.buf->size);
assert(ssrc->surface.u.legacy.level[src_level].offset +
src_slice_pitch * bpp * (srcz + src_box->depth) <=
rsrc->buffer.buf->size);
ssrc->buffer.buf->size);
if (!si_prepare_for_dma_blit(sctx, rdst, dst_level, dstx, dsty,
dstz, rsrc, src_level, src_box))
if (!si_prepare_for_dma_blit(sctx, sdst, dst_level, dstx, dsty,
dstz, ssrc, src_level, src_box))
return false;
dstx /= rdst->surface.blk_w;
dsty /= rdst->surface.blk_h;
dstx /= sdst->surface.blk_w;
dsty /= sdst->surface.blk_h;
if (srcx >= (1 << 14) ||
srcy >= (1 << 14) ||
@ -232,7 +232,7 @@ static bool cik_sdma_copy_texture(struct si_context *sctx,
srcy + copy_height != (1 << 14)))) {
struct radeon_cmdbuf *cs = sctx->dma_cs;
si_need_dma_space(sctx, 13, &rdst->buffer, &rsrc->buffer);
si_need_dma_space(sctx, 13, &sdst->buffer, &ssrc->buffer);
radeon_emit(cs, CIK_SDMA_PACKET(CIK_SDMA_OPCODE_COPY,
CIK_SDMA_COPY_SUB_OPCODE_LINEAR_SUB_WINDOW, 0) |
@ -259,25 +259,25 @@ static bool cik_sdma_copy_texture(struct si_context *sctx,
/* Tiled <-> linear sub-window copy. */
if ((src_mode >= RADEON_SURF_MODE_1D) != (dst_mode >= RADEON_SURF_MODE_1D)) {
struct r600_texture *tiled = src_mode >= RADEON_SURF_MODE_1D ? rsrc : rdst;
struct r600_texture *linear = tiled == rsrc ? rdst : rsrc;
unsigned tiled_level = tiled == rsrc ? src_level : dst_level;
unsigned linear_level = linear == rsrc ? src_level : dst_level;
unsigned tiled_x = tiled == rsrc ? srcx : dstx;
unsigned linear_x = linear == rsrc ? srcx : dstx;
unsigned tiled_y = tiled == rsrc ? srcy : dsty;
unsigned linear_y = linear == rsrc ? srcy : dsty;
unsigned tiled_z = tiled == rsrc ? srcz : dstz;
unsigned linear_z = linear == rsrc ? srcz : dstz;
unsigned tiled_width = tiled == rsrc ? src_width : dst_width;
unsigned linear_width = linear == rsrc ? src_width : dst_width;
unsigned tiled_pitch = tiled == rsrc ? src_pitch : dst_pitch;
unsigned linear_pitch = linear == rsrc ? src_pitch : dst_pitch;
unsigned tiled_slice_pitch = tiled == rsrc ? src_slice_pitch : dst_slice_pitch;
unsigned linear_slice_pitch = linear == rsrc ? src_slice_pitch : dst_slice_pitch;
uint64_t tiled_address = tiled == rsrc ? src_address : dst_address;
uint64_t linear_address = linear == rsrc ? src_address : dst_address;
unsigned tiled_micro_mode = tiled == rsrc ? src_micro_mode : dst_micro_mode;
struct si_texture *tiled = src_mode >= RADEON_SURF_MODE_1D ? ssrc : sdst;
struct si_texture *linear = tiled == ssrc ? sdst : ssrc;
unsigned tiled_level = tiled == ssrc ? src_level : dst_level;
unsigned linear_level = linear == ssrc ? src_level : dst_level;
unsigned tiled_x = tiled == ssrc ? srcx : dstx;
unsigned linear_x = linear == ssrc ? srcx : dstx;
unsigned tiled_y = tiled == ssrc ? srcy : dsty;
unsigned linear_y = linear == ssrc ? srcy : dsty;
unsigned tiled_z = tiled == ssrc ? srcz : dstz;
unsigned linear_z = linear == ssrc ? srcz : dstz;
unsigned tiled_width = tiled == ssrc ? src_width : dst_width;
unsigned linear_width = linear == ssrc ? src_width : dst_width;
unsigned tiled_pitch = tiled == ssrc ? src_pitch : dst_pitch;
unsigned linear_pitch = linear == ssrc ? src_pitch : dst_pitch;
unsigned tiled_slice_pitch = tiled == ssrc ? src_slice_pitch : dst_slice_pitch;
unsigned linear_slice_pitch = linear == ssrc ? src_slice_pitch : dst_slice_pitch;
uint64_t tiled_address = tiled == ssrc ? src_address : dst_address;
uint64_t linear_address = linear == ssrc ? src_address : dst_address;
unsigned tiled_micro_mode = tiled == ssrc ? src_micro_mode : dst_micro_mode;
assert(tiled_pitch % 8 == 0);
assert(tiled_slice_pitch % 64 == 0);
@ -393,9 +393,9 @@ static bool cik_sdma_copy_texture(struct si_context *sctx,
copy_height <= (1 << 14) &&
copy_depth <= (1 << 11)) {
struct radeon_cmdbuf *cs = sctx->dma_cs;
uint32_t direction = linear == rdst ? 1u << 31 : 0;
uint32_t direction = linear == sdst ? 1u << 31 : 0;
si_need_dma_space(sctx, 14, &rdst->buffer, &rsrc->buffer);
si_need_dma_space(sctx, 14, &sdst->buffer, &ssrc->buffer);
radeon_emit(cs, CIK_SDMA_PACKET(CIK_SDMA_OPCODE_COPY,
CIK_SDMA_COPY_SUB_OPCODE_TILED_SUB_WINDOW, 0) |
@ -428,8 +428,8 @@ static bool cik_sdma_copy_texture(struct si_context *sctx,
/* check if these fit into the bitfields */
src_address % 256 == 0 &&
dst_address % 256 == 0 &&
rsrc->surface.u.legacy.tile_split <= 4096 &&
rdst->surface.u.legacy.tile_split <= 4096 &&
ssrc->surface.u.legacy.tile_split <= 4096 &&
sdst->surface.u.legacy.tile_split <= 4096 &&
dstx % 8 == 0 &&
dsty % 8 == 0 &&
srcx % 8 == 0 &&
@ -489,7 +489,7 @@ static bool cik_sdma_copy_texture(struct si_context *sctx,
dstx + copy_width != (1 << 14)))) {
struct radeon_cmdbuf *cs = sctx->dma_cs;
si_need_dma_space(sctx, 15, &rdst->buffer, &rsrc->buffer);
si_need_dma_space(sctx, 15, &sdst->buffer, &ssrc->buffer);
radeon_emit(cs, CIK_SDMA_PACKET(CIK_SDMA_OPCODE_COPY,
CIK_SDMA_COPY_SUB_OPCODE_T2T_SUB_WINDOW, 0));
@ -498,13 +498,13 @@ static bool cik_sdma_copy_texture(struct si_context *sctx,
radeon_emit(cs, srcx | (srcy << 16));
radeon_emit(cs, srcz | (src_pitch_tile_max << 16));
radeon_emit(cs, src_slice_tile_max);
radeon_emit(cs, encode_tile_info(sctx, rsrc, src_level, true));
radeon_emit(cs, encode_tile_info(sctx, ssrc, src_level, true));
radeon_emit(cs, dst_address);
radeon_emit(cs, dst_address >> 32);
radeon_emit(cs, dstx | (dsty << 16));
radeon_emit(cs, dstz | (dst_pitch_tile_max << 16));
radeon_emit(cs, dst_slice_tile_max);
radeon_emit(cs, encode_tile_info(sctx, rdst, dst_level, false));
radeon_emit(cs, encode_tile_info(sctx, sdst, dst_level, false));
if (sctx->chip_class == CIK) {
radeon_emit(cs, copy_width_aligned |
(copy_height_aligned << 16));

152
src/gallium/drivers/radeonsi/si_blit.c
View file

@ -105,8 +105,8 @@ static unsigned u_max_sample(struct pipe_resource *r)
static unsigned
si_blit_dbcb_copy(struct si_context *sctx,
struct r600_texture *src,
struct r600_texture *dst,
struct si_texture *src,
struct si_texture *dst,
unsigned planes, unsigned level_mask,
unsigned first_layer, unsigned last_layer,
unsigned first_sample, unsigned last_sample)
@ -177,8 +177,8 @@ si_blit_dbcb_copy(struct si_context *sctx,
}
void si_blit_decompress_depth(struct pipe_context *ctx,
struct r600_texture *texture,
struct r600_texture *staging,
struct si_texture *texture,
struct si_texture *staging,
unsigned first_level, unsigned last_level,
unsigned first_layer, unsigned last_layer,
unsigned first_sample, unsigned last_sample)
@ -205,7 +205,7 @@ void si_blit_decompress_depth(struct pipe_context *ctx,
*/
static void
si_blit_decompress_zs_planes_in_place(struct si_context *sctx,
struct r600_texture *texture,
struct si_texture *texture,
unsigned planes, unsigned level_mask,
unsigned first_layer, unsigned last_layer)
{
@ -274,7 +274,7 @@ si_blit_decompress_zs_planes_in_place(struct si_context *sctx,
*/
static void
si_blit_decompress_zs_in_place(struct si_context *sctx,
struct r600_texture *texture,
struct si_texture *texture,
unsigned levels_z, unsigned levels_s,
unsigned first_layer, unsigned last_layer)
{
@ -308,7 +308,7 @@ si_blit_decompress_zs_in_place(struct si_context *sctx,
static void
si_decompress_depth(struct si_context *sctx,
struct r600_texture *tex,
struct si_texture *tex,
unsigned required_planes,
unsigned first_level, unsigned last_level,
unsigned first_layer, unsigned last_layer)
@ -352,7 +352,7 @@ si_decompress_depth(struct si_context *sctx,
if (copy_planes &&
(tex->flushed_depth_texture ||
si_init_flushed_depth_texture(&sctx->b, &tex->buffer.b.b, NULL))) {
struct r600_texture *dst = tex->flushed_depth_texture;
struct si_texture *dst = tex->flushed_depth_texture;
unsigned fully_copied_levels;
unsigned levels = 0;
@ -430,7 +430,7 @@ si_decompress_sampler_depth_textures(struct si_context *sctx,
while (mask) {
struct pipe_sampler_view *view;
struct si_sampler_view *sview;
struct r600_texture *tex;
struct si_texture *tex;
i = u_bit_scan(&mask);
@ -438,7 +438,7 @@ si_decompress_sampler_depth_textures(struct si_context *sctx,
assert(view);
sview = (struct si_sampler_view*)view;
tex = (struct r600_texture *)view->texture;
tex = (struct si_texture *)view->texture;
assert(tex->db_compatible);
si_decompress_depth(sctx, tex,
@ -449,10 +449,10 @@ si_decompress_sampler_depth_textures(struct si_context *sctx,
}
static void si_blit_decompress_color(struct si_context *sctx,
struct r600_texture *rtex,
unsigned first_level, unsigned last_level,
unsigned first_layer, unsigned last_layer,
bool need_dcc_decompress)
struct si_texture *tex,
unsigned first_level, unsigned last_level,
unsigned first_layer, unsigned last_layer,
bool need_dcc_decompress)
{
void* custom_blend;
unsigned layer, checked_last_layer, max_layer;
@ -460,7 +460,7 @@ static void si_blit_decompress_color(struct si_context *sctx,
u_bit_consecutive(first_level, last_level - first_level + 1);
if (!need_dcc_decompress)
level_mask &= rtex->dirty_level_mask;
level_mask &= tex->dirty_level_mask;
if (!level_mask)
return;
@ -473,14 +473,14 @@ static void si_blit_decompress_color(struct si_context *sctx,
if (need_dcc_decompress) {
custom_blend = sctx->custom_blend_dcc_decompress;
assert(rtex->dcc_offset);
assert(tex->dcc_offset);
/* disable levels without DCC */
for (int i = first_level; i <= last_level; i++) {
if (!vi_dcc_enabled(rtex, i))
if (!vi_dcc_enabled(tex, i))
level_mask &= ~(1 << i);
}
} else if (rtex->surface.fmask_size) {
} else if (tex->surface.fmask_size) {
custom_blend = sctx->custom_blend_fmask_decompress;
} else {
custom_blend = sctx->custom_blend_eliminate_fastclear;
@ -493,17 +493,17 @@ static void si_blit_decompress_color(struct si_context *sctx,
/* The smaller the mipmap level, the less layers there are
* as far as 3D textures are concerned. */
max_layer = util_max_layer(&rtex->buffer.b.b, level);
max_layer = util_max_layer(&tex->buffer.b.b, level);
checked_last_layer = MIN2(last_layer, max_layer);
for (layer = first_layer; layer <= checked_last_layer; layer++) {
struct pipe_surface *cbsurf, surf_tmpl;
surf_tmpl.format = rtex->buffer.b.b.format;
surf_tmpl.format = tex->buffer.b.b.format;
surf_tmpl.u.tex.level = level;
surf_tmpl.u.tex.first_layer = layer;
surf_tmpl.u.tex.last_layer = layer;
cbsurf = sctx->b.create_surface(&sctx->b, &rtex->buffer.b.b, &surf_tmpl);
cbsurf = sctx->b.create_surface(&sctx->b, &tex->buffer.b.b, &surf_tmpl);
/* Required before and after FMASK and DCC_DECOMPRESS. */
if (custom_blend == sctx->custom_blend_fmask_decompress ||
@ -524,17 +524,17 @@ static void si_blit_decompress_color(struct si_context *sctx,
/* The texture will always be dirty if some layers aren't flushed.
* I don't think this case occurs often though. */
if (first_layer == 0 && last_layer >= max_layer) {
rtex->dirty_level_mask &= ~(1 << level);
tex->dirty_level_mask &= ~(1 << level);
}
}
sctx->decompression_enabled = false;
si_make_CB_shader_coherent(sctx, rtex->buffer.b.b.nr_samples,
vi_dcc_enabled(rtex, first_level));
si_make_CB_shader_coherent(sctx, tex->buffer.b.b.nr_samples,
vi_dcc_enabled(tex, first_level));
}
static void
si_decompress_color_texture(struct si_context *sctx, struct r600_texture *tex,
si_decompress_color_texture(struct si_context *sctx, struct si_texture *tex,
unsigned first_level, unsigned last_level)
{
/* CMASK or DCC can be discarded and we can still end up here. */
@ -555,14 +555,14 @@ si_decompress_sampler_color_textures(struct si_context *sctx,
while (mask) {
struct pipe_sampler_view *view;
struct r600_texture *tex;
struct si_texture *tex;
i = u_bit_scan(&mask);
view = textures->views[i];
assert(view);
tex = (struct r600_texture *)view->texture;
tex = (struct si_texture *)view->texture;
si_decompress_color_texture(sctx, tex, view->u.tex.first_level,
view->u.tex.last_level);
@ -578,14 +578,14 @@ si_decompress_image_color_textures(struct si_context *sctx,
while (mask) {
const struct pipe_image_view *view;
struct r600_texture *tex;
struct si_texture *tex;
i = u_bit_scan(&mask);
view = &images->views[i];
assert(view->resource->target != PIPE_BUFFER);
tex = (struct r600_texture *)view->resource;
tex = (struct si_texture *)view->resource;
si_decompress_color_texture(sctx, tex, view->u.tex.level,
view->u.tex.level);
@ -593,7 +593,7 @@ si_decompress_image_color_textures(struct si_context *sctx,
}
static void si_check_render_feedback_texture(struct si_context *sctx,
struct r600_texture *tex,
struct si_texture *tex,
unsigned first_level,
unsigned last_level,
unsigned first_layer,
@ -612,7 +612,7 @@ static void si_check_render_feedback_texture(struct si_context *sctx,
surf = (struct r600_surface*)sctx->framebuffer.state.cbufs[j];
if (tex == (struct r600_texture *)surf->base.texture &&
if (tex == (struct si_texture *)surf->base.texture &&
surf->base.u.tex.level >= first_level &&
surf->base.u.tex.level <= last_level &&
surf->base.u.tex.first_layer <= last_layer &&
@ -633,7 +633,7 @@ static void si_check_render_feedback_textures(struct si_context *sctx,
while (mask) {
const struct pipe_sampler_view *view;
struct r600_texture *tex;
struct si_texture *tex;
unsigned i = u_bit_scan(&mask);
@ -641,7 +641,7 @@ static void si_check_render_feedback_textures(struct si_context *sctx,
if(view->texture->target == PIPE_BUFFER)
continue;
tex = (struct r600_texture *)view->texture;
tex = (struct si_texture *)view->texture;
si_check_render_feedback_texture(sctx, tex,
view->u.tex.first_level,
@ -658,7 +658,7 @@ static void si_check_render_feedback_images(struct si_context *sctx,
while (mask) {
const struct pipe_image_view *view;
struct r600_texture *tex;
struct si_texture *tex;
unsigned i = u_bit_scan(&mask);
@ -666,7 +666,7 @@ static void si_check_render_feedback_images(struct si_context *sctx,
if (view->resource->target == PIPE_BUFFER)
continue;
tex = (struct r600_texture *)view->resource;
tex = (struct si_texture *)view->resource;
si_check_render_feedback_texture(sctx, tex,
view->u.tex.level,
@ -681,13 +681,13 @@ static void si_check_render_feedback_resident_textures(struct si_context *sctx)
util_dynarray_foreach(&sctx->resident_tex_handles,
struct si_texture_handle *, tex_handle) {
struct pipe_sampler_view *view;
struct r600_texture *tex;
struct si_texture *tex;
view = (*tex_handle)->view;
if (view->texture->target == PIPE_BUFFER)
continue;
tex = (struct r600_texture *)view->texture;
tex = (struct si_texture *)view->texture;
si_check_render_feedback_texture(sctx, tex,
view->u.tex.first_level,
@ -702,13 +702,13 @@ static void si_check_render_feedback_resident_images(struct si_context *sctx)
util_dynarray_foreach(&sctx->resident_img_handles,
struct si_image_handle *, img_handle) {
struct pipe_image_view *view;
struct r600_texture *tex;
struct si_texture *tex;
view = &(*img_handle)->view;
if (view->resource->target == PIPE_BUFFER)
continue;
tex = (struct r600_texture *)view->resource;
tex = (struct si_texture *)view->resource;
si_check_render_feedback_texture(sctx, tex,
view->u.tex.level,
@ -745,7 +745,7 @@ static void si_decompress_resident_textures(struct si_context *sctx)
util_dynarray_foreach(&sctx->resident_tex_needs_color_decompress,
struct si_texture_handle *, tex_handle) {
struct pipe_sampler_view *view = (*tex_handle)->view;
struct r600_texture *tex = (struct r600_texture *)view->texture;
struct si_texture *tex = (struct si_texture *)view->texture;
si_decompress_color_texture(sctx, tex, view->u.tex.first_level,
view->u.tex.last_level);
@ -755,7 +755,7 @@ static void si_decompress_resident_textures(struct si_context *sctx)
struct si_texture_handle *, tex_handle) {
struct pipe_sampler_view *view = (*tex_handle)->view;
struct si_sampler_view *sview = (struct si_sampler_view *)view;
struct r600_texture *tex = (struct r600_texture *)view->texture;
struct si_texture *tex = (struct si_texture *)view->texture;
si_decompress_depth(sctx, tex,
sview->is_stencil_sampler ? PIPE_MASK_S : PIPE_MASK_Z,
@ -769,7 +769,7 @@ static void si_decompress_resident_images(struct si_context *sctx)
util_dynarray_foreach(&sctx->resident_img_needs_color_decompress,
struct si_image_handle *, img_handle) {
struct pipe_image_view *view = &(*img_handle)->view;
struct r600_texture *tex = (struct r600_texture *)view->resource;
struct si_texture *tex = (struct si_texture *)view->resource;
si_decompress_color_texture(sctx, tex, view->u.tex.level,
view->u.tex.level);
@ -815,7 +815,7 @@ void si_decompress_textures(struct si_context *sctx, unsigned shader_mask)
if (sctx->ps_uses_fbfetch) {
struct pipe_surface *cb0 = sctx->framebuffer.state.cbufs[0];
si_decompress_color_texture(sctx,
(struct r600_texture*)cb0->texture,
(struct si_texture*)cb0->texture,
cb0->u.tex.first_layer,
cb0->u.tex.last_layer);
}
@ -839,12 +839,12 @@ static void si_decompress_subresource(struct pipe_context *ctx,
unsigned first_layer, unsigned last_layer)
{
struct si_context *sctx = (struct si_context *)ctx;
struct r600_texture *rtex = (struct r600_texture*)tex;
struct si_texture *stex = (struct si_texture*)tex;
if (rtex->db_compatible) {
if (stex->db_compatible) {
planes &= PIPE_MASK_Z | PIPE_MASK_S;
if (!rtex->surface.has_stencil)
if (!stex->surface.has_stencil)
planes &= ~PIPE_MASK_S;
/* If we've rendered into the framebuffer and it's a blitting
@ -856,10 +856,10 @@ static void si_decompress_subresource(struct pipe_context *ctx,
sctx->framebuffer.state.zsbuf->texture == tex)
si_update_fb_dirtiness_after_rendering(sctx);
si_decompress_depth(sctx, rtex, planes,
si_decompress_depth(sctx, stex, planes,
level, level,
first_layer, last_layer);
} else if (rtex->surface.fmask_size || rtex->cmask.size || rtex->dcc_offset) {
} else if (stex->surface.fmask_size || stex->cmask.size || stex->dcc_offset) {
/* If we've rendered into the framebuffer and it's a blitting
* source, make sure the decompression pass is invoked
* by dirtying the framebuffer.
@ -873,7 +873,7 @@ static void si_decompress_subresource(struct pipe_context *ctx,
}
}
si_blit_decompress_color(sctx, rtex, level, level,
si_blit_decompress_color(sctx, stex, level, level,
first_layer, last_layer, false);
}
}
@ -897,7 +897,7 @@ void si_resource_copy_region(struct pipe_context *ctx,
const struct pipe_box *src_box)
{
struct si_context *sctx = (struct si_context *)ctx;
struct r600_texture *rsrc = (struct r600_texture*)src;
struct si_texture *ssrc = (struct si_texture*)src;
struct pipe_surface *dst_view, dst_templ;
struct pipe_sampler_view src_templ, *src_view;
unsigned dst_width, dst_height, src_width0, src_height0;
@ -929,7 +929,7 @@ void si_resource_copy_region(struct pipe_context *ctx,
if (util_format_is_compressed(src->format) ||
util_format_is_compressed(dst->format)) {
unsigned blocksize = rsrc->surface.bpe;
unsigned blocksize = ssrc->surface.bpe;
if (blocksize == 8)
src_templ.format = PIPE_FORMAT_R16G16B16A16_UINT; /* 64-bit block */
@ -972,7 +972,7 @@ void si_resource_copy_region(struct pipe_context *ctx,
sbox.width = util_format_get_nblocksx(src->format, src_box->width);
src_box = &sbox;
} else {
unsigned blocksize = rsrc->surface.bpe;
unsigned blocksize = ssrc->surface.bpe;
switch (blocksize) {
case 1:
@ -1095,9 +1095,9 @@ static bool do_hardware_msaa_resolve(struct pipe_context *ctx,
const struct pipe_blit_info *info)
{
struct si_context *sctx = (struct si_context*)ctx;
struct r600_texture *src = (struct r600_texture*)info->src.resource;
struct r600_texture *dst = (struct r600_texture*)info->dst.resource;
MAYBE_UNUSED struct r600_texture *rtmp;
struct si_texture *src = (struct si_texture*)info->src.resource;
struct si_texture *dst = (struct si_texture*)info->dst.resource;
MAYBE_UNUSED struct si_texture *stmp;
unsigned dst_width = u_minify(info->dst.resource->width0, info->dst.level);
unsigned dst_height = u_minify(info->dst.resource->height0, info->dst.level);
enum pipe_format format = info->src.format;
@ -1196,10 +1196,10 @@ resolve_to_temp:
tmp = ctx->screen->resource_create(ctx->screen, &templ);
if (!tmp)
return false;
rtmp = (struct r600_texture*)tmp;
stmp = (struct si_texture*)tmp;
assert(!rtmp->surface.is_linear);
assert(src->surface.micro_tile_mode == rtmp->surface.micro_tile_mode);
assert(!stmp->surface.is_linear);
assert(src->surface.micro_tile_mode == stmp->surface.micro_tile_mode);
/* resolve */
si_do_CB_resolve(sctx, info, tmp, 0, 0, format);
@ -1222,7 +1222,7 @@ static void si_blit(struct pipe_context *ctx,
const struct pipe_blit_info *info)
{
struct si_context *sctx = (struct si_context*)ctx;
struct r600_texture *rdst = (struct r600_texture *)info->dst.resource;
struct si_texture *dst = (struct si_texture *)info->dst.resource;
if (do_hardware_msaa_resolve(ctx, info)) {
return;
@ -1234,7 +1234,7 @@ static void si_blit(struct pipe_context *ctx,
* resource_copy_region can't do this yet, because dma_copy calls it
* on failure (recursion).
*/
if (rdst->surface.is_linear &&
if (dst->surface.is_linear &&
sctx->dma_copy &&
util_can_blit_via_copy_region(info, false)) {
sctx->dma_copy(ctx, info->dst.resource, info->dst.level,
@ -1277,7 +1277,7 @@ static boolean si_generate_mipmap(struct pipe_context *ctx,
unsigned first_layer, unsigned last_layer)
{
struct si_context *sctx = (struct si_context*)ctx;
struct r600_texture *rtex = (struct r600_texture *)tex;
struct si_texture *stex = (struct si_texture *)tex;
if (!util_blitter_is_copy_supported(sctx->blitter, tex, tex))
return false;
@ -1291,10 +1291,10 @@ static boolean si_generate_mipmap(struct pipe_context *ctx,
/* Clear dirty_level_mask for the levels that will be overwritten. */
assert(base_level < last_level);
rtex->dirty_level_mask &= ~u_bit_consecutive(base_level + 1,
stex->dirty_level_mask &= ~u_bit_consecutive(base_level + 1,
last_level - base_level);
sctx->generate_mipmap_for_depth = rtex->is_depth;
sctx->generate_mipmap_for_depth = stex->is_depth;
si_blitter_begin(sctx, SI_BLIT | SI_DISABLE_RENDER_COND);
util_blitter_generate_mipmap(sctx->blitter, tex, format,
@ -1310,36 +1310,36 @@ static void si_flush_resource(struct pipe_context *ctx,
struct pipe_resource *res)
{
struct si_context *sctx = (struct si_context*)ctx;
struct r600_texture *rtex = (struct r600_texture*)res;
struct si_texture *tex = (struct si_texture*)res;
assert(res->target != PIPE_BUFFER);
assert(!rtex->dcc_separate_buffer || rtex->dcc_gather_statistics);
assert(!tex->dcc_separate_buffer || tex->dcc_gather_statistics);
/* st/dri calls flush twice per frame (not a bug), this prevents double
* decompression. */
if (rtex->dcc_separate_buffer && !rtex->separate_dcc_dirty)
if (tex->dcc_separate_buffer && !tex->separate_dcc_dirty)
return;
if (!rtex->is_depth && (rtex->cmask.size || rtex->dcc_offset)) {
si_blit_decompress_color(sctx, rtex, 0, res->last_level,
if (!tex->is_depth && (tex->cmask.size || tex->dcc_offset)) {
si_blit_decompress_color(sctx, tex, 0, res->last_level,
0, util_max_layer(res, 0),
rtex->dcc_separate_buffer != NULL);
tex->dcc_separate_buffer != NULL);
}
/* Always do the analysis even if DCC is disabled at the moment. */
if (rtex->dcc_gather_statistics && rtex->separate_dcc_dirty) {
rtex->separate_dcc_dirty = false;
vi_separate_dcc_process_and_reset_stats(ctx, rtex);
if (tex->dcc_gather_statistics && tex->separate_dcc_dirty) {
tex->separate_dcc_dirty = false;
vi_separate_dcc_process_and_reset_stats(ctx, tex);
}
}
void si_decompress_dcc(struct si_context *sctx, struct r600_texture *rtex)
void si_decompress_dcc(struct si_context *sctx, struct si_texture *tex)
{
if (!rtex->dcc_offset)
if (!tex->dcc_offset)
return;
si_blit_decompress_color(sctx, rtex, 0, rtex->buffer.b.b.last_level,
0, util_max_layer(&rtex->buffer.b.b, 0),
si_blit_decompress_color(sctx, tex, 0, tex->buffer.b.b.last_level,
0, util_max_layer(&tex->buffer.b.b, 0),
true);
}

4
src/gallium/drivers/radeonsi/si_buffer.c
View file

@ -104,7 +104,7 @@ void si_init_resource_fields(struct si_screen *sscreen,
struct r600_resource *res,
uint64_t size, unsigned alignment)
{
struct r600_texture *rtex = (struct r600_texture*)res;
struct si_texture *tex = (struct si_texture*)res;
res->bo_size = size;
res->bo_alignment = alignment;
@ -160,7 +160,7 @@ void si_init_resource_fields(struct si_screen *sscreen,
}
/* Tiled textures are unmappable. Always put them in VRAM. */
if ((res->b.b.target != PIPE_BUFFER && !rtex->surface.is_linear) ||
if ((res->b.b.target != PIPE_BUFFER && !tex->surface.is_linear) ||
res->b.b.flags & SI_RESOURCE_FLAG_UNMAPPABLE) {
res->domains = RADEON_DOMAIN_VRAM;
res->flags |= RADEON_FLAG_NO_CPU_ACCESS |

138
src/gallium/drivers/radeonsi/si_clear.c
View file

@ -35,37 +35,37 @@ enum {
};
static void si_alloc_separate_cmask(struct si_screen *sscreen,
struct r600_texture *rtex)
struct si_texture *tex)
{
if (rtex->cmask_buffer)
if (tex->cmask_buffer)
return;
assert(rtex->cmask.size == 0);
assert(tex->cmask.size == 0);
si_texture_get_cmask_info(sscreen, rtex, &rtex->cmask);
if (!rtex->cmask.size)
si_texture_get_cmask_info(sscreen, tex, &tex->cmask);
if (!tex->cmask.size)
return;
rtex->cmask_buffer =
tex->cmask_buffer =
si_aligned_buffer_create(&sscreen->b,
SI_RESOURCE_FLAG_UNMAPPABLE,
PIPE_USAGE_DEFAULT,
rtex->cmask.size,
rtex->cmask.alignment);
if (rtex->cmask_buffer == NULL) {
rtex->cmask.size = 0;
tex->cmask.size,
tex->cmask.alignment);
if (tex->cmask_buffer == NULL) {
tex->cmask.size = 0;
return;
}
/* update colorbuffer state bits */
rtex->cmask.base_address_reg = rtex->cmask_buffer->gpu_address >> 8;
tex->cmask.base_address_reg = tex->cmask_buffer->gpu_address >> 8;
rtex->cb_color_info |= S_028C70_FAST_CLEAR(1);
tex->cb_color_info |= S_028C70_FAST_CLEAR(1);
p_atomic_inc(&sscreen->compressed_colortex_counter);
}
static bool si_set_clear_color(struct r600_texture *rtex,
static bool si_set_clear_color(struct si_texture *tex,
enum pipe_format surface_format,
const union pipe_color_union *color)
{
@ -73,7 +73,7 @@ static bool si_set_clear_color(struct r600_texture *rtex,
memset(&uc, 0, sizeof(uc));
if (rtex->surface.bpe == 16) {
if (tex->surface.bpe == 16) {
/* DCC fast clear only:
* CLEAR_WORD0 = R = G = B
* CLEAR_WORD1 = A
@ -90,10 +90,10 @@ static bool si_set_clear_color(struct r600_texture *rtex,
util_pack_color(color->f, surface_format, &uc);
}
if (memcmp(rtex->color_clear_value, &uc, 2 * sizeof(uint32_t)) == 0)
if (memcmp(tex->color_clear_value, &uc, 2 * sizeof(uint32_t)) == 0)
return false;
memcpy(rtex->color_clear_value, &uc, 2 * sizeof(uint32_t));
memcpy(tex->color_clear_value, &uc, 2 * sizeof(uint32_t));
return true;
}
@ -226,42 +226,42 @@ static bool vi_get_fast_clear_parameters(enum pipe_format base_format,
}
void vi_dcc_clear_level(struct si_context *sctx,
struct r600_texture *rtex,
struct si_texture *tex,
unsigned level, unsigned clear_value)
{
struct pipe_resource *dcc_buffer;
uint64_t dcc_offset, clear_size;
assert(vi_dcc_enabled(rtex, level));
assert(vi_dcc_enabled(tex, level));
if (rtex->dcc_separate_buffer) {
dcc_buffer = &rtex->dcc_separate_buffer->b.b;
if (tex->dcc_separate_buffer) {
dcc_buffer = &tex->dcc_separate_buffer->b.b;
dcc_offset = 0;
} else {
dcc_buffer = &rtex->buffer.b.b;
dcc_offset = rtex->dcc_offset;
dcc_buffer = &tex->buffer.b.b;
dcc_offset = tex->dcc_offset;
}
if (sctx->chip_class >= GFX9) {
/* Mipmap level clears aren't implemented. */
assert(rtex->buffer.b.b.last_level == 0);
assert(tex->buffer.b.b.last_level == 0);
/* 4x and 8x MSAA needs a sophisticated compute shader for
* the clear. See AMDVLK. */
assert(rtex->num_color_samples <= 2);
clear_size = rtex->surface.dcc_size;
assert(tex->num_color_samples <= 2);
clear_size = tex->surface.dcc_size;
} else {
unsigned num_layers = util_num_layers(&rtex->buffer.b.b, level);
unsigned num_layers = util_num_layers(&tex->buffer.b.b, level);
/* If this is 0, fast clear isn't possible. (can occur with MSAA) */
assert(rtex->surface.u.legacy.level[level].dcc_fast_clear_size);
assert(tex->surface.u.legacy.level[level].dcc_fast_clear_size);
/* Layered 4x and 8x MSAA DCC fast clears need to clear
* dcc_fast_clear_size bytes for each layer. A compute shader
* would be more efficient than separate per-layer clear operations.
*/
assert(rtex->num_color_samples <= 2 || num_layers == 1);
assert(tex->num_color_samples <= 2 || num_layers == 1);
dcc_offset += rtex->surface.u.legacy.level[level].dcc_offset;
clear_size = rtex->surface.u.legacy.level[level].dcc_fast_clear_size *
dcc_offset += tex->surface.u.legacy.level[level].dcc_offset;
clear_size = tex->surface.u.legacy.level[level].dcc_fast_clear_size *
num_layers;
}
@ -274,20 +274,20 @@ void vi_dcc_clear_level(struct si_context *sctx,
* src and dst micro tile modes match.
*/
static void si_set_optimal_micro_tile_mode(struct si_screen *sscreen,
struct r600_texture *rtex)
struct si_texture *tex)
{
if (rtex->buffer.b.is_shared ||
rtex->buffer.b.b.nr_samples <= 1 ||
rtex->surface.micro_tile_mode == rtex->last_msaa_resolve_target_micro_mode)
if (tex->buffer.b.is_shared ||
tex->buffer.b.b.nr_samples <= 1 ||
tex->surface.micro_tile_mode == tex->last_msaa_resolve_target_micro_mode)
return;
assert(sscreen->info.chip_class >= GFX9 ||
rtex->surface.u.legacy.level[0].mode == RADEON_SURF_MODE_2D);
assert(rtex->buffer.b.b.last_level == 0);
tex->surface.u.legacy.level[0].mode == RADEON_SURF_MODE_2D);
assert(tex->buffer.b.b.last_level == 0);
if (sscreen->info.chip_class >= GFX9) {
/* 4K or larger tiles only. 0 is linear. 1-3 are 256B tiles. */
assert(rtex->surface.u.gfx9.surf.swizzle_mode >= 4);
assert(tex->surface.u.gfx9.surf.swizzle_mode >= 4);
/* If you do swizzle_mode % 4, you'll get:
* 0 = Depth
@ -297,20 +297,20 @@ static void si_set_optimal_micro_tile_mode(struct si_screen *sscreen,
*
* Depth-sample order isn't allowed:
*/
assert(rtex->surface.u.gfx9.surf.swizzle_mode % 4 != 0);
assert(tex->surface.u.gfx9.surf.swizzle_mode % 4 != 0);
switch (rtex->last_msaa_resolve_target_micro_mode) {
switch (tex->last_msaa_resolve_target_micro_mode) {
case RADEON_MICRO_MODE_DISPLAY:
rtex->surface.u.gfx9.surf.swizzle_mode &= ~0x3;
rtex->surface.u.gfx9.surf.swizzle_mode += 2; /* D */
tex->surface.u.gfx9.surf.swizzle_mode &= ~0x3;
tex->surface.u.gfx9.surf.swizzle_mode += 2; /* D */
break;
case RADEON_MICRO_MODE_THIN:
rtex->surface.u.gfx9.surf.swizzle_mode &= ~0x3;
rtex->surface.u.gfx9.surf.swizzle_mode += 1; /* S */
tex->surface.u.gfx9.surf.swizzle_mode &= ~0x3;
tex->surface.u.gfx9.surf.swizzle_mode += 1; /* S */
break;
case RADEON_MICRO_MODE_ROTATED:
rtex->surface.u.gfx9.surf.swizzle_mode &= ~0x3;
rtex->surface.u.gfx9.surf.swizzle_mode += 3; /* R */
tex->surface.u.gfx9.surf.swizzle_mode &= ~0x3;
tex->surface.u.gfx9.surf.swizzle_mode += 3; /* R */
break;
default: /* depth */
assert(!"unexpected micro mode");
@ -321,48 +321,48 @@ static void si_set_optimal_micro_tile_mode(struct si_screen *sscreen,
* any definitions for them either. They are all 2D_TILED_THIN1
* modes with different bpp and micro tile mode.
*/
switch (rtex->last_msaa_resolve_target_micro_mode) {
switch (tex->last_msaa_resolve_target_micro_mode) {
case RADEON_MICRO_MODE_DISPLAY:
rtex->surface.u.legacy.tiling_index[0] = 10;
tex->surface.u.legacy.tiling_index[0] = 10;
break;
case RADEON_MICRO_MODE_THIN:
rtex->surface.u.legacy.tiling_index[0] = 14;
tex->surface.u.legacy.tiling_index[0] = 14;
break;
case RADEON_MICRO_MODE_ROTATED:
rtex->surface.u.legacy.tiling_index[0] = 28;
tex->surface.u.legacy.tiling_index[0] = 28;
break;
default: /* depth, thick */
assert(!"unexpected micro mode");
return;
}
} else { /* SI */
switch (rtex->last_msaa_resolve_target_micro_mode) {
switch (tex->last_msaa_resolve_target_micro_mode) {
case RADEON_MICRO_MODE_DISPLAY:
switch (rtex->surface.bpe) {
switch (tex->surface.bpe) {
case 1:
rtex->surface.u.legacy.tiling_index[0] = 10;
tex->surface.u.legacy.tiling_index[0] = 10;
break;
case 2:
rtex->surface.u.legacy.tiling_index[0] = 11;
tex->surface.u.legacy.tiling_index[0] = 11;
break;
default: /* 4, 8 */
rtex->surface.u.legacy.tiling_index[0] = 12;
tex->surface.u.legacy.tiling_index[0] = 12;
break;
}
break;
case RADEON_MICRO_MODE_THIN:
switch (rtex->surface.bpe) {
switch (tex->surface.bpe) {
case 1:
rtex->surface.u.legacy.tiling_index[0] = 14;
tex->surface.u.legacy.tiling_index[0] = 14;
break;
case 2:
rtex->surface.u.legacy.tiling_index[0] = 15;
tex->surface.u.legacy.tiling_index[0] = 15;
break;
case 4:
rtex->surface.u.legacy.tiling_index[0] = 16;
tex->surface.u.legacy.tiling_index[0] = 16;
break;
default: /* 8, 16 */
rtex->surface.u.legacy.tiling_index[0] = 17;
tex->surface.u.legacy.tiling_index[0] = 17;
break;
}
break;
@ -372,7 +372,7 @@ static void si_set_optimal_micro_tile_mode(struct si_screen *sscreen,
}
}
rtex->surface.micro_tile_mode = rtex->last_msaa_resolve_target_micro_mode;
tex->surface.micro_tile_mode = tex->last_msaa_resolve_target_micro_mode;
p_atomic_inc(&sscreen->dirty_tex_counter);
}
@ -393,7 +393,7 @@ static void si_do_fast_color_clear(struct si_context *sctx,
return;
for (i = 0; i < fb->nr_cbufs; i++) {
struct r600_texture *tex;
struct si_texture *tex;
unsigned clear_bit = PIPE_CLEAR_COLOR0 << i;
if (!fb->cbufs[i])
@ -407,7 +407,7 @@ static void si_do_fast_color_clear(struct si_context *sctx,
if (level > 0)
continue;
tex = (struct r600_texture *)fb->cbufs[i]->texture;
tex = (struct si_texture *)fb->cbufs[i]->texture;
/* TODO: GFX9: Implement DCC fast clear for level 0 of
* mipmapped textures. Mipmapped DCC has to clear a rectangular
@ -561,8 +561,8 @@ static void si_clear(struct pipe_context *ctx, unsigned buffers,
struct si_context *sctx = (struct si_context *)ctx;
struct pipe_framebuffer_state *fb = &sctx->framebuffer.state;
struct pipe_surface *zsbuf = fb->zsbuf;
struct r600_texture *zstex =
zsbuf ? (struct r600_texture*)zsbuf->texture : NULL;
struct si_texture *zstex =
zsbuf ? (struct si_texture*)zsbuf->texture : NULL;
if (buffers & PIPE_CLEAR_COLOR) {
si_do_fast_color_clear(sctx, &buffers, color);
@ -571,13 +571,13 @@ static void si_clear(struct pipe_context *ctx, unsigned buffers,
/* These buffers cannot use fast clear, make sure to disable expansion. */
for (unsigned i = 0; i < fb->nr_cbufs; i++) {
struct r600_texture *tex;
struct si_texture *tex;
/* If not clearing this buffer, skip. */
if (!(buffers & (PIPE_CLEAR_COLOR0 << i)) || !fb->cbufs[i])
continue;
tex = (struct r600_texture *)fb->cbufs[i]->texture;
tex = (struct si_texture *)fb->cbufs[i]->texture;
if (tex->surface.fmask_size == 0)
tex->dirty_level_mask &= ~(1 << fb->cbufs[i]->u.tex.level);
}
@ -706,7 +706,7 @@ static void si_clear_texture(struct pipe_context *pipe,
const void *data)
{
struct pipe_screen *screen = pipe->screen;
struct r600_texture *rtex = (struct r600_texture*)tex;
struct si_texture *stex = (struct si_texture*)tex;
struct pipe_surface tmpl = {{0}};
struct pipe_surface *sf;
const struct util_format_description *desc =
@ -720,7 +720,7 @@ static void si_clear_texture(struct pipe_context *pipe,
if (!sf)
return;
if (rtex->is_depth) {
if (stex->is_depth) {
unsigned clear;
float depth;
uint8_t stencil = 0;
@ -729,7 +729,7 @@ static void si_clear_texture(struct pipe_context *pipe,
clear = PIPE_CLEAR_DEPTH;
desc->unpack_z_float(&depth, 0, data, 0, 1, 1);
if (rtex->surface.has_stencil) {
if (stex->surface.has_stencil) {
clear |= PIPE_CLEAR_STENCIL;
desc->unpack_s_8uint(&stencil, 0, data, 0, 1, 1);
}

10
src/gallium/drivers/radeonsi/si_debug.c
View file

@ -590,23 +590,23 @@ static void si_dump_bo_list(struct si_context *sctx,
static void si_dump_framebuffer(struct si_context *sctx, struct u_log_context *log)
{
struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
struct r600_texture *rtex;
struct si_texture *tex;
int i;
for (i = 0; i < state->nr_cbufs; i++) {
if (!state->cbufs[i])
continue;
rtex = (struct r600_texture*)state->cbufs[i]->texture;
tex = (struct si_texture*)state->cbufs[i]->texture;
u_log_printf(log, COLOR_YELLOW "Color buffer %i:" COLOR_RESET "\n", i);
si_print_texture_info(sctx->screen, rtex, log);
si_print_texture_info(sctx->screen, tex, log);
u_log_printf(log, "\n");
}
if (state->zsbuf) {
rtex = (struct r600_texture*)state->zsbuf->texture;
tex = (struct si_texture*)state->zsbuf->texture;
u_log_printf(log, COLOR_YELLOW "Depth-stencil buffer:" COLOR_RESET "\n");
si_print_texture_info(sctx->screen, rtex, log);
si_print_texture_info(sctx->screen, tex, log);
u_log_printf(log, "\n");
}
}

128
src/gallium/drivers/radeonsi/si_descriptors.c
View file

@ -248,33 +248,27 @@ static void si_sampler_view_add_buffer(struct si_context *sctx,
bool is_stencil_sampler,
bool check_mem)
{
struct r600_resource *rres;
struct r600_texture *rtex;
struct si_texture *tex = (struct si_texture*)resource;
enum radeon_bo_priority priority;
if (!resource)
return;
if (resource->target != PIPE_BUFFER) {
struct r600_texture *tex = (struct r600_texture*)resource;
/* Use the flushed depth texture if direct sampling is unsupported. */
if (resource->target != PIPE_BUFFER &&
tex->is_depth && !si_can_sample_zs(tex, is_stencil_sampler))
tex = tex->flushed_depth_texture;
if (tex->is_depth && !si_can_sample_zs(tex, is_stencil_sampler))
resource = &tex->flushed_depth_texture->buffer.b.b;
}
rres = r600_resource(resource);
priority = si_get_sampler_view_priority(rres);
radeon_add_to_gfx_buffer_list_check_mem(sctx, rres, usage, priority,
priority = si_get_sampler_view_priority(&tex->buffer);
radeon_add_to_gfx_buffer_list_check_mem(sctx, &tex->buffer, usage, priority,
check_mem);
if (resource->target == PIPE_BUFFER)
return;
/* Now add separate DCC or HTILE. */
rtex = (struct r600_texture*)resource;
if (rtex->dcc_separate_buffer) {
radeon_add_to_gfx_buffer_list_check_mem(sctx, rtex->dcc_separate_buffer,
/* Add separate DCC. */
if (tex->dcc_separate_buffer) {
radeon_add_to_gfx_buffer_list_check_mem(sctx, tex->dcc_separate_buffer,
usage, RADEON_PRIO_DCC, check_mem);
}
}
@ -317,7 +311,7 @@ static void si_set_buf_desc_address(struct r600_resource *buf,
* \param state descriptor to update
*/
void si_set_mutable_tex_desc_fields(struct si_screen *sscreen,
struct r600_texture *tex,
struct si_texture *tex,
const struct legacy_surf_level *base_level_info,
unsigned base_level, unsigned first_level,
unsigned block_width, bool is_stencil,
@ -418,7 +412,7 @@ void si_set_mutable_tex_desc_fields(struct si_screen *sscreen,
static void si_set_sampler_state_desc(struct si_sampler_state *sstate,
struct si_sampler_view *sview,
struct r600_texture *tex,
struct si_texture *tex,
uint32_t *desc)
{
if (sview && sview->is_integer)
@ -436,29 +430,29 @@ static void si_set_sampler_view_desc(struct si_context *sctx,
uint32_t *desc)
{
struct pipe_sampler_view *view = &sview->base;
struct r600_texture *rtex = (struct r600_texture *)view->texture;
bool is_buffer = rtex->buffer.b.b.target == PIPE_BUFFER;
struct si_texture *tex = (struct si_texture *)view->texture;
bool is_buffer = tex->buffer.b.b.target == PIPE_BUFFER;
if (unlikely(!is_buffer && sview->dcc_incompatible)) {
if (vi_dcc_enabled(rtex, view->u.tex.first_level))
if (!si_texture_disable_dcc(sctx, rtex))
si_decompress_dcc(sctx, rtex);
if (vi_dcc_enabled(tex, view->u.tex.first_level))
if (!si_texture_disable_dcc(sctx, tex))
si_decompress_dcc(sctx, tex);
sview->dcc_incompatible = false;
}
assert(rtex); /* views with texture == NULL aren't supported */
assert(tex); /* views with texture == NULL aren't supported */
memcpy(desc, sview->state, 8*4);
if (is_buffer) {
si_set_buf_desc_address(&rtex->buffer,
si_set_buf_desc_address(&tex->buffer,
sview->base.u.buf.offset,
desc + 4);
} else {
bool is_separate_stencil = rtex->db_compatible &&
bool is_separate_stencil = tex->db_compatible &&
sview->is_stencil_sampler;
si_set_mutable_tex_desc_fields(sctx->screen, rtex,
si_set_mutable_tex_desc_fields(sctx->screen, tex,
sview->base_level_info,
sview->base_level,
sview->base.u.tex.first_level,
@ -467,7 +461,7 @@ static void si_set_sampler_view_desc(struct si_context *sctx,
desc);
}
if (!is_buffer && rtex->surface.fmask_size) {
if (!is_buffer && tex->surface.fmask_size) {
memcpy(desc + 8, sview->fmask_state, 8*4);
} else {
/* Disable FMASK and bind sampler state in [12:15]. */
@ -475,26 +469,26 @@ static void si_set_sampler_view_desc(struct si_context *sctx,
if (sstate)
si_set_sampler_state_desc(sstate, sview,
is_buffer ? NULL : rtex,
is_buffer ? NULL : tex,
desc + 12);
}
}
static bool color_needs_decompression(struct r600_texture *rtex)
static bool color_needs_decompression(struct si_texture *tex)
{
return rtex->surface.fmask_size ||
(rtex->dirty_level_mask &&
(rtex->cmask.size || rtex->dcc_offset));
return tex->surface.fmask_size ||
(tex->dirty_level_mask &&
(tex->cmask.size || tex->dcc_offset));
}
static bool depth_needs_decompression(struct r600_texture *rtex)
static bool depth_needs_decompression(struct si_texture *tex)
{
/* If the depth/stencil texture is TC-compatible, no decompression
* will be done. The decompression function will only flush DB caches
* to make it coherent with shaders. That's necessary because the driver
* doesn't flush DB caches in any other case.
*/
return rtex->db_compatible;
return tex->db_compatible;
}
static void si_set_sampler_view(struct si_context *sctx,
@ -512,29 +506,29 @@ static void si_set_sampler_view(struct si_context *sctx,
return;
if (view) {
struct r600_texture *rtex = (struct r600_texture *)view->texture;
struct si_texture *tex = (struct si_texture *)view->texture;
si_set_sampler_view_desc(sctx, rview,
samplers->sampler_states[slot], desc);
if (rtex->buffer.b.b.target == PIPE_BUFFER) {
rtex->buffer.bind_history |= PIPE_BIND_SAMPLER_VIEW;
if (tex->buffer.b.b.target == PIPE_BUFFER) {
tex->buffer.bind_history |= PIPE_BIND_SAMPLER_VIEW;
samplers->needs_depth_decompress_mask &= ~(1u << slot);
samplers->needs_color_decompress_mask &= ~(1u << slot);
} else {
if (depth_needs_decompression(rtex)) {
if (depth_needs_decompression(tex)) {
samplers->needs_depth_decompress_mask |= 1u << slot;
} else {
samplers->needs_depth_decompress_mask &= ~(1u << slot);
}
if (color_needs_decompression(rtex)) {
if (color_needs_decompression(tex)) {
samplers->needs_color_decompress_mask |= 1u << slot;
} else {
samplers->needs_color_decompress_mask &= ~(1u << slot);
}
if (rtex->dcc_offset &&
p_atomic_read(&rtex->framebuffers_bound))
if (tex->dcc_offset &&
p_atomic_read(&tex->framebuffers_bound))
sctx->need_check_render_feedback = true;
}
@ -610,9 +604,9 @@ si_samplers_update_needs_color_decompress_mask(struct si_samplers *samplers)
struct pipe_resource *res = samplers->views[i]->texture;
if (res && res->target != PIPE_BUFFER) {
struct r600_texture *rtex = (struct r600_texture *)res;
struct si_texture *tex = (struct si_texture *)res;
if (color_needs_decompression(rtex)) {
if (color_needs_decompression(tex)) {
samplers->needs_color_decompress_mask |= 1u << i;
} else {
samplers->needs_color_decompress_mask &= ~(1u << i);
@ -703,7 +697,7 @@ static void si_set_shader_image_desc(struct si_context *ctx,
si_set_buf_desc_address(res, view->u.buf.offset, desc + 4);
} else {
static const unsigned char swizzle[4] = { 0, 1, 2, 3 };
struct r600_texture *tex = (struct r600_texture *)res;
struct si_texture *tex = (struct si_texture *)res;
unsigned level = view->u.tex.level;
unsigned width, height, depth, hw_level;
bool uses_dcc = vi_dcc_enabled(tex, level);
@ -797,7 +791,7 @@ static void si_set_shader_image(struct si_context *ctx,
images->needs_color_decompress_mask &= ~(1 << slot);
res->bind_history |= PIPE_BIND_SHADER_IMAGE;
} else {
struct r600_texture *tex = (struct r600_texture *)res;
struct si_texture *tex = (struct si_texture *)res;
unsigned level = view->u.tex.level;
if (color_needs_decompression(tex)) {
@ -858,9 +852,9 @@ si_images_update_needs_color_decompress_mask(struct si_images *images)
struct pipe_resource *res = images->views[i].resource;
if (res && res->target != PIPE_BUFFER) {
struct r600_texture *rtex = (struct r600_texture *)res;
struct si_texture *tex = (struct si_texture *)res;
if (color_needs_decompression(rtex)) {
if (color_needs_decompression(tex)) {
images->needs_color_decompress_mask |= 1 << i;
} else {
images->needs_color_decompress_mask &= ~(1 << i);
@ -895,7 +889,7 @@ void si_update_ps_colorbuf0_slot(struct si_context *sctx)
si_update_ps_iter_samples(sctx);
if (surf) {
struct r600_texture *tex = (struct r600_texture*)surf->texture;
struct si_texture *tex = (struct si_texture*)surf->texture;
struct pipe_image_view view;
assert(tex);
@ -974,11 +968,11 @@ static void si_bind_sampler_states(struct pipe_context *ctx,
struct si_sampler_view *sview =
(struct si_sampler_view *)samplers->views[slot];
struct r600_texture *tex = NULL;
struct si_texture *tex = NULL;
if (sview && sview->base.texture &&
sview->base.texture->target != PIPE_BUFFER)
tex = (struct r600_texture *)sview->base.texture;
tex = (struct si_texture *)sview->base.texture;
if (tex && tex->surface.fmask_size)
continue;
@ -1530,13 +1524,13 @@ si_resident_handles_update_needs_color_decompress(struct si_context *sctx)
util_dynarray_foreach(&sctx->resident_tex_handles,
struct si_texture_handle *, tex_handle) {
struct pipe_resource *res = (*tex_handle)->view->texture;
struct r600_texture *rtex;
struct si_texture *tex;
if (!res || res->target == PIPE_BUFFER)
continue;
rtex = (struct r600_texture *)res;
if (!color_needs_decompression(rtex))
tex = (struct si_texture *)res;
if (!color_needs_decompression(tex))
continue;
util_dynarray_append(&sctx->resident_tex_needs_color_decompress,
@ -1547,13 +1541,13 @@ si_resident_handles_update_needs_color_decompress(struct si_context *sctx)
struct si_image_handle *, img_handle) {
struct pipe_image_view *view = &(*img_handle)->view;
struct pipe_resource *res = view->resource;
struct r600_texture *rtex;
struct si_texture *tex;
if (!res || res->target == PIPE_BUFFER)
continue;
rtex = (struct r600_texture *)res;
if (!color_needs_decompression(rtex))
tex = (struct si_texture *)res;
if (!color_needs_decompression(tex))
continue;
util_dynarray_append(&sctx->resident_img_needs_color_decompress,
@ -2427,25 +2421,25 @@ static void si_make_texture_handle_resident(struct pipe_context *ctx,
if (resident) {
if (sview->base.texture->target != PIPE_BUFFER) {
struct r600_texture *rtex =
(struct r600_texture *)sview->base.texture;
struct si_texture *tex =
(struct si_texture *)sview->base.texture;
if (depth_needs_decompression(rtex)) {
if (depth_needs_decompression(tex)) {
util_dynarray_append(
&sctx->resident_tex_needs_depth_decompress,
struct si_texture_handle *,
tex_handle);
}
if (color_needs_decompression(rtex)) {
if (color_needs_decompression(tex)) {
util_dynarray_append(
&sctx->resident_tex_needs_color_decompress,
struct si_texture_handle *,
tex_handle);
}
if (rtex->dcc_offset &&
p_atomic_read(&rtex->framebuffers_bound))
if (tex->dcc_offset &&
p_atomic_read(&tex->framebuffers_bound))
sctx->need_check_render_feedback = true;
si_update_bindless_texture_descriptor(sctx, tex_handle);
@ -2573,18 +2567,18 @@ static void si_make_image_handle_resident(struct pipe_context *ctx,
if (resident) {
if (res->b.b.target != PIPE_BUFFER) {
struct r600_texture *rtex = (struct r600_texture *)res;
struct si_texture *tex = (struct si_texture *)res;
unsigned level = view->u.tex.level;
if (color_needs_decompression(rtex)) {
if (color_needs_decompression(tex)) {
util_dynarray_append(
&sctx->resident_img_needs_color_decompress,
struct si_image_handle *,
img_handle);
}
if (vi_dcc_enabled(rtex, level) &&
p_atomic_read(&rtex->framebuffers_bound))
if (vi_dcc_enabled(tex, level) &&
p_atomic_read(&tex->framebuffers_bound))
sctx->need_check_render_feedback = true;
si_update_bindless_image_descriptor(sctx, img_handle);

78
src/gallium/drivers/radeonsi/si_dma.c
View file

@ -132,16 +132,16 @@ static void si_dma_copy_tile(struct si_context *ctx,
unsigned bpp)
{
struct radeon_cmdbuf *cs = ctx->dma_cs;
struct r600_texture *rsrc = (struct r600_texture*)src;
struct r600_texture *rdst = (struct r600_texture*)dst;
unsigned dst_mode = rdst->surface.u.legacy.level[dst_level].mode;
struct si_texture *ssrc = (struct si_texture*)src;
struct si_texture *sdst = (struct si_texture*)dst;
unsigned dst_mode = sdst->surface.u.legacy.level[dst_level].mode;
bool detile = dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED;
struct r600_texture *rlinear = detile ? rdst : rsrc;
struct r600_texture *rtiled = detile ? rsrc : rdst;
struct si_texture *linear = detile ? sdst : ssrc;
struct si_texture *tiled = detile ? ssrc : sdst;
unsigned linear_lvl = detile ? dst_level : src_level;
unsigned tiled_lvl = detile ? src_level : dst_level;
struct radeon_info *info = &ctx->screen->info;
unsigned index = rtiled->surface.u.legacy.tiling_index[tiled_lvl];
unsigned index = tiled->surface.u.legacy.tiling_index[tiled_lvl];
unsigned tile_mode = info->si_tile_mode_array[index];
unsigned array_mode, lbpp, pitch_tile_max, slice_tile_max, size;
unsigned ncopy, height, cheight, i;
@ -150,7 +150,7 @@ static void si_dma_copy_tile(struct si_context *ctx,
uint64_t base, addr;
unsigned pipe_config;
assert(dst_mode != rsrc->surface.u.legacy.level[src_level].mode);
assert(dst_mode != ssrc->surface.u.legacy.level[src_level].mode);
sub_cmd = SI_DMA_COPY_TILED;
lbpp = util_logbase2(bpp);
@ -163,35 +163,35 @@ static void si_dma_copy_tile(struct si_context *ctx,
tiled_y = detile ? src_y : dst_y;
tiled_z = detile ? src_z : dst_z;
assert(!util_format_is_depth_and_stencil(rtiled->buffer.b.b.format));
assert(!util_format_is_depth_and_stencil(tiled->buffer.b.b.format));
array_mode = G_009910_ARRAY_MODE(tile_mode);
slice_tile_max = (rtiled->surface.u.legacy.level[tiled_lvl].nblk_x *
rtiled->surface.u.legacy.level[tiled_lvl].nblk_y) / (8*8) - 1;
slice_tile_max = (tiled->surface.u.legacy.level[tiled_lvl].nblk_x *
tiled->surface.u.legacy.level[tiled_lvl].nblk_y) / (8*8) - 1;
/* linear height must be the same as the slice tile max height, it's ok even
* if the linear destination/source have smaller heigh as the size of the
* dma packet will be using the copy_height which is always smaller or equal
* to the linear height
*/
height = rtiled->surface.u.legacy.level[tiled_lvl].nblk_y;
base = rtiled->surface.u.legacy.level[tiled_lvl].offset;
addr = rlinear->surface.u.legacy.level[linear_lvl].offset;
addr += (uint64_t)rlinear->surface.u.legacy.level[linear_lvl].slice_size_dw * 4 * linear_z;
height = tiled->surface.u.legacy.level[tiled_lvl].nblk_y;
base = tiled->surface.u.legacy.level[tiled_lvl].offset;
addr = linear->surface.u.legacy.level[linear_lvl].offset;
addr += (uint64_t)linear->surface.u.legacy.level[linear_lvl].slice_size_dw * 4 * linear_z;
addr += linear_y * pitch + linear_x * bpp;
bank_h = G_009910_BANK_HEIGHT(tile_mode);
bank_w = G_009910_BANK_WIDTH(tile_mode);
mt_aspect = G_009910_MACRO_TILE_ASPECT(tile_mode);
/* Non-depth modes don't have TILE_SPLIT set. */
tile_split = util_logbase2(rtiled->surface.u.legacy.tile_split >> 6);
tile_split = util_logbase2(tiled->surface.u.legacy.tile_split >> 6);
nbanks = G_009910_NUM_BANKS(tile_mode);
base += rtiled->buffer.gpu_address;
addr += rlinear->buffer.gpu_address;
base += tiled->buffer.gpu_address;
addr += linear->buffer.gpu_address;
pipe_config = G_009910_PIPE_CONFIG(tile_mode);
mt = G_009910_MICRO_TILE_MODE(tile_mode);
size = copy_height * pitch;
ncopy = DIV_ROUND_UP(size, SI_DMA_COPY_MAX_DWORD_ALIGNED_SIZE);
si_need_dma_space(ctx, ncopy * 9, &rdst->buffer, &rsrc->buffer);
si_need_dma_space(ctx, ncopy * 9, &sdst->buffer, &ssrc->buffer);
for (i = 0; i < ncopy; i++) {
cheight = copy_height;
@ -225,8 +225,8 @@ static void si_dma_copy(struct pipe_context *ctx,
const struct pipe_box *src_box)
{
struct si_context *sctx = (struct si_context *)ctx;
struct r600_texture *rsrc = (struct r600_texture*)src;
struct r600_texture *rdst = (struct r600_texture*)dst;
struct si_texture *ssrc = (struct si_texture*)src;
struct si_texture *sdst = (struct si_texture*)dst;
unsigned dst_pitch, src_pitch, bpp, dst_mode, src_mode;
unsigned src_w, dst_w;
unsigned src_x, src_y;
@ -259,8 +259,8 @@ static void si_dma_copy(struct pipe_context *ctx,
goto fallback;
if (src_box->depth > 1 ||
!si_prepare_for_dma_blit(sctx, rdst, dst_level, dstx, dsty,
dstz, rsrc, src_level, src_box))
!si_prepare_for_dma_blit(sctx, sdst, dst_level, dstx, dsty,
dstz, ssrc, src_level, src_box))
goto fallback;
src_x = util_format_get_nblocksx(src->format, src_box->x);
@ -268,21 +268,21 @@ static void si_dma_copy(struct pipe_context *ctx,
src_y = util_format_get_nblocksy(src->format, src_box->y);
dst_y = util_format_get_nblocksy(src->format, dst_y);
bpp = rdst->surface.bpe;
dst_pitch = rdst->surface.u.legacy.level[dst_level].nblk_x * rdst->surface.bpe;
src_pitch = rsrc->surface.u.legacy.level[src_level].nblk_x * rsrc->surface.bpe;
src_w = u_minify(rsrc->buffer.b.b.width0, src_level);
dst_w = u_minify(rdst->buffer.b.b.width0, dst_level);
bpp = sdst->surface.bpe;
dst_pitch = sdst->surface.u.legacy.level[dst_level].nblk_x * sdst->surface.bpe;
src_pitch = ssrc->surface.u.legacy.level[src_level].nblk_x * ssrc->surface.bpe;
src_w = u_minify(ssrc->buffer.b.b.width0, src_level);
dst_w = u_minify(sdst->buffer.b.b.width0, dst_level);
dst_mode = rdst->surface.u.legacy.level[dst_level].mode;
src_mode = rsrc->surface.u.legacy.level[src_level].mode;
dst_mode = sdst->surface.u.legacy.level[dst_level].mode;
src_mode = ssrc->surface.u.legacy.level[src_level].mode;
if (src_pitch != dst_pitch || src_box->x || dst_x || src_w != dst_w ||
src_box->width != src_w ||
src_box->height != u_minify(rsrc->buffer.b.b.height0, src_level) ||
src_box->height != u_minify(rdst->buffer.b.b.height0, dst_level) ||
rsrc->surface.u.legacy.level[src_level].nblk_y !=
rdst->surface.u.legacy.level[dst_level].nblk_y) {
src_box->height != u_minify(ssrc->buffer.b.b.height0, src_level) ||
src_box->height != u_minify(sdst->buffer.b.b.height0, dst_level) ||
ssrc->surface.u.legacy.level[src_level].nblk_y !=
sdst->surface.u.legacy.level[dst_level].nblk_y) {
/* FIXME si can do partial blit */
goto fallback;
}
@ -301,18 +301,18 @@ static void si_dma_copy(struct pipe_context *ctx,
* dst_x/y == 0
* dst_pitch == src_pitch
*/
src_offset= rsrc->surface.u.legacy.level[src_level].offset;
src_offset += (uint64_t)rsrc->surface.u.legacy.level[src_level].slice_size_dw * 4 * src_box->z;
src_offset= ssrc->surface.u.legacy.level[src_level].offset;
src_offset += (uint64_t)ssrc->surface.u.legacy.level[src_level].slice_size_dw * 4 * src_box->z;
src_offset += src_y * src_pitch + src_x * bpp;
dst_offset = rdst->surface.u.legacy.level[dst_level].offset;
dst_offset += (uint64_t)rdst->surface.u.legacy.level[dst_level].slice_size_dw * 4 * dst_z;
dst_offset = sdst->surface.u.legacy.level[dst_level].offset;
dst_offset += (uint64_t)sdst->surface.u.legacy.level[dst_level].slice_size_dw * 4 * dst_z;
dst_offset += dst_y * dst_pitch + dst_x * bpp;
si_dma_copy_buffer(sctx, dst, src, dst_offset, src_offset,
(uint64_t)rsrc->surface.u.legacy.level[src_level].slice_size_dw * 4);
(uint64_t)ssrc->surface.u.legacy.level[src_level].slice_size_dw * 4);
} else {
si_dma_copy_tile(sctx, dst, dst_level, dst_x, dst_y, dst_z,
src, src_level, src_x, src_y, src_box->z,
src_box->height / rsrc->surface.blk_h,
src_box->height / ssrc->surface.blk_h,
dst_pitch, bpp);
}
return;

2
src/gallium/drivers/radeonsi/si_pipe.c
View file

@ -241,7 +241,7 @@ static void si_destroy_context(struct pipe_context *context)
sctx->b.destroy_query(&sctx->b,
sctx->dcc_stats[i].ps_stats[j]);
r600_texture_reference(&sctx->dcc_stats[i].tex, NULL);
si_texture_reference(&sctx->dcc_stats[i].tex, NULL);
}
if (sctx->query_result_shader)

58
src/gallium/drivers/radeonsi/si_pipe.h
View file

@ -238,12 +238,12 @@ struct r600_cmask_info {
uint64_t base_address_reg;
};
struct r600_texture {
struct si_texture {
struct r600_resource buffer;
struct radeon_surf surface;
uint64_t size;
struct r600_texture *flushed_depth_texture;
struct si_texture *flushed_depth_texture;
/* Colorbuffer compression and fast clear. */
uint64_t fmask_offset;
@ -1004,7 +1004,7 @@ struct si_context {
bool render_cond_force_off; /* for u_blitter */
/* Statistics gathering for the DCC enablement heuristic. It can't be
* in r600_texture because r600_texture can be shared by multiple
* in si_texture because si_texture can be shared by multiple
* contexts. This is for back buffers only. We shouldn't get too many
* of those.
*
@ -1013,7 +1013,7 @@ struct si_context {
* enabled by DCC stat gathering.
*/
struct {
struct r600_texture *tex;
struct si_texture *tex;
/* Query queue: 0 = usually active, 1 = waiting, 2 = readback. */
struct pipe_query *ps_stats[3];
/* If all slots are used and another slot is needed,
@ -1060,10 +1060,10 @@ void si_resource_copy_region(struct pipe_context *ctx,
struct pipe_resource *src,
unsigned src_level,
const struct pipe_box *src_box);
void si_decompress_dcc(struct si_context *sctx, struct r600_texture *rtex);
void si_decompress_dcc(struct si_context *sctx, struct si_texture *tex);
void si_blit_decompress_depth(struct pipe_context *ctx,
struct r600_texture *texture,
struct r600_texture *staging,
struct si_texture *texture,
struct si_texture *staging,
unsigned first_level, unsigned last_level,
unsigned first_layer, unsigned last_layer,
unsigned first_sample, unsigned last_sample);
@ -1096,7 +1096,7 @@ void si_init_buffer_functions(struct si_context *sctx);
enum pipe_format si_simplify_cb_format(enum pipe_format format);
bool vi_alpha_is_on_msb(enum pipe_format format);
void vi_dcc_clear_level(struct si_context *sctx,
struct r600_texture *rtex,
struct si_texture *tex,
unsigned level, unsigned clear_value);
void si_init_clear_functions(struct si_context *sctx);
@ -1218,26 +1218,26 @@ struct pipe_video_buffer *si_video_buffer_create(struct pipe_context *pipe,
void si_update_vs_viewport_state(struct si_context *ctx);
void si_init_viewport_functions(struct si_context *ctx);
/* r600_texture.c */
/* si_texture.c */
bool si_prepare_for_dma_blit(struct si_context *sctx,
struct r600_texture *rdst,
struct si_texture *dst,
unsigned dst_level, unsigned dstx,
unsigned dsty, unsigned dstz,
struct r600_texture *rsrc,
struct si_texture *src,
unsigned src_level,
const struct pipe_box *src_box);
void si_texture_get_cmask_info(struct si_screen *sscreen,
struct r600_texture *rtex,
struct si_texture *tex,
struct r600_cmask_info *out);
void si_eliminate_fast_color_clear(struct si_context *sctx,
struct r600_texture *rtex);
struct si_texture *tex);
void si_texture_discard_cmask(struct si_screen *sscreen,
struct r600_texture *rtex);
struct si_texture *tex);
bool si_init_flushed_depth_texture(struct pipe_context *ctx,
struct pipe_resource *texture,
struct r600_texture **staging);
struct si_texture **staging);
void si_print_texture_info(struct si_screen *sscreen,
struct r600_texture *rtex, struct u_log_context *log);
struct si_texture *tex, struct u_log_context *log);
struct pipe_resource *si_texture_create(struct pipe_screen *screen,
const struct pipe_resource *templ);
bool vi_dcc_formats_compatible(enum pipe_format format1,
@ -1256,15 +1256,15 @@ struct pipe_surface *si_create_surface_custom(struct pipe_context *pipe,
unsigned width, unsigned height);
unsigned si_translate_colorswap(enum pipe_format format, bool do_endian_swap);
void vi_separate_dcc_try_enable(struct si_context *sctx,
struct r600_texture *tex);
struct si_texture *tex);
void vi_separate_dcc_start_query(struct si_context *sctx,
struct r600_texture *tex);
struct si_texture *tex);
void vi_separate_dcc_stop_query(struct si_context *sctx,
struct r600_texture *tex);
struct si_texture *tex);
void vi_separate_dcc_process_and_reset_stats(struct pipe_context *ctx,
struct r600_texture *tex);
struct si_texture *tex);
bool si_texture_disable_dcc(struct si_context *sctx,
struct r600_texture *rtex);
struct si_texture *tex);
void si_init_screen_texture_functions(struct si_screen *sscreen);
void si_init_context_texture_functions(struct si_context *sctx);
@ -1286,24 +1286,24 @@ r600_resource_reference(struct r600_resource **ptr, struct r600_resource *res)
}
static inline void
r600_texture_reference(struct r600_texture **ptr, struct r600_texture *res)
si_texture_reference(struct si_texture **ptr, struct si_texture *res)
{
pipe_resource_reference((struct pipe_resource **)ptr, &res->buffer.b.b);
}
static inline bool
vi_dcc_enabled(struct r600_texture *tex, unsigned level)
vi_dcc_enabled(struct si_texture *tex, unsigned level)
{
return tex->dcc_offset && level < tex->surface.num_dcc_levels;
}
static inline unsigned
si_tile_mode_index(struct r600_texture *rtex, unsigned level, bool stencil)
si_tile_mode_index(struct si_texture *tex, unsigned level, bool stencil)
{
if (stencil)
return rtex->surface.u.legacy.stencil_tiling_index[level];
return tex->surface.u.legacy.stencil_tiling_index[level];
else
return rtex->surface.u.legacy.tiling_index[level];
return tex->surface.u.legacy.tiling_index[level];
}
static inline void
@ -1458,20 +1458,20 @@ si_make_DB_shader_coherent(struct si_context *sctx, unsigned num_samples,
}
static inline bool
si_can_sample_zs(struct r600_texture *tex, bool stencil_sampler)
si_can_sample_zs(struct si_texture *tex, bool stencil_sampler)
{
return (stencil_sampler && tex->can_sample_s) ||
(!stencil_sampler && tex->can_sample_z);
}
static inline bool
si_htile_enabled(struct r600_texture *tex, unsigned level)
si_htile_enabled(struct si_texture *tex, unsigned level)
{
return tex->htile_offset && level == 0;
}
static inline bool
vi_tc_compat_htile_enabled(struct r600_texture *tex, unsigned level)
vi_tc_compat_htile_enabled(struct si_texture *tex, unsigned level)
{
assert(!tex->tc_compatible_htile || tex->htile_offset);
return tex->tc_compatible_htile && level == 0;

242
src/gallium/drivers/radeonsi/si_state.c
View file

@ -1897,10 +1897,10 @@ static unsigned si_tex_compare(unsigned compare)
}
}
static unsigned si_tex_dim(struct si_screen *sscreen, struct r600_texture *rtex,
static unsigned si_tex_dim(struct si_screen *sscreen, struct si_texture *tex,
unsigned view_target, unsigned nr_samples)
{
unsigned res_target = rtex->buffer.b.b.target;
unsigned res_target = tex->buffer.b.b.target;
if (view_target == PIPE_TEXTURE_CUBE ||
view_target == PIPE_TEXTURE_CUBE_ARRAY)
@ -1914,7 +1914,7 @@ static unsigned si_tex_dim(struct si_screen *sscreen, struct r600_texture *rtex,
if ((res_target == PIPE_TEXTURE_1D ||
res_target == PIPE_TEXTURE_1D_ARRAY) &&
sscreen->info.chip_class >= GFX9 &&
rtex->surface.u.gfx9.resource_type == RADEON_RESOURCE_2D) {
tex->surface.u.gfx9.resource_type == RADEON_RESOURCE_2D) {
if (res_target == PIPE_TEXTURE_1D)
res_target = PIPE_TEXTURE_2D;
else
@ -2334,7 +2334,7 @@ static void si_choose_spi_color_formats(struct r600_surface *surf,
static void si_initialize_color_surface(struct si_context *sctx,
struct r600_surface *surf)
{
struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
struct si_texture *tex = (struct si_texture*)surf->base.texture;
unsigned color_info, color_attrib;
unsigned format, swap, ntype, endian;
const struct util_format_description *desc;
@ -2420,16 +2420,16 @@ static void si_initialize_color_surface(struct si_context *sctx,
color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == PIPE_SWIZZLE_1 ||
util_format_is_intensity(surf->base.format));
if (rtex->buffer.b.b.nr_samples > 1) {
unsigned log_samples = util_logbase2(rtex->buffer.b.b.nr_samples);
unsigned log_fragments = util_logbase2(rtex->num_color_samples);
if (tex->buffer.b.b.nr_samples > 1) {
unsigned log_samples = util_logbase2(tex->buffer.b.b.nr_samples);
unsigned log_fragments = util_logbase2(tex->num_color_samples);
color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
S_028C74_NUM_FRAGMENTS(log_fragments);
if (rtex->surface.fmask_size) {
if (tex->surface.fmask_size) {
color_info |= S_028C70_COMPRESSION(1);
unsigned fmask_bankh = util_logbase2(rtex->surface.u.legacy.fmask.bankh);
unsigned fmask_bankh = util_logbase2(tex->surface.u.legacy.fmask.bankh);
if (sctx->chip_class == SI) {
/* due to a hw bug, FMASK_BANK_HEIGHT must be set on SI too */
@ -2449,10 +2449,10 @@ static void si_initialize_color_surface(struct si_context *sctx,
if (!sctx->screen->info.has_dedicated_vram)
min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
if (rtex->num_color_samples > 1) {
if (rtex->surface.bpe == 1)
if (tex->num_color_samples > 1) {
if (tex->surface.bpe == 1)
max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
else if (rtex->surface.bpe == 2)
else if (tex->surface.bpe == 2)
max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
}
@ -2462,8 +2462,8 @@ static void si_initialize_color_surface(struct si_context *sctx,
}
/* This must be set for fast clear to work without FMASK. */
if (!rtex->surface.fmask_size && sctx->chip_class == SI) {
unsigned bankh = util_logbase2(rtex->surface.u.legacy.bankh);
if (!tex->surface.fmask_size && sctx->chip_class == SI) {
unsigned bankh = util_logbase2(tex->surface.u.legacy.bankh);
color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
}
@ -2471,14 +2471,14 @@ static void si_initialize_color_surface(struct si_context *sctx,
S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
if (sctx->chip_class >= GFX9) {
unsigned mip0_depth = util_max_layer(&rtex->buffer.b.b, 0);
unsigned mip0_depth = util_max_layer(&tex->buffer.b.b, 0);
color_view |= S_028C6C_MIP_LEVEL(surf->base.u.tex.level);
color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
S_028C74_RESOURCE_TYPE(rtex->surface.u.gfx9.resource_type);
S_028C74_RESOURCE_TYPE(tex->surface.u.gfx9.resource_type);
surf->cb_color_attrib2 = S_028C68_MIP0_WIDTH(surf->width0 - 1) |
S_028C68_MIP0_HEIGHT(surf->height0 - 1) |
S_028C68_MAX_MIP(rtex->buffer.b.b.last_level);
S_028C68_MAX_MIP(tex->buffer.b.b.last_level);
}
surf->cb_color_view = color_view;
@ -2486,7 +2486,7 @@ static void si_initialize_color_surface(struct si_context *sctx,
surf->cb_color_attrib = color_attrib;
/* Determine pixel shader export format */
si_choose_spi_color_formats(surf, format, swap, ntype, rtex->is_depth);
si_choose_spi_color_formats(surf, format, swap, ntype, tex->is_depth);
surf->color_initialized = true;
}
@ -2494,18 +2494,18 @@ static void si_initialize_color_surface(struct si_context *sctx,
static void si_init_depth_surface(struct si_context *sctx,
struct r600_surface *surf)
{
struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
struct si_texture *tex = (struct si_texture*)surf->base.texture;
unsigned level = surf->base.u.tex.level;
unsigned format, stencil_format;
uint32_t z_info, s_info;
format = si_translate_dbformat(rtex->db_render_format);
stencil_format = rtex->surface.has_stencil ?
format = si_translate_dbformat(tex->db_render_format);
stencil_format = tex->surface.has_stencil ?
V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
assert(format != V_028040_Z_INVALID);
if (format == V_028040_Z_INVALID)
PRINT_ERR("Invalid DB format: %d, disabling DB.\n", rtex->buffer.b.b.format);
PRINT_ERR("Invalid DB format: %d, disabling DB.\n", tex->buffer.b.b.format);
surf->db_depth_view = S_028008_SLICE_START(surf->base.u.tex.first_layer) |
S_028008_SLICE_MAX(surf->base.u.tex.last_layer);
@ -2513,31 +2513,31 @@ static void si_init_depth_surface(struct si_context *sctx,
surf->db_htile_surface = 0;
if (sctx->chip_class >= GFX9) {
assert(rtex->surface.u.gfx9.surf_offset == 0);
surf->db_depth_base = rtex->buffer.gpu_address >> 8;
surf->db_stencil_base = (rtex->buffer.gpu_address +
rtex->surface.u.gfx9.stencil_offset) >> 8;
assert(tex->surface.u.gfx9.surf_offset == 0);
surf->db_depth_base = tex->buffer.gpu_address >> 8;
surf->db_stencil_base = (tex->buffer.gpu_address +
tex->surface.u.gfx9.stencil_offset) >> 8;
z_info = S_028038_FORMAT(format) |
S_028038_NUM_SAMPLES(util_logbase2(rtex->buffer.b.b.nr_samples)) |
S_028038_SW_MODE(rtex->surface.u.gfx9.surf.swizzle_mode) |
S_028038_MAXMIP(rtex->buffer.b.b.last_level);
S_028038_NUM_SAMPLES(util_logbase2(tex->buffer.b.b.nr_samples)) |
S_028038_SW_MODE(tex->surface.u.gfx9.surf.swizzle_mode) |
S_028038_MAXMIP(tex->buffer.b.b.last_level);
s_info = S_02803C_FORMAT(stencil_format) |
S_02803C_SW_MODE(rtex->surface.u.gfx9.stencil.swizzle_mode);
surf->db_z_info2 = S_028068_EPITCH(rtex->surface.u.gfx9.surf.epitch);
surf->db_stencil_info2 = S_02806C_EPITCH(rtex->surface.u.gfx9.stencil.epitch);
S_02803C_SW_MODE(tex->surface.u.gfx9.stencil.swizzle_mode);
surf->db_z_info2 = S_028068_EPITCH(tex->surface.u.gfx9.surf.epitch);
surf->db_stencil_info2 = S_02806C_EPITCH(tex->surface.u.gfx9.stencil.epitch);
surf->db_depth_view |= S_028008_MIPID(level);
surf->db_depth_size = S_02801C_X_MAX(rtex->buffer.b.b.width0 - 1) |
S_02801C_Y_MAX(rtex->buffer.b.b.height0 - 1);
surf->db_depth_size = S_02801C_X_MAX(tex->buffer.b.b.width0 - 1) |
S_02801C_Y_MAX(tex->buffer.b.b.height0 - 1);
if (si_htile_enabled(rtex, level)) {
if (si_htile_enabled(tex, level)) {
z_info |= S_028038_TILE_SURFACE_ENABLE(1) |
S_028038_ALLOW_EXPCLEAR(1);
if (rtex->tc_compatible_htile) {
if (tex->tc_compatible_htile) {
unsigned max_zplanes = 4;
if (rtex->db_render_format == PIPE_FORMAT_Z16_UNORM &&
rtex->buffer.b.b.nr_samples > 1)
if (tex->db_render_format == PIPE_FORMAT_Z16_UNORM &&
tex->buffer.b.b.nr_samples > 1)
max_zplanes = 2;
z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes + 1) |
@ -2545,43 +2545,43 @@ static void si_init_depth_surface(struct si_context *sctx,
s_info |= S_02803C_ITERATE_FLUSH(1);
}
if (rtex->surface.has_stencil) {
if (tex->surface.has_stencil) {
/* Stencil buffer workaround ported from the SI-CI-VI code.
* See that for explanation.
*/
s_info |= S_02803C_ALLOW_EXPCLEAR(rtex->buffer.b.b.nr_samples <= 1);
s_info |= S_02803C_ALLOW_EXPCLEAR(tex->buffer.b.b.nr_samples <= 1);
} else {
/* Use all HTILE for depth if there's no stencil. */
s_info |= S_02803C_TILE_STENCIL_DISABLE(1);
}
surf->db_htile_data_base = (rtex->buffer.gpu_address +
rtex->htile_offset) >> 8;
surf->db_htile_data_base = (tex->buffer.gpu_address +
tex->htile_offset) >> 8;
surf->db_htile_surface = S_028ABC_FULL_CACHE(1) |
S_028ABC_PIPE_ALIGNED(rtex->surface.u.gfx9.htile.pipe_aligned) |
S_028ABC_RB_ALIGNED(rtex->surface.u.gfx9.htile.rb_aligned);
S_028ABC_PIPE_ALIGNED(tex->surface.u.gfx9.htile.pipe_aligned) |
S_028ABC_RB_ALIGNED(tex->surface.u.gfx9.htile.rb_aligned);
}
} else {
/* SI-CI-VI */
struct legacy_surf_level *levelinfo = &rtex->surface.u.legacy.level[level];
struct legacy_surf_level *levelinfo = &tex->surface.u.legacy.level[level];
assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
surf->db_depth_base = (rtex->buffer.gpu_address +
rtex->surface.u.legacy.level[level].offset) >> 8;
surf->db_stencil_base = (rtex->buffer.gpu_address +
rtex->surface.u.legacy.stencil_level[level].offset) >> 8;
surf->db_depth_base = (tex->buffer.gpu_address +
tex->surface.u.legacy.level[level].offset) >> 8;
surf->db_stencil_base = (tex->buffer.gpu_address +
tex->surface.u.legacy.stencil_level[level].offset) >> 8;
z_info = S_028040_FORMAT(format) |
S_028040_NUM_SAMPLES(util_logbase2(rtex->buffer.b.b.nr_samples));
S_028040_NUM_SAMPLES(util_logbase2(tex->buffer.b.b.nr_samples));
s_info = S_028044_FORMAT(stencil_format);
surf->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!rtex->tc_compatible_htile);
surf->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!tex->tc_compatible_htile);
if (sctx->chip_class >= CIK) {
struct radeon_info *info = &sctx->screen->info;
unsigned index = rtex->surface.u.legacy.tiling_index[level];
unsigned stencil_index = rtex->surface.u.legacy.stencil_tiling_index[level];
unsigned macro_index = rtex->surface.u.legacy.macro_tile_index;
unsigned index = tex->surface.u.legacy.tiling_index[level];
unsigned stencil_index = tex->surface.u.legacy.stencil_tiling_index[level];
unsigned macro_index = tex->surface.u.legacy.macro_tile_index;
unsigned tile_mode = info->si_tile_mode_array[index];
unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
@ -2596,9 +2596,9 @@ static void si_init_depth_surface(struct si_context *sctx,
z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
s_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
} else {
unsigned tile_mode_index = si_tile_mode_index(rtex, level, false);
unsigned tile_mode_index = si_tile_mode_index(tex, level, false);
z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
tile_mode_index = si_tile_mode_index(rtex, level, true);
tile_mode_index = si_tile_mode_index(tex, level, true);
s_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
}
@ -2607,11 +2607,11 @@ static void si_init_depth_surface(struct si_context *sctx,
surf->db_depth_slice = S_02805C_SLICE_TILE_MAX((levelinfo->nblk_x *
levelinfo->nblk_y) / 64 - 1);
if (si_htile_enabled(rtex, level)) {
if (si_htile_enabled(tex, level)) {
z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
S_028040_ALLOW_EXPCLEAR(1);
if (rtex->surface.has_stencil) {
if (tex->surface.has_stencil) {
/* Workaround: For a not yet understood reason, the
* combination of MSAA, fast stencil clear and stencil
* decompress messes with subsequent stencil buffer
@ -2623,9 +2623,9 @@ static void si_init_depth_surface(struct si_context *sctx,
* Check piglit's arb_texture_multisample-stencil-clear
* test if you want to try changing this.
*/
if (rtex->buffer.b.b.nr_samples <= 1)
if (tex->buffer.b.b.nr_samples <= 1)
s_info |= S_028044_ALLOW_EXPCLEAR(1);
} else if (!rtex->tc_compatible_htile) {
} else if (!tex->tc_compatible_htile) {
/* Use all of the htile_buffer for depth if there's no stencil.
* This must not be set when TC-compatible HTILE is enabled
* due to a hw bug.
@ -2633,17 +2633,17 @@ static void si_init_depth_surface(struct si_context *sctx,
s_info |= S_028044_TILE_STENCIL_DISABLE(1);
}
surf->db_htile_data_base = (rtex->buffer.gpu_address +
rtex->htile_offset) >> 8;
surf->db_htile_data_base = (tex->buffer.gpu_address +
tex->htile_offset) >> 8;
surf->db_htile_surface = S_028ABC_FULL_CACHE(1);
if (rtex->tc_compatible_htile) {
if (tex->tc_compatible_htile) {
surf->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
/* 0 = full compression. N = only compress up to N-1 Z planes. */
if (rtex->buffer.b.b.nr_samples <= 1)
if (tex->buffer.b.b.nr_samples <= 1)
z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(5);
else if (rtex->buffer.b.b.nr_samples <= 4)
else if (tex->buffer.b.b.nr_samples <= 4)
z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(3);
else
z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(2);
@ -2664,24 +2664,24 @@ void si_update_fb_dirtiness_after_rendering(struct si_context *sctx)
if (sctx->framebuffer.state.zsbuf) {
struct pipe_surface *surf = sctx->framebuffer.state.zsbuf;
struct r600_texture *rtex = (struct r600_texture *)surf->texture;
struct si_texture *tex = (struct si_texture *)surf->texture;
rtex->dirty_level_mask |= 1 << surf->u.tex.level;
tex->dirty_level_mask |= 1 << surf->u.tex.level;
if (rtex->surface.has_stencil)
rtex->stencil_dirty_level_mask |= 1 << surf->u.tex.level;
if (tex->surface.has_stencil)
tex->stencil_dirty_level_mask |= 1 << surf->u.tex.level;
}
unsigned compressed_cb_mask = sctx->framebuffer.compressed_cb_mask;
while (compressed_cb_mask) {
unsigned i = u_bit_scan(&compressed_cb_mask);
struct pipe_surface *surf = sctx->framebuffer.state.cbufs[i];
struct r600_texture *rtex = (struct r600_texture*)surf->texture;
struct si_texture *tex = (struct si_texture*)surf->texture;
if (rtex->surface.fmask_size)
rtex->dirty_level_mask |= 1 << surf->u.tex.level;
if (rtex->dcc_gather_statistics)
rtex->separate_dcc_dirty = true;
if (tex->surface.fmask_size)
tex->dirty_level_mask |= 1 << surf->u.tex.level;
if (tex->dcc_gather_statistics)
tex->separate_dcc_dirty = true;
}
}
@ -2689,14 +2689,14 @@ static void si_dec_framebuffer_counters(const struct pipe_framebuffer_state *sta
{
for (int i = 0; i < state->nr_cbufs; ++i) {
struct r600_surface *surf = NULL;
struct r600_texture *rtex;
struct si_texture *tex;
if (!state->cbufs[i])
continue;
surf = (struct r600_surface*)state->cbufs[i];
rtex = (struct r600_texture*)surf->base.texture;
tex = (struct si_texture*)surf->base.texture;
p_atomic_dec(&rtex->framebuffers_bound);
p_atomic_dec(&tex->framebuffers_bound);
}
}
@ -2706,14 +2706,14 @@ static void si_set_framebuffer_state(struct pipe_context *ctx,
struct si_context *sctx = (struct si_context *)ctx;
struct pipe_constant_buffer constbuf = {0};
struct r600_surface *surf = NULL;
struct r600_texture *rtex;
struct si_texture *tex;
bool old_any_dst_linear = sctx->framebuffer.any_dst_linear;
unsigned old_nr_samples = sctx->framebuffer.nr_samples;
unsigned old_colorbuf_enabled_4bit = sctx->framebuffer.colorbuf_enabled_4bit;
bool old_has_zsbuf = !!sctx->framebuffer.state.zsbuf;
bool old_has_stencil =
old_has_zsbuf &&
((struct r600_texture*)sctx->framebuffer.state.zsbuf->texture)->surface.has_stencil;
((struct si_texture*)sctx->framebuffer.state.zsbuf->texture)->surface.has_stencil;
bool unbound = false;
int i;
@ -2723,9 +2723,9 @@ static void si_set_framebuffer_state(struct pipe_context *ctx,
if (!sctx->framebuffer.state.cbufs[i])
continue;
rtex = (struct r600_texture*)sctx->framebuffer.state.cbufs[i]->texture;
if (rtex->dcc_gather_statistics)
vi_separate_dcc_stop_query(sctx, rtex);
tex = (struct si_texture*)sctx->framebuffer.state.cbufs[i]->texture;
if (tex->dcc_gather_statistics)
vi_separate_dcc_stop_query(sctx, tex);
}
/* Disable DCC if the formats are incompatible. */
@ -2734,7 +2734,7 @@ static void si_set_framebuffer_state(struct pipe_context *ctx,
continue;
surf = (struct r600_surface*)state->cbufs[i];
rtex = (struct r600_texture*)surf->base.texture;
tex = (struct si_texture*)surf->base.texture;
if (!surf->dcc_incompatible)
continue;
@ -2749,9 +2749,9 @@ static void si_set_framebuffer_state(struct pipe_context *ctx,
unbound = true;
}
if (vi_dcc_enabled(rtex, surf->base.u.tex.level))
if (!si_texture_disable_dcc(sctx, rtex))
si_decompress_dcc(sctx, rtex);
if (vi_dcc_enabled(tex, surf->base.u.tex.level))
if (!si_texture_disable_dcc(sctx, tex))
si_decompress_dcc(sctx, tex);
surf->dcc_incompatible = false;
}
@ -2830,7 +2830,7 @@ static void si_set_framebuffer_state(struct pipe_context *ctx,
continue;
surf = (struct r600_surface*)state->cbufs[i];
rtex = (struct r600_texture*)surf->base.texture;
tex = (struct si_texture*)surf->base.texture;
if (!surf->color_initialized) {
si_initialize_color_surface(sctx, surf);
@ -2851,7 +2851,7 @@ static void si_set_framebuffer_state(struct pipe_context *ctx,
if (surf->color_is_int10)
sctx->framebuffer.color_is_int10 |= 1 << i;
if (rtex->surface.fmask_size)
if (tex->surface.fmask_size)
sctx->framebuffer.compressed_cb_mask |= 1 << i;
else
sctx->framebuffer.uncompressed_cb_mask |= 1 << i;
@ -2859,35 +2859,35 @@ static void si_set_framebuffer_state(struct pipe_context *ctx,
/* Don't update nr_color_samples for non-AA buffers.
* (e.g. destination of MSAA resolve)
*/
if (rtex->buffer.b.b.nr_samples >= 2 &&
rtex->num_color_samples < rtex->buffer.b.b.nr_samples) {
if (tex->buffer.b.b.nr_samples >= 2 &&
tex->num_color_samples < tex->buffer.b.b.nr_samples) {
sctx->framebuffer.nr_color_samples =
MIN2(sctx->framebuffer.nr_color_samples,
rtex->num_color_samples);
tex->num_color_samples);
}
if (rtex->surface.is_linear)
if (tex->surface.is_linear)
sctx->framebuffer.any_dst_linear = true;
if (vi_dcc_enabled(rtex, surf->base.u.tex.level))
if (vi_dcc_enabled(tex, surf->base.u.tex.level))
sctx->framebuffer.CB_has_shader_readable_metadata = true;
si_context_add_resource_size(sctx, surf->base.texture);
p_atomic_inc(&rtex->framebuffers_bound);
p_atomic_inc(&tex->framebuffers_bound);
if (rtex->dcc_gather_statistics) {
if (tex->dcc_gather_statistics) {
/* Dirty tracking must be enabled for DCC usage analysis. */
sctx->framebuffer.compressed_cb_mask |= 1 << i;
vi_separate_dcc_start_query(sctx, rtex);
vi_separate_dcc_start_query(sctx, tex);
}
}
struct r600_texture *zstex = NULL;
struct si_texture *zstex = NULL;
if (state->zsbuf) {
surf = (struct r600_surface*)state->zsbuf;
zstex = (struct r600_texture*)surf->base.texture;
zstex = (struct si_texture*)surf->base.texture;
if (!surf->depth_initialized) {
si_init_depth_surface(sctx, surf);
@ -2963,7 +2963,7 @@ static void si_emit_framebuffer_state(struct si_context *sctx)
struct radeon_cmdbuf *cs = sctx->gfx_cs;
struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
unsigned i, nr_cbufs = state->nr_cbufs;
struct r600_texture *tex = NULL;
struct si_texture *tex = NULL;
struct r600_surface *cb = NULL;
unsigned cb_color_info = 0;
@ -2982,7 +2982,7 @@ static void si_emit_framebuffer_state(struct si_context *sctx)
continue;
}
tex = (struct r600_texture *)cb->base.texture;
tex = (struct si_texture *)cb->base.texture;
radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
&tex->buffer, RADEON_USAGE_READWRITE,
tex->buffer.b.b.nr_samples > 1 ?
@ -3139,10 +3139,10 @@ static void si_emit_framebuffer_state(struct si_context *sctx)
/* ZS buffer. */
if (state->zsbuf && sctx->framebuffer.dirty_zsbuf) {
struct r600_surface *zb = (struct r600_surface*)state->zsbuf;
struct r600_texture *rtex = (struct r600_texture*)zb->base.texture;
struct si_texture *tex = (struct si_texture*)zb->base.texture;
radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
&rtex->buffer, RADEON_USAGE_READWRITE,
&tex->buffer, RADEON_USAGE_READWRITE,
zb->base.texture->nr_samples > 1 ?
RADEON_PRIO_DEPTH_BUFFER_MSAA :
RADEON_PRIO_DEPTH_BUFFER);
@ -3155,7 +3155,7 @@ static void si_emit_framebuffer_state(struct si_context *sctx)
radeon_set_context_reg_seq(cs, R_028038_DB_Z_INFO, 10);
radeon_emit(cs, zb->db_z_info | /* DB_Z_INFO */
S_028038_ZRANGE_PRECISION(rtex->depth_clear_value != 0));
S_028038_ZRANGE_PRECISION(tex->depth_clear_value != 0));
radeon_emit(cs, zb->db_stencil_info); /* DB_STENCIL_INFO */
radeon_emit(cs, zb->db_depth_base); /* DB_Z_READ_BASE */
radeon_emit(cs, S_028044_BASE_HI(zb->db_depth_base >> 32)); /* DB_Z_READ_BASE_HI */
@ -3175,7 +3175,7 @@ static void si_emit_framebuffer_state(struct si_context *sctx)
radeon_set_context_reg_seq(cs, R_02803C_DB_DEPTH_INFO, 9);
radeon_emit(cs, zb->db_depth_info); /* DB_DEPTH_INFO */
radeon_emit(cs, zb->db_z_info | /* DB_Z_INFO */
S_028040_ZRANGE_PRECISION(rtex->depth_clear_value != 0));
S_028040_ZRANGE_PRECISION(tex->depth_clear_value != 0));
radeon_emit(cs, zb->db_stencil_info); /* DB_STENCIL_INFO */
radeon_emit(cs, zb->db_depth_base); /* DB_Z_READ_BASE */
radeon_emit(cs, zb->db_stencil_base); /* DB_STENCIL_READ_BASE */
@ -3186,8 +3186,8 @@ static void si_emit_framebuffer_state(struct si_context *sctx)
}
radeon_set_context_reg_seq(cs, R_028028_DB_STENCIL_CLEAR, 2);
radeon_emit(cs, rtex->stencil_clear_value); /* R_028028_DB_STENCIL_CLEAR */
radeon_emit(cs, fui(rtex->depth_clear_value)); /* R_02802C_DB_DEPTH_CLEAR */
radeon_emit(cs, tex->stencil_clear_value); /* R_028028_DB_STENCIL_CLEAR */
radeon_emit(cs, fui(tex->depth_clear_value)); /* R_02802C_DB_DEPTH_CLEAR */
radeon_set_context_reg(cs, R_028008_DB_DEPTH_VIEW, zb->db_depth_view);
radeon_set_context_reg(cs, R_028ABC_DB_HTILE_SURFACE, zb->db_htile_surface);
@ -3286,8 +3286,8 @@ static bool si_out_of_order_rasterization(struct si_context *sctx)
};
if (sctx->framebuffer.state.zsbuf) {
struct r600_texture *zstex =
(struct r600_texture*)sctx->framebuffer.state.zsbuf->texture;
struct si_texture *zstex =
(struct si_texture*)sctx->framebuffer.state.zsbuf->texture;
bool has_stencil = zstex->surface.has_stencil;
dsa_order_invariant = dsa->order_invariance[has_stencil];
if (!dsa_order_invariant.zs)
@ -3603,7 +3603,7 @@ static unsigned gfx9_border_color_swizzle(const unsigned char swizzle[4])
*/
void
si_make_texture_descriptor(struct si_screen *screen,
struct r600_texture *tex,
struct si_texture *tex,
bool sampler,
enum pipe_texture_target target,
enum pipe_format pipe_format,
@ -3966,7 +3966,7 @@ si_create_sampler_view_custom(struct pipe_context *ctx,
{
struct si_context *sctx = (struct si_context*)ctx;
struct si_sampler_view *view = CALLOC_STRUCT(si_sampler_view);
struct r600_texture *tmp = (struct r600_texture*)texture;
struct si_texture *tex = (struct si_texture*)texture;
unsigned base_level, first_level, last_level;
unsigned char state_swizzle[4];
unsigned height, depth, width;
@ -4037,30 +4037,30 @@ si_create_sampler_view_custom(struct pipe_context *ctx,
pipe_format = state->format;
/* Depth/stencil texturing sometimes needs separate texture. */
if (tmp->is_depth && !si_can_sample_zs(tmp, view->is_stencil_sampler)) {
if (!tmp->flushed_depth_texture &&
if (tex->is_depth && !si_can_sample_zs(tex, view->is_stencil_sampler)) {
if (!tex->flushed_depth_texture &&
!si_init_flushed_depth_texture(ctx, texture, NULL)) {
pipe_resource_reference(&view->base.texture, NULL);
FREE(view);
return NULL;
}
assert(tmp->flushed_depth_texture);
assert(tex->flushed_depth_texture);
/* Override format for the case where the flushed texture
* contains only Z or only S.
*/
if (tmp->flushed_depth_texture->buffer.b.b.format != tmp->buffer.b.b.format)
pipe_format = tmp->flushed_depth_texture->buffer.b.b.format;
if (tex->flushed_depth_texture->buffer.b.b.format != tex->buffer.b.b.format)
pipe_format = tex->flushed_depth_texture->buffer.b.b.format;
tmp = tmp->flushed_depth_texture;
tex = tex->flushed_depth_texture;
}
surflevel = tmp->surface.u.legacy.level;
surflevel = tex->surface.u.legacy.level;
if (tmp->db_compatible) {
if (tex->db_compatible) {
if (!view->is_stencil_sampler)
pipe_format = tmp->db_render_format;
pipe_format = tex->db_render_format;
switch (pipe_format) {
case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
@ -4077,7 +4077,7 @@ si_create_sampler_view_custom(struct pipe_context *ctx,
case PIPE_FORMAT_S8X24_UINT:
case PIPE_FORMAT_X32_S8X24_UINT:
pipe_format = PIPE_FORMAT_S8_UINT;
surflevel = tmp->surface.u.legacy.stencil_level;
surflevel = tex->surface.u.legacy.stencil_level;
break;
default:;
}
@ -4088,7 +4088,7 @@ si_create_sampler_view_custom(struct pipe_context *ctx,
state->u.tex.first_level,
state->format);
si_make_texture_descriptor(sctx->screen, tmp, true,
si_make_texture_descriptor(sctx->screen, tex, true,
state->target, pipe_format, state_swizzle,
first_level, last_level,
state->u.tex.first_layer, last_layer,

6
src/gallium/drivers/radeonsi/si_state.h
View file

@ -42,7 +42,7 @@
struct si_screen;
struct si_shader;
struct si_shader_selector;
struct r600_texture;
struct si_texture;
struct si_qbo_state;
/* State atoms are callbacks which write a sequence of packets into a GPU
@ -407,7 +407,7 @@ struct si_buffer_resources {
/* si_descriptors.c */
void si_set_mutable_tex_desc_fields(struct si_screen *sscreen,
struct r600_texture *tex,
struct si_texture *tex,
const struct legacy_surf_level *base_level_info,
unsigned base_level, unsigned first_level,
unsigned block_width, bool is_stencil,
@ -462,7 +462,7 @@ si_make_buffer_descriptor(struct si_screen *screen, struct r600_resource *buf,
uint32_t *state);
void
si_make_texture_descriptor(struct si_screen *screen,
struct r600_texture *tex,
struct si_texture *tex,
bool sampler,
enum pipe_texture_target target,
enum pipe_format pipe_format,

14
src/gallium/drivers/radeonsi/si_state_binning.c
View file

@ -74,9 +74,9 @@ static struct uvec2 si_get_color_bin_size(struct si_context *sctx,
if (!(cb_target_enabled_4bit & (0xf << (i * 4))))
continue;
struct r600_texture *rtex =
(struct r600_texture*)sctx->framebuffer.state.cbufs[i]->texture;
sum += rtex->surface.bpe;
struct si_texture *tex =
(struct si_texture*)sctx->framebuffer.state.cbufs[i]->texture;
sum += tex->surface.bpe;
}
/* Multiply the sum by some function of the number of samples. */
@ -190,13 +190,13 @@ static struct uvec2 si_get_depth_bin_size(struct si_context *sctx)
return size;
}
struct r600_texture *rtex =
(struct r600_texture*)sctx->framebuffer.state.zsbuf->texture;
struct si_texture *tex =
(struct si_texture*)sctx->framebuffer.state.zsbuf->texture;
unsigned depth_coeff = dsa->depth_enabled ? 5 : 0;
unsigned stencil_coeff = rtex->surface.has_stencil &&
unsigned stencil_coeff = tex->surface.has_stencil &&
dsa->stencil_enabled ? 1 : 0;
unsigned sum = 4 * (depth_coeff + stencil_coeff) *
rtex->buffer.b.b.nr_samples;
tex->buffer.b.b.nr_samples;
static const si_bin_size_subtable table[] = {
{

22
src/gallium/drivers/radeonsi/si_test_dma.c
View file

@ -220,8 +220,8 @@ void si_test_dma(struct si_screen *sscreen)
*/
for (i = 0; i < iterations; i++) {
struct pipe_resource tsrc = {}, tdst = {}, *src, *dst;
struct r600_texture *rdst;
struct r600_texture *rsrc;
struct si_texture *sdst;
struct si_texture *ssrc;
struct cpu_texture src_cpu, dst_cpu;
unsigned bpp, max_width, max_height, max_depth, j, num;
unsigned gfx_blits = 0, dma_blits = 0, max_tex_side_gen;
@ -290,24 +290,24 @@ void si_test_dma(struct si_screen *sscreen)
dst = screen->resource_create(screen, &tdst);
assert(src);
assert(dst);
rdst = (struct r600_texture*)dst;
rsrc = (struct r600_texture*)src;
sdst = (struct si_texture*)dst;
ssrc = (struct si_texture*)src;
alloc_cpu_texture(&src_cpu, &tsrc, bpp);
alloc_cpu_texture(&dst_cpu, &tdst, bpp);
printf("%4u: dst = (%5u x %5u x %u, %s), "
" src = (%5u x %5u x %u, %s), bpp = %2u, ",
i, tdst.width0, tdst.height0, tdst.array_size,
array_mode_to_string(sscreen, &rdst->surface),
array_mode_to_string(sscreen, &sdst->surface),
tsrc.width0, tsrc.height0, tsrc.array_size,
array_mode_to_string(sscreen, &rsrc->surface), bpp);
array_mode_to_string(sscreen, &ssrc->surface), bpp);
fflush(stdout);
/* set src pixels */
set_random_pixels(ctx, src, &src_cpu);
/* clear dst pixels */
si_clear_buffer(sctx, dst, 0, rdst->surface.surf_size, 0, true);
si_clear_buffer(sctx, dst, 0, sdst->surface.surf_size, 0, true);
memset(dst_cpu.ptr, 0, dst_cpu.layer_stride * tdst.array_size);
/* preparation */
@ -337,8 +337,8 @@ void si_test_dma(struct si_screen *sscreen)
dstz = rand() % (tdst.array_size - depth + 1);
/* special code path to hit the tiled partial copies */
if (!rsrc->surface.is_linear &&
!rdst->surface.is_linear &&
if (!ssrc->surface.is_linear &&
!sdst->surface.is_linear &&
rand() & 1) {
if (max_width < 8 || max_height < 8)
continue;
@ -365,8 +365,8 @@ void si_test_dma(struct si_screen *sscreen)
}
/* special code path to hit out-of-bounds reads in L2T */
if (rsrc->surface.is_linear &&
!rdst->surface.is_linear &&
if (ssrc->surface.is_linear &&
!sdst->surface.is_linear &&
rand() % 4 == 0) {
srcx = 0;
srcy = 0;

768
src/gallium/drivers/radeonsi/si_texture.c
View file

File diff suppressed because it is too large Load diff

14
src/gallium/drivers/radeonsi/si_uvd.c
View file

@ -41,7 +41,7 @@ struct pipe_video_buffer *si_video_buffer_create(struct pipe_context *pipe,
const struct pipe_video_buffer *tmpl)
{
struct si_context *ctx = (struct si_context *)pipe;
struct r600_texture *resources[VL_NUM_COMPONENTS] = {};
struct si_texture *resources[VL_NUM_COMPONENTS] = {};
struct radeon_surf *surfaces[VL_NUM_COMPONENTS] = {};
struct pb_buffer **pbs[VL_NUM_COMPONENTS] = {};
const enum pipe_format *resource_formats;
@ -68,11 +68,11 @@ struct pipe_video_buffer *si_video_buffer_create(struct pipe_context *pipe,
vl_video_buffer_template(&templ, &vidtemplate,
resource_formats[i], 1,
array_size, PIPE_USAGE_DEFAULT, i);
/* Set PIPE_BIND_SHARED to avoid reallocation in r600_texture_get_handle,
/* Set PIPE_BIND_SHARED to avoid reallocation in si_texture_get_handle,
* which can't handle joined surfaces. */
/* TODO: get tiling working */
templ.bind = PIPE_BIND_LINEAR | PIPE_BIND_SHARED;
resources[i] = (struct r600_texture *)
resources[i] = (struct si_texture *)
pipe->screen->resource_create(pipe->screen, &templ);
if (!resources[i])
goto error;
@ -103,7 +103,7 @@ struct pipe_video_buffer *si_video_buffer_create(struct pipe_context *pipe,
error:
for (i = 0; i < VL_NUM_COMPONENTS; ++i)
r600_texture_reference(&resources[i], NULL);
si_texture_reference(&resources[i], NULL);
return NULL;
}
@ -112,8 +112,8 @@ error:
static struct pb_buffer* si_uvd_set_dtb(struct ruvd_msg *msg, struct vl_video_buffer *buf)
{
struct si_screen *sscreen = (struct si_screen*)buf->base.context->screen;
struct r600_texture *luma = (struct r600_texture *)buf->resources[0];
struct r600_texture *chroma = (struct r600_texture *)buf->resources[1];
struct si_texture *luma = (struct si_texture *)buf->resources[0];
struct si_texture *chroma = (struct si_texture *)buf->resources[1];
enum ruvd_surface_type type = (sscreen->info.chip_class >= GFX9) ?
RUVD_SURFACE_TYPE_GFX9 :
RUVD_SURFACE_TYPE_LEGACY;
@ -130,7 +130,7 @@ static void si_vce_get_buffer(struct pipe_resource *resource,
struct pb_buffer **handle,
struct radeon_surf **surface)
{
struct r600_texture *res = (struct r600_texture *)resource;
struct si_texture *res = (struct si_texture *)resource;
if (handle)
*handle = res->buffer.buf;