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ac/gpu_info: add htile_cmask_support_1d_tiling

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Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
This commit is contained in:
Marek Olšák 2018-05-02 18:35:27 -04:00
parent b81149e258
commit 8b58a14ef7
5 changed files with 10 additions and 9 deletions
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2
src/amd/common/ac_gpu_info.c
View file

@ -317,6 +317,7 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
info->has_local_buffers = info->drm_minor >= 20 &&
!info->has_dedicated_vram;
info->kernel_flushes_hdp_before_ib = true;
info->htile_cmask_support_1d_tiling = true;
info->num_render_backends = amdinfo->rb_pipes;
/* The value returned by the kernel driver was wrong. */
@ -465,6 +466,7 @@ void ac_print_gpu_info(struct radeon_info *info)
printf(" has_ctx_priority = %u\n", info->has_ctx_priority);
printf(" has_local_buffers = %u\n", info->has_local_buffers);
printf(" kernel_flushes_hdp_before_ib = %u\n", info->kernel_flushes_hdp_before_ib);
printf(" htile_cmask_support_1d_tiling = %u\n", info->htile_cmask_support_1d_tiling);
printf("Shader core info:\n");
printf(" max_shader_clock = %i\n", info->max_shader_clock);

1
src/amd/common/ac_gpu_info.h
View file

@ -97,6 +97,7 @@ struct radeon_info {
bool has_ctx_priority;
bool has_local_buffers;
bool kernel_flushes_hdp_before_ib;
bool htile_cmask_support_1d_tiling;
/* Shader cores. */
uint32_t r600_max_quad_pipes; /* wave size / 16 */

7
src/gallium/drivers/radeonsi/si_clear.c
View file

@ -437,13 +437,10 @@ static void si_do_fast_color_clear(struct si_context *sctx,
!(tex->buffer.external_usage & PIPE_HANDLE_USAGE_EXPLICIT_FLUSH))
continue;
/* fast color clear with 1D tiling doesn't work on old kernels and CIK */
if (sctx->chip_class == CIK &&
if (sctx->chip_class <= VI &&
tex->surface.u.legacy.level[0].mode == RADEON_SURF_MODE_1D &&
sctx->screen->info.drm_major == 2 &&
sctx->screen->info.drm_minor < 38) {
!sctx->screen->info.htile_cmask_support_1d_tiling)
continue;
}
/* Fast clear is the most appropriate place to enable DCC for
* displayable surfaces.

6
src/gallium/drivers/radeonsi/si_texture.c
View file

@ -922,10 +922,8 @@ static void si_texture_get_htile_size(struct si_screen *sscreen,
rtex->surface.htile_size = 0;
/* HTILE is broken with 1D tiling on old kernels and CIK. */
if (sscreen->info.chip_class >= CIK &&
rtex->surface.u.legacy.level[0].mode == RADEON_SURF_MODE_1D &&
sscreen->info.drm_major == 2 && sscreen->info.drm_minor < 38)
if (rtex->surface.u.legacy.level[0].mode == RADEON_SURF_MODE_1D &&
!sscreen->info.htile_cmask_support_1d_tiling)
return;
/* Overalign HTILE on P2 configs to work around GPU hangs in

3
src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
View file

@ -529,6 +529,9 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws)
ws->info.tcc_cache_line_size = 64; /* TC L2 line size on GCN */
ws->info.ib_start_alignment = 4096;
ws->info.kernel_flushes_hdp_before_ib = ws->info.drm_minor >= 40;
/* HTILE is broken with 1D tiling on old kernels and CIK. */
ws->info.htile_cmask_support_1d_tiling = ws->info.chip_class != CIK ||
ws->info.drm_minor >= 38;
ws->check_vm = strstr(debug_get_option("R600_DEBUG", ""), "check_vm") != NULL;