Commit graph

184774 commits

Author SHA1 Message Date
Aditya Swarup
a648ee7a70 intel/isl: Convert linear texture to Tile4 format
Add memcpy function to convert linear data to Tile 4 format.
Tile 4 format consists of 4KB block divided into chunks of 512B.
Each 512B chunk/block is comprised of 8 64B blocks arranged in
Y-tile format.

Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13391>
2023-09-02 21:49:05 -07:00
Aditya Swarup
d16eac17d8 intel/isl: Unittest for linear to Ytile conversion
Add unittests for linear to tiled and tiled to linear texture
conversions for Ytile. The test prints the source/output buffer
in hex format with debug flags to verify the result.

Linear to tile conversion fills the linear buffer with values
based on the OWORD index number i.e., OWORD3 will contain
all values filled as 0x03 and
OWORD3 = 0x03030303030303030303030303030303.

The Y-tile to Linear tile conversion uses a similar logic to place
the tiled values in a manner that will result in a linear buffer with
OWORDs filled according to index number as mentioned above.

Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13391>
2023-09-02 21:49:03 -07:00
Rohan Garg
ca7ae1a53f blorp: drop undefined macro
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 97d6ceaf04 ("intel: Remove GEN_IS_HASWELL macro")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25011>
2023-09-03 03:04:26 +00:00
Rohan Garg
99a88ca4a2 crocus: fix GFX_VERx10 macro
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25011>
2023-09-03 03:04:26 +00:00
Rohan Garg
802043018e crocus: add a __gen_get_batch_address declaration
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25011>
2023-09-03 03:04:26 +00:00
Rohan Garg
86e8ba4d32 anv: use the lineage number for WA
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: d0669f3ede ("intel/dev: switch defect identifiers to use lineage numbers")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25011>
2023-09-03 03:04:26 +00:00
Rohan Garg
50c2fe46fa iris: use the correct WA macros and lineage numbers
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 0ce595a89a ("intel: use generated helpers for Wa_1508744258")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25011>
2023-09-03 03:04:26 +00:00
Rohan Garg
cbc4916661 anv: drop dead ifdef
The GFX_VERX10 macro doesn't exist and we no longer use
SCRATCH_SURFACE_STATE_POOL_SIZE.

Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: b3f6e5dc70 ('anv: remove incorrect ifdef')
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25011>
2023-09-03 03:04:26 +00:00
Matt Turner
c38b67f4d1 intel: Limit Intel Vulkan RT to x86_64
Note: passed CI repeatedly except for the timing out WHL jobs.

Fixes: 28c1053c07 ("intel: Allow using intel_clc from the system")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25009>
2023-09-02 15:43:18 -04:00
Alyssa Rosenzweig
fd114ab706 ci: Disable WHL jobs
Timing out all day.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2023-09-02 15:43:01 -04:00
Alyssa Rosenzweig
3e457c6b7e ci: Disable known broken Bifrost Vulkan job
Until someone does the work to eliminate faults, PanVK will be inherently flaky
and should not be in CI. deqp-runner can eat a lot of flakes, and then retrying
the whole job eats more flakes, but neither is a substitute for not testing
known broken (and hence flaky) code and both increase runtime unacceptably. the
g52-vk job earned 2 spots on the latest leaderboard for slowest jobs, I clicked
on https://gitlab.freedesktop.org/mesa/mesa/-/jobs/48142375 to see a jawdropping
54 flakes reported by deqp-runner.

If people insist on keeping the job, then panfrost-g52-vk needs to be demoted to
manual until after someone fixes all these bugs on the driver side. If that's
not going to happen, then there's no point in it being in CI at all. It's broken
code. After a buggy MR, it'll still be broken code. CI doesn't matter if we're
ok with it being broken.

Bottom line is, we can't be running known broken code in CI (bugs = faults =
flakes = unhappy developers), at least for non-robust stacks (panfrost.ko
included). This needs to be policy if it isn't already. Merging this single
character change deals with the hot problem without any fanfare or adverse
effects.

This turns the job into a nightly as David suggested to get it out of the
premerge path until someone is committed to supporting it and does the work to
make it happen.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9721
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24943>
2023-09-02 13:32:17 +00:00
Georg Lehmann
2ae94b3894 aco: implement some exclusive scans with inclusive scans
exclusive scan lowering uses full wave shift, for iadd/ixor it's faster
to do inclusive scans and subtract/xor the thread's source.

Foz-DB Navi21:
Totals from 21 (0.02% of 132657) affected shaders:
Instrs: 10925 -> 10727 (-1.81%)
CodeSize: 58064 -> 56488 (-2.71%)
Latency: 178471 -> 177928 (-0.30%)
InvThroughput: 24374 -> 24145 (-0.94%)

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24555>
2023-09-02 11:42:22 +00:00
Karol Herbst
f90f68aa1c rusticl/memory: only specify PIPE_BIND_SHADER_IMAGE where supported
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24982>
2023-09-02 10:11:24 +00:00
Georg Lehmann
3a715cc9d2 nir: add nir_scalar_equal
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24656>
2023-09-02 00:26:31 +00:00
Georg Lehmann
bce9bba90d nir: add nir_scalar intrinsic helpers
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24656>
2023-09-02 00:26:31 +00:00
David Heidelberg
1ae3c40732 docs: add LAVA farm informations
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24959>
2023-09-01 23:58:51 +00:00
David Heidelberg
1a990e21c8 Revert "ci: disable a660 jobs"
This reverts commit 209ed8eace.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24959>
2023-09-01 23:58:51 +00:00
Lionel Landwerlin
4066f05fe4 anv: enable standard Y tiles
We kept those tilings disabled up to know. Now that ISL has proper
support for them, remove this.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
2023-09-01 23:22:18 +00:00
Jason Ekstrand
db4488a2dc anv: Align memory VA to support for Ys, Tile64 tiled images
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
2023-09-01 23:22:18 +00:00
Aditya Swarup
e03f3b646c isl: enable Tile64 for 3D images
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
2023-09-01 23:22:18 +00:00
Jason Ekstrand
e956f6ad30 intel/isl: Allow Ys tiling
Ys & Yf are both implemented in ISL now, we still have some Yf issues
to investigate. Instead of disabling them in ISL, we disable them in
the two drivers.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
2023-09-01 23:22:18 +00:00
Lionel Landwerlin
4ac46dbb46 isl: reorder tiling selection
Select tilings in this order :
  - recommended Y tilings
  - Yf tilings
  - Ys/Tile64 tilings
  - legacy tilings (W, X) & Linear

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
2023-09-01 23:22:18 +00:00
Lionel Landwerlin
af559c48d3 intel/aux_map: correctly program tiling mode for Ys
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
2023-09-01 23:22:18 +00:00
Lionel Landwerlin
3c6d003d9f blorp: allow 3D blits/copies on Ys/Yf/Tile64 tiling
The data in Ys/Yf/Tile64 tiled images is arranged differently for 2D &
3D images. Therefore we cannot assume that we will use 2D images for
blits/copies.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
2023-09-01 23:22:18 +00:00
Lionel Landwerlin
e182f5770d isl: disable CCS on Ys/Yf
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
2023-09-01 23:22:18 +00:00
Lionel Landwerlin
4e36aa507e isl: disable miptails on gfx12 with yuv formats
A number of CTS tests are failing, like :

   dEQP-VK.ycbcr.format.b8g8r8g8_422_unorm.vertex_optimal

Failures are reproduced on simulation.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
2023-09-01 23:22:18 +00:00
Lionel Landwerlin
aa31683dde isl: disallow miptails on planar formats
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
2023-09-01 23:22:18 +00:00
Lionel Landwerlin
7ee41c162d isl: add Gfx12/12.5 restriction on 3D surfaces & compression
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
2023-09-01 23:22:18 +00:00
Jason Ekstrand
63c86a95b2 intel/isl: Disallow CCS on 3D surfaces with miptails
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
2023-09-01 23:22:18 +00:00
Jason Ekstrand
46f45d62d1 intel/isl: Start using miptails
This commit adds the code for choosing where to start the miptail and
enables miptails by default unless the client driver passes
info->min_miptail_start_level >= info->levels.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
2023-09-01 23:22:18 +00:00
Jason Ekstrand
a42d808b71 intel/isl: Support miptails in isl_surf_get_uncompressed_surf
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
2023-09-01 23:22:18 +00:00
Lionel Landwerlin
866af3d8fa isl: make isl_surf_get_uncompressed_surf robust to argument accesses
Since the input & output arguments can point to the same location in
memory, if you ever access the input after writing the output you're
in trouble.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
2023-09-01 23:22:18 +00:00
Jason Ekstrand
988fa2006a intel/isl: Add support for computing offsets with miptails
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
2023-09-01 23:22:17 +00:00
Lionel Landwerlin
1ada5f5490 intel/isl: Add a max_miptail_levels field to isl_tile_info
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
2023-09-01 23:22:17 +00:00
Jason Ekstrand
b1862a0964 intel/isl: Add initial data-structure support for miptails
This commit just adds a miptail start field to isl_surf and wires it up
in the RENDER_SURFACE_STATE and 3DSTATE_DEPTH code.  We also add a
minimum miptail LOD so that client drivers have a knob to control the
miptails a bit.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
2023-09-01 23:22:17 +00:00
Jason Ekstrand
68ac5c2165 intel/isl: Support Yf/Ys tiling in emit_depth_stencil_hiz
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
2023-09-01 23:22:17 +00:00
Jason Ekstrand
01b50c9dac intel/isl: Support Yf/Ys tiling in surf_fill_state
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
2023-09-01 23:22:17 +00:00
Jason Ekstrand
6f90d6d228 intel/isl: Support Ys, Yf & Tile64 in isl_surf_get_uncompressed_surf
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
2023-09-01 23:22:17 +00:00
Jason Ekstrand
4ef7b074e7 intel/isl: Indent uncompressed surface code
We're about to add separate code for Yf/Ys and this helps keep the diff
reasonable.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
2023-09-01 23:22:17 +00:00
Jason Ekstrand
9a4e9848ad intel/isl: Fill out the correct phys_total_extent for Ys/Yf/Tile64
With these tilings, everything is aligned to a tile and the tiled
surface size calculations will handle the array stride for us.  We need
to provide an accurate 4D size so that 3D and multisampled images get
tiled correctly.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
2023-09-01 23:22:17 +00:00
Jason Ekstrand
9421998e95 intel/isl: Use the depth field of phys_level0_sa for GFX4_2D 3D surfaces
This makes things a tiny bit stickier in isl_calc_phys_total_extent_el
but will be worth it when we enable Yf and Ys.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
2023-09-01 23:22:17 +00:00
Lionel Landwerlin
390d53e13f isl: disallow TileYs/Yf on 3D storage images on Gfx9/11
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
2023-09-01 23:22:17 +00:00
Lionel Landwerlin
15648dcbba isl: add a usage flag to request 2D/3D compatible views
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
2023-09-01 23:22:17 +00:00
Lionel Landwerlin
7c5015e181 isl: disable Yf/Ys/Tile64 tilings for 1D images
The ICL+ PRMs show that this is not a supported thing anymore for
Ys/Yf and there isn't really much use for it in Vulkan/Sparse.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
2023-09-01 23:22:17 +00:00
Lionel Landwerlin
6cde6b1d1a intel/isl: Disallow Yf, Ys and Tile64 for 3D depth/stencil surfaces
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
2023-09-01 23:22:17 +00:00
Jason Ekstrand
911832e9cf intel/isl: Implement correct tile size calculations for Ys/Yf
The tile size calculations use a clever bit of math to make them short
and simple.  We add unit tests to assert that they identically match the
tables in the PRM.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
2023-09-01 23:22:17 +00:00
Jason Ekstrand
e230ef329b intel/isl: Add ICL variants of Yf and Ys tiling
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
2023-09-01 23:22:17 +00:00
Jason Ekstrand
fa625aea3d intel/isl: Rename ISL_TILING_Yf/s to ISL_TILING_SKL_Yf/s
The Yf and Ys tilings change a bit between SKL and later generations so
we have to be able to distinguish between them.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
2023-09-01 23:22:17 +00:00
Lionel Landwerlin
298e8dee61 isl: program 3DSTATE_HIER_DEPTH_BUFFER_BODY::TiledMode as documented
Since this value is 0, it doesn't change anything, but it's just good
practice like we did for Gfx12.5 right above.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
2023-09-01 23:22:17 +00:00
Lionel Landwerlin
3e9f366b70 genxml/gfx12: rename Tiled Resource Mode
To match documentation.

BSpec 46965

TGL PRMs, Volume 2d: Command Reference: Structures, 3DSTATE_HIER_DEPTH_BUFFER_BODY

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23620>
2023-09-01 23:22:17 +00:00