Commit graph

145366 commits

Author SHA1 Message Date
Bas Nieuwenhuizen
ae5bea3125 radv: Add helper to parse raytracing stages.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12592>
2021-09-21 01:53:39 +00:00
Bas Nieuwenhuizen
207ce6d658 radv: Add helper to inline shaders into the main shader.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12592>
2021-09-21 01:53:39 +00:00
Bas Nieuwenhuizen
dcb02dbe73 radv: Add main loop variables.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12592>
2021-09-21 01:53:39 +00:00
Bas Nieuwenhuizen
701803e340 radv: Add scaffolding for RT pipeline compilation incl libraries.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12592>
2021-09-21 01:53:39 +00:00
Bas Nieuwenhuizen
f087b457e5 radv: Make some pipeline functions non-static.
Want to put the rt stuff in its own file. radv_pipeline.c is pretty
large already.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12592>
2021-09-21 01:53:39 +00:00
Bas Nieuwenhuizen
8312b2232b radv: Add raytracing pipeline properties.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12592>
2021-09-21 01:53:39 +00:00
Bas Nieuwenhuizen
0f090a51b3 radv: Add group info to pipeline.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12592>
2021-09-21 01:53:39 +00:00
Bas Nieuwenhuizen
080400e43c radv: Add pipeline type.
I want to keep pointers that need to be freed in the union and need
to figure out the type a destruction time. This seems more reliable
than checking the shader array in case we destroy mid-creation (i.e.
on failure).

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12592>
2021-09-21 01:53:39 +00:00
Bas Nieuwenhuizen
f5362742b9 radv: Add RT cache flushes.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12592>
2021-09-21 01:53:39 +00:00
Bas Nieuwenhuizen
8ca54b4d38 radv: Support nir_intrinsic_load_global_constant.
SPIR-V parsing can result in some direct constant usage for shader
records. Lower this early to a global based intrinsic so that it
doesn't interfere with the later 32-bit offset based constants
for scratch usage.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12592>
2021-09-21 01:53:39 +00:00
Bas Nieuwenhuizen
0d8bd8518d nir: Support ray launch size in divergence analysis.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12592>
2021-09-21 01:53:39 +00:00
Bas Nieuwenhuizen
c299968988 aco: Add support for ray launch size.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12592>
2021-09-21 01:53:39 +00:00
Bas Nieuwenhuizen
1ca4fd31e6 radv: Add support for ray launch size.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12592>
2021-09-21 01:53:39 +00:00
Bas Nieuwenhuizen
56b06c09b4 nir: Add AMD rt intrinsics.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12592>
2021-09-21 01:53:39 +00:00
Bas Nieuwenhuizen
148ea4375c radv: Implement NULL accel struct descriptor write.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12592>
2021-09-21 01:53:39 +00:00
Bas Nieuwenhuizen
2070d36cf3 radv: Do more meta shader lowering.
Need this to clean up our generated RT pipeline.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12592>
2021-09-21 01:53:39 +00:00
Bas Nieuwenhuizen
b1074fd51d radv: Refactor some nir_channels usage to use nir_channel.
cleanup, nir_channels wasn't needed as these were only accessing a
single channel.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12592>
2021-09-21 01:53:39 +00:00
Bas Nieuwenhuizen
817553c052 aco: Implement call scope.
Since we do no repacking yet, just use invocation.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12592>
2021-09-21 01:53:39 +00:00
Bas Nieuwenhuizen
b6be96a2bd radv: Modify load_sbt_amd intrinsic to get the descriptor.
That way we can get the address to the entry, which is needed for
some nir builtins because extra data in the entry can be used as
shader input.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12592>
2021-09-21 01:53:39 +00:00
Bas Nieuwenhuizen
2abf44cf18 radv: Add bvh node definitions to a header.
So that we can avoid some magic numbers in the pipeline creation.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12592>
2021-09-21 01:53:39 +00:00
Bas Nieuwenhuizen
a99ccd353b radv: Add optimized CPU BVH builds.
This trivial sorting helps speed up bad cases (like in CTS significantly).

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12592>
2021-09-21 01:53:39 +00:00
Bas Nieuwenhuizen
848d175c76 radv: Add more acceleration structure formats.
These are required ...

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12592>
2021-09-21 01:53:39 +00:00
Bas Nieuwenhuizen
506757ea86 radv: Add accel struct build support for the object-to-world matrix.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12592>
2021-09-21 01:53:39 +00:00
Bas Nieuwenhuizen
3e059dc1e0 radv: Fix arrayOfPointers for instances in accel struct build.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12592>
2021-09-21 01:53:39 +00:00
Bas Nieuwenhuizen
58ec4f3069 radv: Fix CPU AABB build.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12592>
2021-09-21 01:53:39 +00:00
Martin Krastev
4807d777c0 meson: introduce option vmware-mks-stats controlling the instrumentations of gallium svga driver
The new boolean option controls the instrumentations of gallium svga driver for mksGuestStats.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Zack Rusin <zackr@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
(cherry picked from commit 57760b7fe4eeb80acc8d6cd8bf6ec609a11a11dc)
(cherry picked from commit 12aed00f08bd95afd605cab34c833e81a4957dbd)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12873>
2021-09-21 00:07:40 +00:00
Martin Krastev
4feb9c3c47 svga: enable DRM mks-stats via hooking to the corresponding DRM ioctls
SVGA DRM stat calls were situated but did not actually register with the mks-stats
mechanism due to absence of corresponding ioctls. The employed new ioctls in vmwgfx
are DRM_VMW_MKSSTAT_ADD and DRM_VMW_MKSSTAT_REMOVE, subject to version check.

Reviewed-by: Charmaine Lee <charmainel@vmware.com>
(cherry picked from commit be47c077cc927c27a8c36342b47697aa81719677)
(cherry picked from commit 0388afc67b830f6ab916d0839c33eb1d91d6353f)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12873>
2021-09-21 00:07:39 +00:00
Mike Blumenkrantz
b61e9345c1 build: fix nine compilation with only zink enabled as a gallium driver
fixes #5360

Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12943>
2021-09-20 22:47:38 +00:00
Mike Blumenkrantz
aff177a0ad zink: fix regex syntax from previous ci commit
argh

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12948>
2021-09-20 18:33:32 -04:00
Mike Blumenkrantz
49b5e5be5a zink: disable miplevel tests in ci completely for now
I still can't repro, and I'm running these regularly on multiple platforms,
so they're not going to get any worse for the time being

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12947>
2021-09-20 22:20:48 +00:00
Philipp Zabel
b1b6d9e9a1 etnaviv: add mov for direct depth store output from load input
If the fragment shader writes fragment depth from an ALU instruction,
the register allocator makes sure that the instruction is pointed to the
correct register and write mask (t0.__z_).
If there is no instruction emitted because the source is an input
load intrinsic, or if the source instruction does not support swizzle
and write mask, we have to add a mov instruction for this to work.

Fixes piglit test spec@glsl-1.10@execution@glsl-1.10-fragdepth.

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12891>
2021-09-20 21:19:09 +00:00
Emma Anholt
ae01d856de nir_to_tgsi: Remove the abs on fcsel's bool src.
While the nir fcsel opcode specifies src0 != 0.0, as the comment says,
it's only ever used on bools-as-floats, so we know that src0 is
non-negative.  This saves an instruction per CMP on i915.

Reviewed-by: Zoltán Böszörményi <zboszor@gmail.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12921>
2021-09-20 20:20:54 +00:00
Emma Anholt
4b0975a8e1 ci/freedreno: Update restricted trace sha1s.
Rendering changed slightly recently, but the diffs look fine.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12939>
2021-09-20 19:55:55 +00:00
Emma Anholt
306a039472 ci/baremetal: Retry if our network device spontaneously fails.
Seen in https://gitlab.freedesktop.org/mesa/mesa/-/jobs/13824132.  It's
unlikely that graphics would kill the network, so just assume it's not our
fault and keep going.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12939>
2021-09-20 19:55:55 +00:00
Emma Anholt
9017bb0837 ci/freedreno: Add some cubearray piglit flakes on a630 I noticed.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12939>
2021-09-20 19:55:55 +00:00
Emma Anholt
feb971fdee freedreno: Assert to check for the previous regression.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12942>
2021-09-20 19:34:57 +00:00
Emma Anholt
b8c4ad378d freedreno: Fix autotune regression since batch-cache rework.
I freed the key that autotune needed a little early.

Fixes: b2349a4671 ("freedreno: Move the batch cache to the context.")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12942>
2021-09-20 19:34:57 +00:00
Rob Clark
27dd22cb62 turnip: Fix a6xx gen4 compute shaders
Port of 74d1052537 freedreno/a6xx: ("Fix a6xx gen4 compute shaders")

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5354
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12856>
2021-09-20 19:13:25 +00:00
Rob Clark
4e05338d99 turnip: Rast updates for a6xx gen4
Port of 219e12b7f3 ("freedreno/a6xx: Rast updates for a6xx gen3")

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12856>
2021-09-20 19:13:25 +00:00
Rob Clark
6ac1d8dc4c turnip: Fix unitialized cs->device
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12856>
2021-09-20 19:13:25 +00:00
Rob Clark
68d4d09b56 freedreno: Add info->a6xx.has_shading_rate
@flto noticed these registers seem to be related to GL_QCOM_shading_rate

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12856>
2021-09-20 19:13:25 +00:00
Danylo Piliaiev
4839f442e9 turnip: consider multiview_mask when clearing depth-stencil attachment
Otherwise only first layer is being cleared.

Would fix several VK_EXT_multi_draw tests:
 dEQP-VK.draw.multi_draw.overlapping.normal.max_draws.*.vert_only.multiview.no_offset

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12913>
2021-09-20 18:41:23 +00:00
Timur Kristóf
872d21820f nir: Exclude non-generic patch variables from get_variable_io_mask.
These are I/O variables which are not going to be removed anyway.
However, get_variable_io_mask handles their location incorrectly.

Found using the GCC undefined behavior sanitizer.
Fixes the following error:

runtime error:
shift exponent 4294967258 is too large
for 64-bit type 'long unsigned int'

Closes: #5319
Fixes: cf5f8f55c3
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12719>
2021-09-20 18:08:16 +00:00
Timur Kristóf
13e467a147 ac/nir: Fix match_mask to work correctly for VS outputs.
match_mask checks the intrinsic type and decides whether it's
per-patch or not. VS don't have per-patch outputs,
so this causes wrong behaviour there.

Found using the GCC undefined behavior sanitizer.
Fixes the following error:

runtime error:
shift exponent 18446744073709551584 is too large
for 64-bit type 'long unsigned int'

Closes: #5319
Fixes: bf966d1c1d
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12719>
2021-09-20 18:08:16 +00:00
Emma Anholt
4474c46f5f mesa/st: Allow loops in GLSL when NIR is enabled, even if the HW can't.
The jump lowering enabled by EmitNoLoops breaks GLSL's loop unrolling on
various obviously unrollable loops, resulting in a lot of deqp-gles2 and
piglit failures.  NIR will help unroll whatever GLSL doesn't, so we can
trust the driver to apply that after GLSL's unrolling, so no need to ask
GLSL to lower all loops.

Fixes: #4979
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Zoltán Böszörményi <zboszor@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12917>
2021-09-20 17:41:24 +00:00
Emma Anholt
346a2950bb ci/i915g: Clarify failure happening in fbo-fragcoord2.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12917>
2021-09-20 17:41:24 +00:00
Philipp Zabel
4968313fe5 etnaviv: fix dirty bit check for baselod emission
Since baselod is stored in sampler state, not sampler view, we should
check the ETNA_DIRTY_SAMPLERS bit instead of ETNA_DIRTY_SAMPLER_VIEWS.

Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12916>
2021-09-20 17:03:14 +00:00
Zachary Michaels
fc5ea6a054 X11: Ensure that VK_SUBOPTIMAL_KHR propagates to user code
Commit 0245b825 switched from returning the error code VK_ERROR_OUT_OF_DATE_KHR
to returning the success code VK_SUBOPTIMAL_KHR. Prior to that commit, the error
code caused all code paths to fail immediately, but the success code does not.

Currently the success code is not recorded in some scenarios, resulting in a
result of VK_SUCCESS instead. This breaks applications that rely on the
result (per the spec) to trigger resizes.

This commit ensures that the proper VK_SUBOPTIMAL_KHR success code is set as a
sticky status (as comments indicate was intended), ensuring that it is
propagated to user code.

Fixes #5331

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12782>
2021-09-20 16:43:10 +00:00
Samuel Pitoiset
0be0ad102e radv: keep depth/stencil images compressed for TRANSFER_DST on compute
Only if the image is TC-compat HTILE because it can be decompressed
on compute for partial copies.

This should remove few depth/stencil decompressions for RAGE2 and Red
Dead Redemption 2 because they declare all images as concurrent but
never use the compute queue for them.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12452>
2021-09-20 15:17:42 +00:00
Samuel Pitoiset
2b805b8a6c radv: add support for copying compressed depth/stencil images on compute
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12452>
2021-09-20 15:17:42 +00:00