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freedreno: Add info->a6xx.has_shading_rate

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@flto noticed these registers seem to be related to GL_QCOM_shading_rate

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12856>
This commit is contained in:
Rob Clark 2021-09-14 11:29:00 -07:00 • committed by Marge Bot
parent 4839f442e9
commit 68d4d09b56
3 changed files with 5 additions and 8 deletions
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3
src/freedreno/common/freedreno_dev_info.h
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@ -69,6 +69,9 @@ struct fd_dev_info {
bool tess_use_shared;
/* Does the hw support GL_QCOM_shading_rate? */
bool has_shading_rate;
/* newer a6xx allows using 16-bit descriptor for both 16-bit
* and 32-bit access
*/

1
src/freedreno/common/freedreno_devices.py
View file

@ -243,6 +243,7 @@ a6xx_gen4 = dict(
has_cp_reg_write = False,
has_8bpp_ubwc = False,
has_lpac = True,
has_shading_rate = True,
)
add_gpus([

9
src/gallium/drivers/freedreno/a6xx/fd6_rasterizer.c
View file

@ -94,14 +94,7 @@ __fd6_setup_rasterizer_stateobj(struct fd_context *ctx,
OUT_REG(ring, A6XX_VPC_POLYGON_MODE(mode));
OUT_REG(ring, A6XX_PC_POLYGON_MODE(mode));
/* These started showing up in a6xx gen3, but so far I haven't found
* any example of blob setting them to anything other than zero.
*
* Probably not related to tess_use_shared, but that is a convenient
* thing to key off of until we find whatever new feature gen3 added
* that uses these registers.
*/
if (ctx->screen->info->a6xx.tess_use_shared) {
if (ctx->screen->info->a6xx.has_shading_rate) {
OUT_REG(ring, A6XX_RB_UNKNOWN_8A00());
OUT_REG(ring, A6XX_RB_UNKNOWN_8A10());
OUT_REG(ring, A6XX_RB_UNKNOWN_8A20());