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Author SHA1 Message Date
Dave Airlie
a01816da59 r500: bump state atom size up for fp and fp constants 2008-05-22 17:09:58 +10:00
Corbin Simpson
4f9dcdc35b r5xx: Fixed LRP. 
Works perfectly. It's a complex one, though, so it might fail in weird ways...
 2008-05-21 23:35:43 -07:00
Corbin Simpson
0dfbe9cdd7 r5xx: Change debug info for readability. 
It's weird seeing the compiled program before the assembly, that's all.
 2008-05-21 23:33:13 -07:00
Corbin Simpson
d06f4edb14 r5xx: Initial (broken) OPCODE_LRP. 
Will compile, run, and not eat your kids, but the math is wrong.
 2008-05-21 13:51:32 -07:00
Corbin Simpson
1e2907f170 r5xx: Add OPCODE_POW. 
Necessary for Google Earth, among other things.
 2008-05-21 08:24:28 -07:00
Dave Airlie
bb57c30a53 r500: print out opcode string 2008-05-21 16:00:18 +10:00
Dave Airlie
b453b0e2e1 r500: set the RS unit register for R500 not R300 dangnammit.. 
So this appears to be my BUG. damn it to hell.

also fix sec color to be more like spec says.
 2008-05-21 12:14:42 +10:00
Dave Airlie
9ec2b1c83f r500: finish main texture instruction decoding 2008-05-21 10:49:26 +10:00
Corbin Simpson
2bda1a9502 r5xx: Count refs so we don't have to guess on temp reg allocation. 
As a bonus, we can now have multiple temp temps, by slot.
 2008-05-20 09:47:50 -07:00
Corbin Simpson
94994b13c5 r5xx: Fixup SOP insts. 
Use the correct swizzle for alpha/SOP stuff.
 2008-05-19 23:56:53 -07:00
Corbin Simpson
78fa506059 r5xx: New fix for COS/SIN/SCS. 
Not perfect yet, but getting better.
 2008-05-19 23:56:53 -07:00
Dave Airlie
f0d76d526b r300/r500: fixup some of the register write sizes 2008-05-20 16:30:36 +10:00
Dave Airlie
2005de48f9 r300: some ctrl-m's wierd. 2008-05-20 16:02:19 +10:00
Dave Airlie
282cdc8b5c r300/r500: fix RS col fmt bits 2008-05-20 15:59:56 +10:00
Corbin Simpson
476248befe r5xx: Fixup emit_tex, add debugging info, enable temp temps. 
emit_tex now chases itself with an OUT if needed.
Added airlied's dump_program, with some fixes.
 2008-05-19 11:06:41 -07:00
Dave Airlie
03b3fed8f1 r500: add more input srcs 2008-05-19 21:58:28 +10:00
Dave Airlie
ac315792bf r500: fix swz gets and some returns 2008-05-19 21:40:40 +10:00
Dave Airlie
60b8e1f524 r500: add mask debugging 2008-05-19 21:11:55 +10:00
Dave Airlie
cddab021e3 r500: add fragment program debug dumper 2008-05-19 20:24:09 +10:00
Corbin Simpson
c60bdcf8a8 r5xx: Fix magic offsets for output fifo write masks. 
Well, this sure explains a lot.
 2008-05-19 00:00:08 -07:00
Corbin Simpson
2708d7f700 r5xx: Swap sources for CMP. 
Follows the same pattern as the op on r3xx/r4xx. Thanks airlied.
 2008-05-18 23:52:54 -07:00
Corbin Simpson
a6c38f2f64 r5xx: Fix typo of epic proportions. 2008-05-18 23:35:07 -07:00
Corbin Simpson
2225b9bdb0 r5xx: ALU/OUT fixups. 
Lots of small changes. Intentionally breaks some tex stuffs.
 2008-05-18 22:38:28 -07:00
Dave Airlie
bdfd5d95c5 r300: fixup US_OUT_FMT bits 2008-05-18 17:58:29 +10:00
Dave Airlie
126673261d r500: you can have a single texcoord 2008-05-18 15:25:08 +10:00
Corbin Simpson
0910d9d4d6 r5xx: Add OPCODE_KIL. 2008-05-17 13:38:35 -07:00
Corbin Simpson
c57b3b1d2c r5xx: Added OPCODE_DPH. 
Like DP4, but with one swizzle change.
 2008-05-17 12:45:46 -07:00
Corbin Simpson
6dd3c0ed96 r5xx: Fix FRC. 
This makes tri-frc work.
(Remind me again why I'm allowed near a compiler, lawl.)
 2008-05-17 09:27:35 -07:00
Corbin Simpson
16cc362f0b r5xx: Fix SCS. 
Output instructions need to be marked OUT so they can write to the fifo.
Also, negation doesn't work with SWZ yet.
 2008-05-17 07:12:38 -07:00
Corbin Simpson
c11a33fe76 r5xx: Add OPCODE_SWZ. 
It's so easy!
 2008-05-17 07:12:37 -07:00
Corbin Simpson
d5aa421661 r5xx: Add OPCODE_SCS. 
It's disabled, though, because it doesn't work. I'll figure it out later...
 2008-05-17 07:12:37 -07:00
Corbin Simpson
405ee871c5 r5xx: Adding more opcodes. 
EX2, FRC, LG2, SIN, RCP, and RSQ, if you care.
All of these except FRC are like COS. This pretty much rounds out the set of
opcodes which can be done in one ALU inst.
 2008-05-17 07:12:37 -07:00
Corbin Simpson
0de02f1716 r5xx: First swing at OPCODE_COS. 2008-05-17 07:12:37 -07:00
Corbin Simpson
d8529d9b00 r5xx: Unbreak MAX and MIN. 
Both of them had faulty copypasta.
 2008-05-17 07:12:37 -07:00
Dave Airlie
5e075fb809 r500: set fragprog end to correct place 2008-05-17 13:31:14 +10:00
Alex Deucher
ba50c3fed3 r300: SC register naming cleanup 2008-05-17 10:40:47 +10:00
Alex Deucher
791c95230c r500: write out the correct FP registers 2008-05-17 10:29:52 +10:00
Dave Airlie
d6333af7e9 r500: default rsunit swizzle like fglrx 2008-05-15 20:38:41 +10:00
Dave Airlie
9aa62c7238 r500: shift tex src properly 2008-05-15 18:40:07 +10:00
Dave Airlie
76f32499d2 r500: fixup r500 rs unit texture coordinate counting 2008-05-15 18:40:07 +10:00
Dave Airlie
a0bc6d2fb2 r500: remove some debugging 2008-05-15 18:40:07 +10:00
Dave Airlie
73af48fff5 r500: split output/pixel masks and emit in the correct places 2008-05-15 18:40:07 +10:00
Dave Airlie
c9d5d11d2d r3/500: emit RS state before VAP 2008-05-15 18:40:07 +10:00
Dave Airlie
412c850eab r500: fixup the program allocations to be the correct sizes 2008-05-15 18:40:07 +10:00
Dave Airlie
350c80fa99 r300: set screen so that context init can find out chip ids 2008-05-15 18:40:07 +10:00
Dave Airlie
e1bffd0318 r500: add cmp support in theory 2008-05-15 18:40:07 +10:00
Dave Airlie
10e0a36a49 r500: some trivial fixups to get tri working. 
the counter was being used one instruction over the end
 2008-05-15 18:40:07 +10:00
Dave Airlie
375656440b r500: we just need to emit a colour for clear drop tex instruction 2008-05-15 18:40:07 +10:00
Alex Deucher
f86baae1a7 R300: clean up GA registers 2008-05-13 16:12:57 -04:00
Alex Deucher
de3fc8b1c4 R3xx: clean up ZB registers 2008-05-13 15:46:23 -04:00