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R3xx: clean up ZB registers

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This commit is contained in:
Alex Deucher 2008-05-13 15:46:23 -04:00
parent c5b7a1ee3c
commit de3fc8b1c4
5 changed files with 181 additions and 186 deletions
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12
src/mesa/drivers/dri/r300/r300_cmdbuf.c
View file

@ -465,20 +465,20 @@ void r300InitCmdBuf(r300ContextPtr r300)
r300->hw.rb3d_discard_src_pixel_lte_threshold.cmd[0] = cmdpacket0(R500_RB3D_DISCARD_SRC_PIXEL_LTE_THRESHOLD, 2);
ALLOC_STATE(zs, always, R300_ZS_CMDSIZE, 0);
r300->hw.zs.cmd[R300_ZS_CMD_0] =
cmdpacket0(R300_RB3D_ZSTENCIL_CNTL_0, 3);
cmdpacket0(R300_ZB_CNTL, 3);
ALLOC_STATE(zstencil_format, always, 5, 0);
r300->hw.zstencil_format.cmd[0] =
cmdpacket0(ZB_FORMAT, 4);
cmdpacket0(R300_ZB_FORMAT, 4);
ALLOC_STATE(zb, always, R300_ZB_CMDSIZE, 0);
r300->hw.zb.cmd[R300_ZB_CMD_0] = cmdpacket0(ZB_DEPTHOFFSET, 2);
r300->hw.zb.cmd[R300_ZB_CMD_0] = cmdpacket0(R300_ZB_DEPTHOFFSET, 2);
ALLOC_STATE(zb_depthclearvalue, always, 2, 0);
r300->hw.zb_depthclearvalue.cmd[0] = cmdpacket0(ZB_DEPTHCLEARVALUE, 1);
r300->hw.zb_depthclearvalue.cmd[0] = cmdpacket0(R300_ZB_DEPTHCLEARVALUE, 1);
ALLOC_STATE(unk4F30, always, 3, 0);
r300->hw.unk4F30.cmd[0] = cmdpacket0(0x4F30, 2);
ALLOC_STATE(zb_hiz_offset, always, 2, 0);
r300->hw.zb_hiz_offset.cmd[0] = cmdpacket0(ZB_HIZ_OFFSET, 1);
r300->hw.zb_hiz_offset.cmd[0] = cmdpacket0(R300_ZB_HIZ_OFFSET, 1);
ALLOC_STATE(zb_hiz_pitch, always, 2, 0);
r300->hw.zb_hiz_pitch.cmd[0] = cmdpacket0(ZB_HIZ_PITCH, 1);
r300->hw.zb_hiz_pitch.cmd[0] = cmdpacket0(R300_ZB_HIZ_PITCH, 1);
/* VPU only on TCL */
if (has_tcl) {

6
src/mesa/drivers/dri/r300/r300_emit.c
View file

@ -553,7 +553,7 @@ void r300EmitCacheFlush(r300ContextPtr rmesa)
e32(R300_RB3D_DSTCACHE_CTLSTAT_DC_FREE_FREE_3D_TAGS |
R300_RB3D_DSTCACHE_CTLSTAT_DC_FLUSH_FLUSH_DIRTY_3D);
reg_start(ZB_ZCACHE_CTLSTAT, 0);
e32(ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE |
ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE);
reg_start(R300_ZB_ZCACHE_CTLSTAT, 0);
e32(R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE |
R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE);
}

28
src/mesa/drivers/dri/r300/r300_ioctl.c
View file

@ -118,7 +118,7 @@ static void r300ClearBuffer(r300ContextPtr r300, int flags, int buffer)
}
R300_STATECHANGE(r300, zs);
reg_start(R300_RB3D_ZSTENCIL_CNTL_0, 2);
reg_start(R300_ZB_CNTL, 2);
{
uint32_t t1, t2;
@ -127,32 +127,32 @@ static void r300ClearBuffer(r300ContextPtr r300, int flags, int buffer)
t2 = 0x0;
if (flags & CLEARBUFFER_DEPTH) {
t1 |= R300_RB3D_Z_WRITE_ONLY;
t1 |= R300_Z_ENABLE | R300_Z_WRITE_ENABLE;
t2 |=
(R300_ZS_ALWAYS << R300_RB3D_ZS1_DEPTH_FUNC_SHIFT);
} else {
t1 |= R300_RB3D_Z_DISABLED_1; // disable
(R300_ZS_ALWAYS << R300_Z_FUNC_SHIFT);
} else { //XXX
t1 |= R300_STENCIL_FRONT_BACK; // disable
}
if (flags & CLEARBUFFER_STENCIL) {
t1 |= R300_RB3D_STENCIL_ENABLE;
t1 |= R300_STENCIL_ENABLE;
t2 |=
(R300_ZS_ALWAYS <<
R300_RB3D_ZS1_FRONT_FUNC_SHIFT) |
R300_S_FRONT_FUNC_SHIFT) |
(R300_ZS_REPLACE <<
R300_RB3D_ZS1_FRONT_FAIL_OP_SHIFT) |
R300_S_FRONT_SFAIL_OP_SHIFT) |
(R300_ZS_REPLACE <<
R300_RB3D_ZS1_FRONT_ZPASS_OP_SHIFT) |
R300_S_FRONT_ZPASS_OP_SHIFT) |
(R300_ZS_REPLACE <<
R300_RB3D_ZS1_FRONT_ZFAIL_OP_SHIFT) |
R300_S_FRONT_ZFAIL_OP_SHIFT) |
(R300_ZS_ALWAYS <<
R300_RB3D_ZS1_BACK_FUNC_SHIFT) |
R300_S_BACK_FUNC_SHIFT) |
(R300_ZS_REPLACE <<
R300_RB3D_ZS1_BACK_FAIL_OP_SHIFT) |
R300_S_BACK_SFAIL_OP_SHIFT) |
(R300_ZS_REPLACE <<
R300_RB3D_ZS1_BACK_ZPASS_OP_SHIFT) |
R300_S_BACK_ZPASS_OP_SHIFT) |
(R300_ZS_REPLACE <<
R300_RB3D_ZS1_BACK_ZFAIL_OP_SHIFT);
R300_S_BACK_ZFAIL_OP_SHIFT);
}
e32(t1);

219
src/mesa/drivers/dri/r300/r300_reg.h
View file

@ -2279,19 +2279,14 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
* for this.
* Bit (1<<8) is the "test" bit. so plain write is 6 - vd
*/
#define R300_RB3D_ZSTENCIL_CNTL_0 0x4F00
# define R300_RB3D_Z_DISABLED_1 0x00000010
# define R300_RB3D_Z_DISABLED_2 0x00000014
# define R300_RB3D_Z_TEST 0x00000012
# define R300_RB3D_Z_TEST_AND_WRITE 0x00000016
# define R300_RB3D_Z_WRITE_ONLY 0x00000006
#define R300_ZB_CNTL 0x4F00
# define R300_STENCIL_ENABLE (1 << 0)
# define R300_Z_ENABLE (1 << 1)
# define R300_Z_WRITE_ENABLE (1 << 2)
# define R300_Z_SIGNED_COMPARE (1 << 3)
# define R300_STENCIL_FRONT_BACK (1 << 4)
# define R300_RB3D_Z_TEST 0x00000012
# define R300_RB3D_Z_TEST_AND_WRITE 0x00000016
# define R300_RB3D_Z_WRITE_ONLY 0x00000006
# define R300_RB3D_STENCIL_ENABLE 0x00000001
#define R300_RB3D_ZSTENCIL_CNTL_1 0x4f04
#define R300_ZB_ZSTENCILCNTL 0x4f04
/* functions */
# define R300_ZS_NEVER 0
# define R300_ZS_LESS 1
@ -2311,51 +2306,49 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
# define R300_ZS_INVERT 5
# define R300_ZS_INCR_WRAP 6
# define R300_ZS_DECR_WRAP 7
# define R300_Z_FUNC_SHIFT 0
/* front and back refer to operations done for front
and back faces, i.e. separate stencil function support */
# define R300_RB3D_ZS1_DEPTH_FUNC_SHIFT 0
# define R300_RB3D_ZS1_FRONT_FUNC_SHIFT 3
# define R300_RB3D_ZS1_FRONT_FAIL_OP_SHIFT 6
# define R300_RB3D_ZS1_FRONT_ZPASS_OP_SHIFT 9
# define R300_RB3D_ZS1_FRONT_ZFAIL_OP_SHIFT 12
# define R300_RB3D_ZS1_BACK_FUNC_SHIFT 15
# define R300_RB3D_ZS1_BACK_FAIL_OP_SHIFT 18
# define R300_RB3D_ZS1_BACK_ZPASS_OP_SHIFT 21
# define R300_RB3D_ZS1_BACK_ZFAIL_OP_SHIFT 24
# define R300_S_FRONT_FUNC_SHIFT 3
# define R300_S_FRONT_SFAIL_OP_SHIFT 6
# define R300_S_FRONT_ZPASS_OP_SHIFT 9
# define R300_S_FRONT_ZFAIL_OP_SHIFT 12
# define R300_S_BACK_FUNC_SHIFT 15
# define R300_S_BACK_SFAIL_OP_SHIFT 18
# define R300_S_BACK_ZPASS_OP_SHIFT 21
# define R300_S_BACK_ZFAIL_OP_SHIFT 24
#define ZB_STENCILREFMASK 0x4f08
# define ZB_STENCILREFMASK_STENCILREF_SHIFT 0
# define ZB_STENCILREFMASK_STENCIL_MASK 0xff
# define ZB_STENCILREFMASK_STENCILREF_MASK 0x000000ff
# define ZB_STENCILREFMASK_STENCILMASK_SHIFT 8
# define ZB_STENCILREFMASK_STENCILMASK_MASK 0x0000ff00
# define ZB_STENCILREFMASK_STENCILWRITEMASK_SHIFT 16
# define ZB_STENCILREFMASK_STENCILWRITEMASK_MASK 0xffff0000
#define R300_ZB_STENCILREFMASK 0x4f08
# define R300_STENCILREF_SHIFT 0
# define R300_STENCILREF_MASK 0x000000ff
# define R300_STENCILMASK_SHIFT 8
# define R300_STENCILMASK_MASK 0x0000ff00
# define R300_STENCILWRITEMASK_SHIFT 16
# define R300_STENCILWRITEMASK_MASK 0x00ff0000
/* gap */
#define ZB_FORMAT 0x4f10
# define ZB_FORMAR_DEPTHFORMAT_16BIT_INT_Z (0 << 0)
# define ZB_FORMAR_DEPTHFORMAT_16BIT_13E3 (1 << 0)
# define ZB_FORMAR_DEPTHFORMAT_24BIT_INT_Z (2 << 0)
#define R300_ZB_FORMAT 0x4f10
# define R300_DEPTHFORMAT_16BIT_INT_Z (0 << 0)
# define R300_DEPTHFORMAT_16BIT_13E3 (1 << 0)
# define R300_DEPTHFORMAT_24BIT_INT_Z_8BIT_STENCIL (2 << 0)
/* reserved up to (15 << 0) */
# define ZB_FORMAR_INVERT_13E3_LEADING_ONES (0 << 4)
# define ZB_FORMAR_INVERT_13E3_LEADING_ZEROS (1 << 4)
# define ZB_FORMAR_PEQ8_UNUSED (1 << 5)
# define R300_INVERT_13E3_LEADING_ONES (0 << 4)
# define R300_INVERT_13E3_LEADING_ZEROS (1 << 4)
#define R300_RB3D_EARLY_Z 0x4F14
# define R300_EARLY_Z_DISABLE (0 << 0)
# define R300_EARLY_Z_ENABLE (1 << 0)
#define R300_ZB_ZTOP 0x4F14
# define R300_ZTOP_DISABLE (0 << 0)
# define R300_ZTOP_ENABLE (1 << 0)
/* gap */
#define ZB_ZCACHE_CTLSTAT 0x4f18
# define ZB_ZCACHE_CTLSTAT_ZC_FLUSH_NO_EFFECT (0 << 0)
# define ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE (1 << 0)
# define ZB_ZCACHE_CTLSTAT_ZC_FREE_NO_EFFECT (0 << 1)
# define ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE (1 << 1)
# define ZB_ZCACHE_CTLSTAT_ZC_BUSY_IDLE (0 << 31)
# define ZB_ZCACHE_CTLSTAT_ZC_BUSY_BUSY (1 << 31)
#define R300_ZB_ZCACHE_CTLSTAT 0x4f18
# define R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_NO_EFFECT (0 << 0)
# define R300_ZB_ZCACHE_CTLSTAT_ZC_FLUSH_FLUSH_AND_FREE (1 << 0)
# define R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_NO_EFFECT (0 << 1)
# define R300_ZB_ZCACHE_CTLSTAT_ZC_FREE_FREE (1 << 1)
# define R300_ZB_ZCACHE_CTLSTAT_ZC_BUSY_IDLE (0 << 31)
# define R300_ZB_ZCACHE_CTLSTAT_ZC_BUSY_BUSY (1 << 31)
#define R300_ZB_BW_CNTL 0x4f1c
# define R300_HIZ_DISABLE (0 << 0)
@ -2372,31 +2365,32 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
# define R300_ZB_CB_CLEAR_CACHE_LINEAR (1 << 5)
# define R300_FORCE_COMPRESSED_STENCIL_VALUE_DISABLE (0 << 6)
# define R300_FORCE_COMPRESSED_STENCIL_VALUE_ENABLE (1 << 6)
# define R300_ZEQUAL_OPTIMIZE_ENABLE (0 << 7)
# define R300_ZEQUAL_OPTIMIZE_DISABLE (1 << 7)
# define R300_SEQUAL_OPTIMIZE_ENABLE (0 << 8)
# define R300_SEQUAL_OPTIMIZE_DISABLE (1 << 8)
/* gap in AMD docs */
# define R300_BMASK_ENABLE (0 << 10)
# define R300_BMASK_DISABLE (1 << 10)
# define R300_HIZ_EQUAL_REJECT_DISABLE (0 << 11)
# define R300_HIZ_EQUAL_REJECT_ENABLE (1 << 11)
# define R300_HIZ_FP_EXP_BITS_DISABLE (0 << 12)
# define R300_HIZ_FP_EXP_BITS_1 (1 << 12)
# define R300_HIZ_FP_EXP_BITS_2 (2 << 12)
# define R300_HIZ_FP_EXP_BITS_3 (3 << 12)
# define R300_HIZ_FP_EXP_BITS_4 (4 << 12)
# define R300_HIZ_FP_EXP_BITS_5 (5 << 12)
# define R300_HIZ_FP_INVERT_LEADING_ONES (0 << 15)
# define R300_HIZ_FP_INVERT_LEADING_ZEROS (1 << 15)
# define R300_TILE_OVERWRITE_RECOMPRESSION_ENABLE (0 << 16)
# define R300_TILE_OVERWRITE_RECOMPRESSION_DISABLE (1 << 16)
# define R300_CONTIGUOUS_6XAA_SAMPLES_ENABLE (0 << 17)
# define R300_CONTIGUOUS_6XAA_SAMPLES_DISABLE (1 << 17)
# define R300_PEQ_PACKING_DISABLE (0 << 18)
# define R300_PEQ_PACKING_ENABLE (1 << 18)
# define R300_COVERED_PTR_MASKING_DISABLE (0 << 18)
# define R300_COVERED_PTR_MASKING_ENABLE (1 << 18)
# define R500_ZEQUAL_OPTIMIZE_ENABLE (0 << 7)
# define R500_ZEQUAL_OPTIMIZE_DISABLE (1 << 7)
# define R500_SEQUAL_OPTIMIZE_ENABLE (0 << 8)
# define R500_SEQUAL_OPTIMIZE_DISABLE (1 << 8)
# define R500_BMASK_ENABLE (0 << 10)
# define R500_BMASK_DISABLE (1 << 10)
# define R500_HIZ_EQUAL_REJECT_DISABLE (0 << 11)
# define R500_HIZ_EQUAL_REJECT_ENABLE (1 << 11)
# define R500_HIZ_FP_EXP_BITS_DISABLE (0 << 12)
# define R500_HIZ_FP_EXP_BITS_1 (1 << 12)
# define R500_HIZ_FP_EXP_BITS_2 (2 << 12)
# define R500_HIZ_FP_EXP_BITS_3 (3 << 12)
# define R500_HIZ_FP_EXP_BITS_4 (4 << 12)
# define R500_HIZ_FP_EXP_BITS_5 (5 << 12)
# define R500_HIZ_FP_INVERT_LEADING_ONES (0 << 15)
# define R500_HIZ_FP_INVERT_LEADING_ZEROS (1 << 15)
# define R500_TILE_OVERWRITE_RECOMPRESSION_ENABLE (0 << 16)
# define R500_TILE_OVERWRITE_RECOMPRESSION_DISABLE (1 << 16)
# define R500_CONTIGUOUS_6XAA_SAMPLES_ENABLE (0 << 17)
# define R500_CONTIGUOUS_6XAA_SAMPLES_DISABLE (1 << 17)
# define R500_PEQ_PACKING_DISABLE (0 << 18)
# define R500_PEQ_PACKING_ENABLE (1 << 18)
# define R500_COVERED_PTR_MASKING_DISABLE (0 << 18)
# define R500_COVERED_PTR_MASKING_ENABLE (1 << 18)
/* gap */
@ -2404,67 +2398,68 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
/* Z Buffer Address Offset.
* Bits 31 to 5 are used for aligned Z buffer address offset for macro tiles.
*/
#define ZB_DEPTHOFFSET 0x4f20
#define R300_ZB_DEPTHOFFSET 0x4f20
/* Z Buffer Pitch and Endian Control */
#define ZB_DEPTHPITCH 0x4f24
# define R300_DEPTHPITCH_MASK 0x00001FF8 /* TODO: should be (13:2) */
# define ZB_DEPTHPITCH_DEPTHMACROTILE_DISABLE (0 << 16)
# define ZB_DEPTHPITCH_DEPTHMACROTILE_ENABLE (1 << 16)
# define ZB_DEPTHPITCH_DEPTHMICROTILE_LINEAR (0 << 17)
# define ZB_DEPTHPITCH_DEPTHMICROTILE_TILED (1 << 17)
# define ZB_DEPTHPITCH_DEPTHMICROTILE_TILED_SQUARE (2 << 17)
# define ZB_DEPTHPITCH_DEPTHENDIAN_NO_SWAP (0 << 18)
# define ZB_DEPTHPITCH_DEPTHENDIAN_WORD_SWAP (1 << 18)
# define ZB_DEPTHPITCH_DEPTHENDIAN_DWORD_SWAP (2 << 18)
# define ZB_DEPTHPITCH_DEPTHENDIAN_HALF_DWORD_SWAP (3 << 18)
#define R300_ZB_DEPTHPITCH 0x4f24
# define R300_DEPTHPITCH_MASK 0x00003FFC
# define R300_DEPTHMACROTILE_DISABLE (0 << 16)
# define R300_DEPTHMACROTILE_ENABLE (1 << 16)
# define R300_DEPTHMICROTILE_LINEAR (0 << 17)
# define R300_DEPTHMICROTILE_TILED (1 << 17)
# define R300_DEPTHMICROTILE_TILED_SQUARE (2 << 17)
# define R300_DEPTHENDIAN_NO_SWAP (0 << 18)
# define R300_DEPTHENDIAN_WORD_SWAP (1 << 18)
# define R300_DEPTHENDIAN_DWORD_SWAP (2 << 18)
# define R300_DEPTHENDIAN_HALF_DWORD_SWAP (3 << 18)
/* Z Buffer Clear Value */
#define ZB_DEPTHCLEARVALUE 0x4f28
#define R300_ZB_DEPTHCLEARVALUE 0x4f28
/* Hierarchical Z Memory Offset */
#define ZB_HIZ_OFFSET 0x4f44
/* Hierarchical Z Read Index */
#define ZB_HIZ_RDINDEX 0x4f48
/* Hierarchical Z Data */
#define ZB_HIZ_DWORD 0x4f4c
#define R300_ZB_HIZ_OFFSET 0x4f44
/* Hierarchical Z Write Index */
#define ZB_HIZ_WRINDEX 0x4f50
#define R300_ZB_HIZ_WRINDEX 0x4f48
/* Hierarchical Z Data */
#define R300_ZB_HIZ_DWORD 0x4f4c
/* Hierarchical Z Read Index */
#define R300_ZB_HIZ_RDINDEX 0x4f50
/* Hierarchical Z Pitch */
#define ZB_HIZ_PITCH 0x4f54
#define R300_ZB_HIZ_PITCH 0x4f54
/* Z Buffer Z Pass Counter Data */
#define ZB_ZPASS_DATA 0x4f58
#define R300_ZB_ZPASS_DATA 0x4f58
/* Z Buffer Z Pass Counter Address */
#define ZB_ZPASS_ADDR 0x4f5c
#define R300_ZB_ZPASS_ADDR 0x4f5c
/* Depth buffer X and Y coordinate offset */
#define ZB_DEPTHXY_OFFSET 0x4f60
# define ZB_DEPTHX_OFFSET_SHIFT 1
# define ZB_DEPTHX_OFFSET_MASK 0x000007FE
# define ZB_DEPTHY_OFFSET_SHIFT 17
# define ZB_DEPTHY_OFFSET_MASK 0x07FE0000
#define R300_ZB_DEPTHXY_OFFSET 0x4f60
# define R300_DEPTHX_OFFSET_SHIFT 1
# define R300_DEPTHX_OFFSET_MASK 0x000007FE
# define R300_DEPTHY_OFFSET_SHIFT 17
# define R300_DEPTHY_OFFSET_MASK 0x07FE0000
/* Sets the fifo sizes */
#define ZB_FIFO_SIZE 0x4fd0
# define ZB_FIFO_SIZE_OP_FIFO_SIZE_FULL (0 << 0)
# define ZB_FIFO_SIZE_OP_FIFO_SIZE_HALF (1 << 0)
# define ZB_FIFO_SIZE_OP_FIFO_SIZE_QUATER (2 << 0)
# define ZB_FIFO_SIZE_OP_FIFO_SIZE_EIGTHS (4 << 0)
#define R500_ZB_FIFO_SIZE 0x4fd0
# define R500_OP_FIFO_SIZE_FULL (0 << 0)
# define R500_OP_FIFO_SIZE_HALF (1 << 0)
# define R500_OP_FIFO_SIZE_QUATER (2 << 0)
# define R500_OP_FIFO_SIZE_EIGTHS (4 << 0)
/* Stencil Reference Value and Mask for backfacing quads */
#define ZB_STENCILREFMASK_BF 0x4fd4
# define ZB_STENCILREFMASK_BF_STENCILREF_SHIFT 0
# define ZB_STENCILREFMASK_BF_STENCILREF_MASK 0x000000ff
# define ZB_STENCILREFMASK_BF_STENCILMASK_SHIFT 8
# define ZB_STENCILREFMASK_BF_STENCILMASK_MASK 0x0000ff00
# define ZB_STENCILREFMASK_BF_STENCILWRITEMASK_SHIFT 16
# define ZB_STENCILREFMASK_BF_STENCILWRITEMASK_MASK 0xffff0000
/* R300_ZB_STENCILREFMASK handles front face */
#define R500_ZB_STENCILREFMASK_BF 0x4fd4
# define R500_STENCILREF_SHIFT 0
# define R500_STENCILREF_MASK 0x000000ff
# define R500_STENCILMASK_SHIFT 8
# define R500_STENCILMASK_MASK 0x0000ff00
# define R500_STENCILWRITEMASK_SHIFT 16
# define R500_STENCILWRITEMASK_MASK 0x00ff0000
/**
* \defgroup R3XX_R5XX_PROGRAMMABLE_VERTEX_SHADER_DESCRIPTION R3XX-R5XX PROGRAMMABLE VERTEX SHADER DESCRIPTION

102
src/mesa/drivers/dri/r300/r300_state.c
View file

@ -415,10 +415,10 @@ static void r300SetEarlyZState(GLcontext * ctx)
R300_STATECHANGE(r300, zstencil_format);
switch (ctx->Visual.depthBits) {
case 16:
r300->hw.zstencil_format.cmd[1] = ZB_FORMAR_DEPTHFORMAT_16BIT_INT_Z;
r300->hw.zstencil_format.cmd[1] = R300_DEPTHFORMAT_16BIT_INT_Z;
break;
case 24:
r300->hw.zstencil_format.cmd[1] = ZB_FORMAR_DEPTHFORMAT_24BIT_INT_Z;
r300->hw.zstencil_format.cmd[1] = R300_DEPTHFORMAT_24BIT_INT_Z_8BIT_STENCIL;
break;
default:
fprintf(stderr, "Error: Unsupported depth %d... exiting\n", ctx->Visual.depthBits);
@ -427,14 +427,14 @@ static void r300SetEarlyZState(GLcontext * ctx)
if (ctx->Color.AlphaEnabled && ctx->Color.AlphaFunc != GL_ALWAYS)
/* disable early Z */
r300->hw.zstencil_format.cmd[2] = R300_EARLY_Z_DISABLE;
r300->hw.zstencil_format.cmd[2] = R300_ZTOP_DISABLE;
else {
if (ctx->Depth.Test && ctx->Depth.Func != GL_NEVER)
/* enable early Z */
r300->hw.zstencil_format.cmd[2] = R300_EARLY_Z_ENABLE;
r300->hw.zstencil_format.cmd[2] = R300_ZTOP_ENABLE;
else
/* disable early Z */
r300->hw.zstencil_format.cmd[2] = R300_EARLY_Z_DISABLE;
r300->hw.zstencil_format.cmd[2] = R300_ZTOP_DISABLE;
}
r300->hw.zstencil_format.cmd[3] = 0x00000003;
@ -527,24 +527,24 @@ static void r300SetDepthState(GLcontext * ctx)
r300ContextPtr r300 = R300_CONTEXT(ctx);
R300_STATECHANGE(r300, zs);
r300->hw.zs.cmd[R300_ZS_CNTL_0] &= R300_RB3D_STENCIL_ENABLE;
r300->hw.zs.cmd[R300_ZS_CNTL_0] &= R300_STENCIL_ENABLE; // XXX
r300->hw.zs.cmd[R300_ZS_CNTL_1] &=
~(R300_ZS_MASK << R300_RB3D_ZS1_DEPTH_FUNC_SHIFT);
~(R300_ZS_MASK << R300_Z_FUNC_SHIFT);
if (ctx->Depth.Test && ctx->Depth.Func != GL_NEVER) {
if (ctx->Depth.Mask)
r300->hw.zs.cmd[R300_ZS_CNTL_0] |=
R300_RB3D_Z_TEST_AND_WRITE;
R300_Z_ENABLE | R300_Z_WRITE_ENABLE | R300_STENCIL_FRONT_BACK; // XXX
else
r300->hw.zs.cmd[R300_ZS_CNTL_0] |= R300_RB3D_Z_TEST;
r300->hw.zs.cmd[R300_ZS_CNTL_0] |= R300_Z_ENABLE | R300_STENCIL_FRONT_BACK; // XXX
r300->hw.zs.cmd[R300_ZS_CNTL_1] |=
translate_func(ctx->Depth.
Func) << R300_RB3D_ZS1_DEPTH_FUNC_SHIFT;
Func) << R300_Z_FUNC_SHIFT;
} else {
r300->hw.zs.cmd[R300_ZS_CNTL_0] |= R300_RB3D_Z_DISABLED_1;
r300->hw.zs.cmd[R300_ZS_CNTL_0] |= R300_STENCIL_FRONT_BACK; // XXX
r300->hw.zs.cmd[R300_ZS_CNTL_1] |=
translate_func(GL_NEVER) << R300_RB3D_ZS1_DEPTH_FUNC_SHIFT;
translate_func(GL_NEVER) << R300_Z_FUNC_SHIFT;
}
r300SetEarlyZState(ctx);
@ -558,10 +558,10 @@ static void r300SetStencilState(GLcontext * ctx, GLboolean state)
R300_STATECHANGE(r300, zs);
if (state) {
r300->hw.zs.cmd[R300_ZS_CNTL_0] |=
R300_RB3D_STENCIL_ENABLE;
R300_STENCIL_ENABLE;
} else {
r300->hw.zs.cmd[R300_ZS_CNTL_0] &=
~R300_RB3D_STENCIL_ENABLE;
~R300_STENCIL_ENABLE;
}
} else {
#if R200_MERGED
@ -916,36 +916,36 @@ static void r300StencilFuncSeparate(GLcontext * ctx, GLenum face,
r300ContextPtr rmesa = R300_CONTEXT(ctx);
GLuint refmask =
(((ctx->Stencil.
Ref[0] & 0xff) << ZB_STENCILREFMASK_STENCILREF_SHIFT) | ((ctx->
Stencil.
ValueMask
[0] &
0xff)
<<
ZB_STENCILREFMASK_STENCILMASK_SHIFT));
Ref[0] & 0xff) << R300_STENCILREF_SHIFT) | ((ctx->
Stencil.
ValueMask
[0] &
0xff)
<<
R300_STENCILMASK_SHIFT));
GLuint flag;
R300_STATECHANGE(rmesa, zs);
rmesa->hw.zs.cmd[R300_ZS_CNTL_1] &= ~((R300_ZS_MASK <<
R300_RB3D_ZS1_FRONT_FUNC_SHIFT)
R300_S_FRONT_FUNC_SHIFT)
| (R300_ZS_MASK <<
R300_RB3D_ZS1_BACK_FUNC_SHIFT));
R300_S_BACK_FUNC_SHIFT));
rmesa->hw.zs.cmd[R300_ZS_CNTL_2] &=
~((ZB_STENCILREFMASK_STENCIL_MASK << ZB_STENCILREFMASK_STENCILREF_SHIFT) |
(ZB_STENCILREFMASK_STENCIL_MASK << ZB_STENCILREFMASK_STENCILMASK_SHIFT));
~((R300_STENCILREF_MASK << R300_STENCILREF_SHIFT) |
(R300_STENCILREF_MASK << R300_STENCILMASK_SHIFT));
flag = translate_func(ctx->Stencil.Function[0]);
rmesa->hw.zs.cmd[R300_ZS_CNTL_1] |=
(flag << R300_RB3D_ZS1_FRONT_FUNC_SHIFT);
(flag << R300_S_FRONT_FUNC_SHIFT);
if (ctx->Stencil._TestTwoSide)
flag = translate_func(ctx->Stencil.Function[1]);
rmesa->hw.zs.cmd[R300_ZS_CNTL_1] |=
(flag << R300_RB3D_ZS1_BACK_FUNC_SHIFT);
(flag << R300_S_BACK_FUNC_SHIFT);
rmesa->hw.zs.cmd[R300_ZS_CNTL_2] |= refmask;
}
@ -955,12 +955,12 @@ static void r300StencilMaskSeparate(GLcontext * ctx, GLenum face, GLuint mask)
R300_STATECHANGE(rmesa, zs);
rmesa->hw.zs.cmd[R300_ZS_CNTL_2] &=
~(ZB_STENCILREFMASK_STENCIL_MASK <<
ZB_STENCILREFMASK_STENCILWRITEMASK_SHIFT);
~(R300_STENCILREF_MASK <<
R300_STENCILWRITEMASK_SHIFT);
rmesa->hw.zs.cmd[R300_ZS_CNTL_2] |=
(ctx->Stencil.
WriteMask[0] & ZB_STENCILREFMASK_STENCIL_MASK) <<
ZB_STENCILREFMASK_STENCILWRITEMASK_SHIFT;
WriteMask[0] & R300_STENCILREF_MASK) <<
R300_STENCILWRITEMASK_SHIFT;
}
static void r300StencilOpSeparate(GLcontext * ctx, GLenum face,
@ -971,34 +971,34 @@ static void r300StencilOpSeparate(GLcontext * ctx, GLenum face,
R300_STATECHANGE(rmesa, zs);
/* It is easier to mask what's left.. */
rmesa->hw.zs.cmd[R300_ZS_CNTL_1] &=
(R300_ZS_MASK << R300_RB3D_ZS1_DEPTH_FUNC_SHIFT) |
(R300_ZS_MASK << R300_RB3D_ZS1_FRONT_FUNC_SHIFT) |
(R300_ZS_MASK << R300_RB3D_ZS1_BACK_FUNC_SHIFT);
(R300_ZS_MASK << R300_Z_FUNC_SHIFT) |
(R300_ZS_MASK << R300_S_FRONT_FUNC_SHIFT) |
(R300_ZS_MASK << R300_S_BACK_FUNC_SHIFT);
rmesa->hw.zs.cmd[R300_ZS_CNTL_1] |=
(translate_stencil_op(ctx->Stencil.FailFunc[0]) <<
R300_RB3D_ZS1_FRONT_FAIL_OP_SHIFT)
R300_S_FRONT_SFAIL_OP_SHIFT)
| (translate_stencil_op(ctx->Stencil.ZFailFunc[0]) <<
R300_RB3D_ZS1_FRONT_ZFAIL_OP_SHIFT)
R300_S_FRONT_ZFAIL_OP_SHIFT)
| (translate_stencil_op(ctx->Stencil.ZPassFunc[0]) <<
R300_RB3D_ZS1_FRONT_ZPASS_OP_SHIFT);
R300_S_FRONT_ZPASS_OP_SHIFT);
if (ctx->Stencil._TestTwoSide) {
rmesa->hw.zs.cmd[R300_ZS_CNTL_1] |=
(translate_stencil_op(ctx->Stencil.FailFunc[1]) <<
R300_RB3D_ZS1_BACK_FAIL_OP_SHIFT)
R300_S_BACK_SFAIL_OP_SHIFT)
| (translate_stencil_op(ctx->Stencil.ZFailFunc[1]) <<
R300_RB3D_ZS1_BACK_ZFAIL_OP_SHIFT)
R300_S_BACK_ZFAIL_OP_SHIFT)
| (translate_stencil_op(ctx->Stencil.ZPassFunc[1]) <<
R300_RB3D_ZS1_BACK_ZPASS_OP_SHIFT);
R300_S_BACK_ZPASS_OP_SHIFT);
} else {
rmesa->hw.zs.cmd[R300_ZS_CNTL_1] |=
(translate_stencil_op(ctx->Stencil.FailFunc[0]) <<
R300_RB3D_ZS1_BACK_FAIL_OP_SHIFT)
R300_S_BACK_SFAIL_OP_SHIFT)
| (translate_stencil_op(ctx->Stencil.ZFailFunc[0]) <<
R300_RB3D_ZS1_BACK_ZFAIL_OP_SHIFT)
R300_S_BACK_ZFAIL_OP_SHIFT)
| (translate_stencil_op(ctx->Stencil.ZPassFunc[0]) <<
R300_RB3D_ZS1_BACK_ZPASS_OP_SHIFT);
R300_S_BACK_ZPASS_OP_SHIFT);
}
}
@ -1007,10 +1007,10 @@ static void r300ClearStencil(GLcontext * ctx, GLint s)
r300ContextPtr rmesa = R300_CONTEXT(ctx);
rmesa->state.stencil.clear =
((GLuint) (ctx->Stencil.Clear & ZB_STENCILREFMASK_STENCIL_MASK) |
(ZB_STENCILREFMASK_STENCIL_MASK << ZB_STENCILREFMASK_STENCILMASK_SHIFT) |
((ctx->Stencil.WriteMask[0] & ZB_STENCILREFMASK_STENCIL_MASK) <<
ZB_STENCILREFMASK_STENCILMASK_SHIFT));
((GLuint) (ctx->Stencil.Clear & R300_STENCILREF_MASK) |
(R300_STENCILREF_MASK << R300_STENCILMASK_SHIFT) |
((ctx->Stencil.WriteMask[0] & R300_STENCILREF_MASK) <<
R300_STENCILMASK_SHIFT));
}
/* =============================================================
@ -2287,11 +2287,11 @@ static void r300ResetHwState(r300ContextPtr r300)
if (r300->radeon.sarea->tiling_enabled) {
/* XXX: Turn off when clearing buffers ? */
r300->hw.zb.cmd[R300_ZB_PITCH] |= ZB_DEPTHPITCH_DEPTHMACROTILE_ENABLE;
r300->hw.zb.cmd[R300_ZB_PITCH] |= R300_DEPTHMACROTILE_ENABLE;
if (ctx->Visual.depthBits == 24)
r300->hw.zb.cmd[R300_ZB_PITCH] |=
ZB_DEPTHPITCH_DEPTHMICROTILE_TILED;
R300_DEPTHMICROTILE_TILED;
}
r300->hw.zb_depthclearvalue.cmd[1] = 0;
@ -2546,12 +2546,12 @@ void r300InitState(r300ContextPtr r300)
switch (ctx->Visual.depthBits) {
case 16:
r300->state.depth.scale = 1.0 / (GLfloat) 0xffff;
depth_fmt = ZB_FORMAR_DEPTHFORMAT_16BIT_INT_Z;
depth_fmt = R300_DEPTHFORMAT_16BIT_INT_Z;
r300->state.stencil.clear = 0x00000000;
break;
case 24:
r300->state.depth.scale = 1.0 / (GLfloat) 0xffffff;
depth_fmt = ZB_FORMAR_DEPTHFORMAT_24BIT_INT_Z;
depth_fmt = R300_DEPTHFORMAT_24BIT_INT_Z_8BIT_STENCIL;
r300->state.stencil.clear = 0x00ff0000;
break;
default: