Commit graph

9431 commits

Author SHA1 Message Date
Lionel Landwerlin
9fb9ae5ac6 anv: fix anv_nir_lower_ubo_loads pass
In order to use load_global_const_block_intel we need to ensure the
64bit address in src[0] is uniform. This is not the case in the
vkd3d-proton test_bindless_cbv tests for example.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22624>
2023-04-27 09:08:03 +00:00
Sviatoslav Peleshko
697ed61e7c anv: Improve image/view usage bits verification
This change makes usage bits verification closer to the Vulkan spec.
i.e. VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT does not always require all formats
to support all the requested usage bits.
Also, VK_IMAGE_CREATE_EXTENDED_USAGE_BIT, when combined with
VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT can relax the requirements for the
usage supported by the original image format.

v2: Removed strict verification of the format_list_info formats usage
    per chadversary's suggestion. Other minor style/comments tweaks.

v3: Added checking of all compatible formats when
    VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT and VK_IMAGE_CREATE_EXTENDED_USAGE_BIT
    are specified, but no list of possible formats was given.

v4: Add VK_IMAGE_CREATE_BLOCK_TEXEL_VIEW_COMPATIBLE_BIT handling.

Cc: 22.2 <mesa-stable>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6031
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17182>
2023-04-27 01:04:44 +00:00
Sviatoslav Peleshko
9899151361 anv: Handle UNDEFINED format in image format list
It's not invalid to have this value in the list, but the only case it
is actually valid as format in the creation of an image or image view
is with Android Hardware Buffers which have their format specified
externally.

So we can just ignore all entries with VK_FORMAT_UNDEFINED.

Cc: 22.2 <mesa-stable>
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17182>
2023-04-27 01:04:44 +00:00
Sviatoslav Peleshko
0ed8a48ce9 isl: Check all channels in isl_formats_have_same_bits_per_channel
Cc: 22.2 <mesa-stable>
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17182>
2023-04-27 01:04:44 +00:00
Lionel Landwerlin
5c214117ad intel/tools: add ability to dump out raw kernels data
Useful for debug.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22703>
2023-04-26 10:00:54 +00:00
Mark Janes
acb2a7d2ec intel/dev: report stepping for TGL systems
Workaround 14010672564 requires a check for the TGL B0 stepping.

Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22458>
2023-04-26 02:00:17 +00:00
Mark Janes
47ac056d0f intel/dev: update mesa_defs.json from defect database
These modifications represent:

 * changes to defects made since Feb 16, 2023
 * changes to automated processing of defect state

Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22458>
2023-04-26 02:00:17 +00:00
Tapani Pälli
e501b31e15 anv: implement state cache invalidate for Wa_16013063087
Cc: mesa-stable
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22651>
2023-04-25 10:45:55 +00:00
Tapani Pälli
72fc56aa37 anv: cleanup bitmask construction for PIPELINE_SELECT
Cc: mesa-stable
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22651>
2023-04-25 10:45:55 +00:00
Iván Briano
4cfb4f7d12 anv: support fast color clears on vkCmdClearAttachments
As long as some conditions are met.

Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20175>
2023-04-24 21:33:49 +00:00
Iván Briano
5faf75dd74 anv: expose some helper functions
v2: (Rohan Garg)
- Make set_fast_clear_state take an image and format instead of an iview

Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20175>
2023-04-24 21:33:49 +00:00
Iván Briano
9046319cc9 anv: factor out code for ccs_op and mcs_op
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20175>
2023-04-24 21:33:49 +00:00
Iván Briano
2a67a1f0c2 anv: make anv_can_fast_clear_color_view more generally available
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20175>
2023-04-24 21:33:49 +00:00
Iván Briano
a2e02c4ba4 anv: Remove dead parameters from copy_fast_clear_dwords
There's only one caller of this function and always passes false.

v2: (Nanley Chery)
- Also remove the aspect parameter

v3: (Nanley Chery)
- Rename the function so it's more clear in which direction it works

Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20175>
2023-04-24 21:33:49 +00:00
Sagar Ghuge
e488773b29 anv: Fast clear depth/stencil surface in vkCmdClearAttachments
Instead of doing a slow depth clear, we can do depth fast clear in
vkClearAttachments.

Sascha Willems occlusionquery demo shows more than 2% perf boost with
this series.

On Felix's Tigerlake with the GPU at fixed frequency, this patch
improves performance of RoTR by +0.5%.

v2: (Nanley Chery)
- Clear stencil surface along with depth.
- Check for multilayer resources.
- Lookout for state.attachments.
- Fallback on slow clear for BDW and CHV if conditional rendering
  enabled.
- Keep flush in same function.

v3: (Nanley Chery)
- Return immediately after fast clearing.
- Remove unnecessary comment.

v4: (Nanley Chery)
- Add assertion for BLORP_BATCH_NO_EMIT_DEPTH_STENCIL.
- Remove unnecessary local variable.
- Add 3DSTATE_WM_HZ_OP comment.

v5: (Nanley Chery)
- Fix comments.
- Don't take fast depth clear path if BLORP_BATCH_PREDICATE_ENABLE set.
- Refactor code in can_hiz_clear_att.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20175>
2023-04-24 21:33:49 +00:00
Sagar Ghuge
ee03b30e45 anv: Move and make anv_can_hiz_clear_ds_view non-static
v2:
- Pass const image view param. (Nanley)

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20175>
2023-04-24 21:33:49 +00:00
Sagar Ghuge
e04a414206 anv: Factor out code from anv_image_hiz_clear
Refactoring code from anv_image_hiz_clear which helps in future patches
to support fast depth clear in vkCmdClearAttachments.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20175>
2023-04-24 21:33:48 +00:00
Marcin Ślusarz
aa45b13398 anv: move nir_shader_gather_info to anv_pipeline_nir_preprocess
Fixes dEQP-VK.mesh_shader.ext.misc.custom_attributes*.

Fixes: 16c7c37718 ("anv: move preprocessing of NIR right before compilation")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22629>
2023-04-24 08:43:51 +00:00
Lionel Landwerlin
56840e4c89 anv: rework Wa_14017076903 to only apply with occlusion queries
Fixes KHR-GL46.transform_feedback.* tests with zink+anv on DG2

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: c34916f841 ("anv: implement occlusion query related Wa_14017076903")
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22586>
2023-04-21 12:48:52 +00:00
Jordan Justen
fcb72ffd0c intel/compiler/gfx12.5+: Lower 64-bit cluster_broadcast with 32-bit ops
For MTL (verx10 == 125), float64 is supported, but int64 is not.
Therefore we need to lower cluster broadcast using 32-bit int ops.

For gfx12.5+ platforms that support int64, the register regions
used by cluster broadcast aren't supported by the 64-bit pipeline.

On MTL, dEQP-VK.subgroups.clustered.*_double* and
dEQP-VK.subgroups.clustered.*_dvec* were failing to validate the
compiled shader in debug mode, and reportedly gpu-hanging in release
mode.

With this change dEQP-VK.subgroups.clustered.*_double* passed all 48
tests and dEQP-VK.subgroups.clustered.*_dvec* passed all 140 tests on
MTL.

Rework:
 * Move from generator to brw_fs_lower_regioning.cpp. (Suggested by
   Francisco)
 * Apply to verx10 >= 125.. (Suggested by Francisco)

Cc: 23.1 <mesa-stable>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com> (v1)
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22569>
2023-04-20 11:41:10 -07:00
Lionel Landwerlin
2e2491b76c anv: enable shaderStorageImageReadWithoutFormat on Gfx12.5+
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22552>
2023-04-19 06:04:52 +00:00
Michel Dänzer
73e9cf6062 anv/format: Fix GetPhysicalDeviceSparseImageFormatProperties definition
To match its declaration (and the corresponding definition in Vulkan
headers).

Pointed out by GCC 13:

../src/intel/vulkan/anv_formats.c:1597:6: warning: conflicting types for ‘anv_GetPhysicalDeviceSparseImageFormatProperties’ due to enum/integer mismatch; have ‘void(struct VkPhysicalDevice_T *, VkFormat,  VkImageType,  uint32_t,  VkImageUsageFlags,  VkImageTiling,  uint32_t *, VkSparseImageFormatProperties *)’ {aka ‘void(struct VkPhysicalDevice_T *, VkFormat,  VkImageType,  unsigned int,  unsigned int,  VkImageTiling,  unsigned int *, VkSparseImageFormatProperties *)’} [-Wenum-int-mismatch]
 1597 | void anv_GetPhysicalDeviceSparseImageFormatProperties(
      |      ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
In file included from ../src/intel/vulkan/anv_private.h:123,
                 from ../src/intel/vulkan/anv_formats.c:24:
src/intel/vulkan/anv_entrypoints.h:122:30: note: previous declaration of ‘anv_GetPhysicalDeviceSparseImageFormatProperties’ with type ‘void(struct VkPhysicalDevice_T *, VkFormat,  VkImageType,  VkSampleCountFlagBits,  VkImageUsageFlags,  VkImageTiling,  uint32_t *, VkSparseImageFormatProperties *)’ {aka ‘void(struct VkPhysicalDevice_T *, VkFormat,  VkImageType,  VkSampleCountFlagBits,  unsigned int,  VkImageTiling,  unsigned int *, VkSparseImageFormatProperties *)’}
  122 |   VKAPI_ATTR void VKAPI_CALL anv_GetPhysicalDeviceSparseImageFormatProperties(VkPhysicalDevice physicalDevice, VkFormat format, VkImageType type, VkSampleCountFlagBits samples, VkImageUsageFlags usage, VkImageTiling tiling, uint32_t* pPropertyCount, VkSparseImageFormatProperties* pProperties);
      |                              ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22517>
2023-04-18 09:49:44 +00:00
Lionel Landwerlin
3beaaa9ae8 anv: drop lowered storage images code
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22302>
2023-04-18 08:38:55 +00:00
Lionel Landwerlin
d04d701cc6 intel/nir: add options to storage image lowering
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22302>
2023-04-18 08:38:55 +00:00
Lionel Landwerlin
d4f498a583 isl: fix a number of errors on storage format support on Gfx9/12.5
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22302>
2023-04-18 08:38:55 +00:00
Tapani Pälli
d561bac6bb isl: disable mcs (and mcs+ccs) for color msaa on gfxver 125
Same/similar issues are seen on MTL platform as DG2 so disable for both.

Cc: mesa-stable
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22435>
2023-04-18 07:08:18 +03:00
Lionel Landwerlin
2d4fbb3025 anv: Work around the spec question about pipeline feedback vs GPL.
This gives anv the same behavior as turnip in not asserting, and just not
filling out feedback for those stages.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15637>
2023-04-17 22:43:38 +00:00
Emma Anholt
e433925789 anv: Refactor repeated pipeline creation feedback output code.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15637>
2023-04-17 22:43:37 +00:00
Emma Anholt
647ca81654 anv: Only enable GPL if ANV_GPL=true, or if zink or DXVK are the engine.
Since there are concerns that the VK_EXT_GPL implementation may have
issues with mesh shading, disable it by default but give users a knob to
turn it on to experiment.

This doesn't automatically enable GPL use in zink, because we lack
extendedDynamicState2PatchControlPoints, but it means that you only need
to set ZINK_DEBUG=gpl and not both env vars.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15637>
2023-04-17 22:43:37 +00:00
Lionel Landwerlin
3d49cdb71e anv: implement VK_EXT_graphics_pipeline_library
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15637>
2023-04-17 22:43:37 +00:00
Lionel Landwerlin
0b8a2de2a1 anv: add dynamic buffer offsets support with independent sets
With independent sets, we're not able to compute immediate values for
the index at which to read anv_push_constants::dynamic_offsets to get
the offset of a dynamic buffer. This is because the pipeline layout
may not have all the descriptor set layouts when we compile the
shader.

To solve that issue, we insert a layer of indirection.

This reworks the dynamic buffer offset storage with a 2D array in
anv_cmd_pipeline_state :

   dynamic_offsets[MAX_SETS][MAX_DYN_BUFFERS]

When the pipeline or the dynamic buffer offsets are updated, we
flatten that array into the
anv_push_constants::dynamic_offsets[MAX_DYN_BUFFERS] array.

For shaders compiled with independent sets, the bottom 6 bits of
element X in anv_push_constants::desc_sets[] is used to specify the
base offsets into the anv_push_constants::dynamic_offsets[] for the
set X.

The computation in the shader is now something like :

  base_dyn_buffer_set_idx = anv_push_constants::desc_sets[set_idx] & 0x3f
  dyn_buffer_offset = anv_push_constants::dynamic_offsets[base_dyn_buffer_set_idx + dynamic_buffer_idx]

It was suggested by Faith to use a different push constant buffer with
dynamic_offsets prepared for each stage when using independent sets
instead, but it feels easier to understand this way. And there is some
room for optimization if you are set X and that you know all the sets in
the range [0, X], then you can still avoid the indirection. Separate
push constant allocations per stage do have a CPU cost.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15637>
2023-04-17 22:43:37 +00:00
Lionel Landwerlin
16c7c37718 anv: move preprocessing of NIR right before compilation
For graphics pipelines, we'll need to load NIR for retained shaders.
We want to avoid as much processing as possible while doing that when
we're able to load ISA from cache.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15637>
2023-04-17 22:43:37 +00:00
Lionel Landwerlin
17e7fe9d97 anv: make input attachments available through bindless
With independent sets, we cannot bake into the shader the binding
table entry of input attachments anymore because that final location
is affected by multiple sets.

We can still access them by looking into the descriptor buffer. This
change enables the image handle to be stored in the descriptor buffer.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15637>
2023-04-17 22:43:37 +00:00
Lionel Landwerlin
e82b05dc64 anv: move force shading rate writes checks
With variable fragment shading rate, the last pre-rasterization stage
is responsible to write the shading rate value.

The current checks is as follow :

   If the fragment shader can be dispatched at variable shading rate,
   look for the last pre-raster stage to force the write.

We change this to :

   If we're the last pre-raster stage, force the write.

That way this works for pre-rasterization shaders compiled without a
fragment shader.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15637>
2023-04-17 22:43:37 +00:00
Lionel Landwerlin
b2d3d818d5 anv: introduce a base graphics pipeline object
Pipeline libraries and linked pipelines will inherit from this.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15637>
2023-04-17 22:43:37 +00:00
Lionel Landwerlin
3ca1fdc8b5 isl: don't set inconsistent fields for depth when using stencil only
Since Gfx12+ 3DSTATE_STENCIL_BUFFER gained its own
Width/Depth/Format/etc... fields. So don't set those fields but leave
the address/pitch to 0.

Issue found on simulation.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15637>
2023-04-17 22:43:37 +00:00
José Roberto de Souza
1563210a41 intel/common: Add gt_id to intel_engine_class
MTL and newer platforms on Xe kmd will have engines with gt_id != 0.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22477>
2023-04-17 14:43:06 +00:00
Lionel Landwerlin
a787728906 anv: enable blorp query reset for performance queries
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Felix DeGrood <felix.j.degrood@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22480>
2023-04-15 12:25:57 +03:00
Felix DeGrood
0417cfd7a0 anv: Enable INTEL_MEASURE=cpu
Reviewed-by: Mark Janes <markjanes@swizzler.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21505>
2023-04-14 21:57:50 +00:00
Felix DeGrood
55ba4575be intel: INTEL_MEASURE cpu mode
INTEL_MEASURE normally measures timing of GPU events. However, it
is sometimes useful to instead measure when these gfx API calls
were requested of the driver. INTEL_MEASURE cpu can be used in
in conjunction with other driver debug capabilities, like
INTEL_DEBUG=pc for analyzing stalls/flushes or when debugger is
attached, to track which frame you're currently on or where in
the frame you're at.

Initial commit, without plumbing into anv/iris.

"INTEL_MEASURE=cpu" will collect a cpu timestamp for each
INTEL_MEASURE event instead of GPU timestamps.

Reviewed-by: Mark Janes <markjanes@swizzler.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21505>
2023-04-14 21:57:50 +00:00
Felix DeGrood
c45dee34aa anv: split INTEL_MEASURE multi events
Measure performance of each draw separately in multi_draw event.
Previously, we measured duration of the sum of all draws launched
per multi_draw. This should provide more detailed data for
multi_draws.

Reviewed-by: Mark Janes <markjanes@swizzler.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21505>
2023-04-14 21:57:49 +00:00
Felix DeGrood
50bda45d15 anv: Add flush reason to NEEDS_END_OF_PIPE_SYNC
cs_stall gets inserted if both flushes and invalidates are required.
This cs_stall reason was not called out explicitly, until now.

Reviewed-by: Mark Janes <markjanes@swizzler.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21505>
2023-04-14 21:57:49 +00:00
Felix DeGrood
bdeb849e25 anv: Add flush reasons to raytracing flushes
Reviewed-by: Mark Janes <markjanes@swizzler.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21505>
2023-04-14 21:57:49 +00:00
Felix DeGrood
9a30493ccb anv: Add END_OF_PIPE_SYNC reporting to INTEL_DEBUG=pc
Reviewed-by: Mark Janes <markjanes@swizzler.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21505>
2023-04-14 21:57:49 +00:00
Marcin Ślusarz
cf90be90ad intel: split URB space between task and mesh proportionally to entry sizes
Improves performance by 0.5-2.5% in vk_meshlet_cadscene
depending on the model.

Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22445>
2023-04-14 15:43:50 +00:00
Eric Engestrom
e876a018e9 ci: stop removing -x11 suffix for x11 build of deqp-egl
Makes it clearer which platform is being run.

Signed-off-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: David Heidelberg <david.heidelberg@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Helen Koike <helen.koike@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22450>
2023-04-14 11:28:21 +00:00
Lionel Landwerlin
08cf224c4a intel/vec4: force exec_all on float control instruction
Applying the same rule as the fs backend so that generation code
doesn't assert.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: daa8003e45 ("intel/fs: use nomask for setting cr0 for float controls")
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22473>
2023-04-14 10:54:01 +00:00
Felix DeGrood
0a52002a1c anv: disable reset query pools using blorp opt on MTL
This optimization causes some MTL tests to run forever. Not
yet sure why. Disabling optimization until we have a fix.

Reviewed-by: Mark Janes <markjanes@swizzler.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22373>
2023-04-13 19:35:34 +00:00
Tapani Pälli
b967cbba57 intel/compiler: use intel_needs_workaround for Wa_14012437816
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22437>
2023-04-13 07:33:50 +00:00
Tapani Pälli
ccf16693e1 intel/fs: use intel_needs_workaround for Wa_22013689345
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22437>
2023-04-13 07:33:50 +00:00