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anv: Factor out code from anv_image_hiz_clear
Refactoring code from anv_image_hiz_clear which helps in future patches to support fast depth clear in vkCmdClearAttachments. Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com> Reviewed-by: Nanley Chery <nanley.g.chery@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20175>
This commit is contained in:
Sagar Ghuge
Marge Bot
parent
ae2784b832
commit
e04a414206
1 changed files with 107 additions and 94 deletions
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@ -1194,6 +1194,111 @@ clear_color_attachment(struct anv_cmd_buffer *cmd_buffer,
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}
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}
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static void
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anv_fast_clear_depth_stencil(struct anv_cmd_buffer *cmd_buffer,
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struct blorp_batch *batch,
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const struct anv_image *image,
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VkImageAspectFlags aspects,
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uint32_t level,
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uint32_t base_layer, uint32_t layer_count,
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VkRect2D area, uint8_t stencil_value)
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{
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assert(image->vk.aspects & (VK_IMAGE_ASPECT_DEPTH_BIT |
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VK_IMAGE_ASPECT_STENCIL_BIT));
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struct blorp_surf depth = {};
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if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT) {
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const uint32_t plane =
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anv_image_aspect_to_plane(image, VK_IMAGE_ASPECT_DEPTH_BIT);
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assert(base_layer + layer_count <=
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anv_image_aux_layers(image, VK_IMAGE_ASPECT_DEPTH_BIT, level));
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get_blorp_surf_for_anv_image(cmd_buffer->device,
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image, VK_IMAGE_ASPECT_DEPTH_BIT,
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0, ANV_IMAGE_LAYOUT_EXPLICIT_AUX,
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image->planes[plane].aux_usage, &depth);
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}
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struct blorp_surf stencil = {};
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if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
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const uint32_t plane =
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anv_image_aspect_to_plane(image, VK_IMAGE_ASPECT_STENCIL_BIT);
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get_blorp_surf_for_anv_image(cmd_buffer->device,
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image, VK_IMAGE_ASPECT_STENCIL_BIT,
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0, ANV_IMAGE_LAYOUT_EXPLICIT_AUX,
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image->planes[plane].aux_usage, &stencil);
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}
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/* From the Sky Lake PRM Volume 7, "Depth Buffer Clear":
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*
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* "The following is required when performing a depth buffer clear with
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* using the WM_STATE or 3DSTATE_WM:
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*
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* * If other rendering operations have preceded this clear, a
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* PIPE_CONTROL with depth cache flush enabled, Depth Stall bit
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* enabled must be issued before the rectangle primitive used for
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* the depth buffer clear operation.
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* * [...]"
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*
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* Even though the PRM only says that this is required if using 3DSTATE_WM
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* and a 3DPRIMITIVE, the GPU appears to also need this to avoid occasional
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* hangs when doing a clear with WM_HZ_OP.
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*/
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anv_add_pending_pipe_bits(cmd_buffer,
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ANV_PIPE_DEPTH_CACHE_FLUSH_BIT |
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ANV_PIPE_DEPTH_STALL_BIT,
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"before clear hiz");
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if ((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
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depth.aux_usage == ISL_AUX_USAGE_HIZ_CCS_WT) {
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/* From Bspec 47010 (Depth Buffer Clear):
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*
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* Since the fast clear cycles to CCS are not cached in TileCache,
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* any previous depth buffer writes to overlapping pixels must be
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* flushed out of TileCache before a succeeding Depth Buffer Clear.
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* This restriction only applies to Depth Buffer with write-thru
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* enabled, since fast clears to CCS only occur for write-thru mode.
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*
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* There may have been a write to this depth buffer. Flush it from the
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* tile cache just in case.
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*/
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anv_add_pending_pipe_bits(cmd_buffer,
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ANV_PIPE_DEPTH_CACHE_FLUSH_BIT |
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ANV_PIPE_TILE_CACHE_FLUSH_BIT,
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"before clear hiz_ccs_wt");
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}
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blorp_hiz_clear_depth_stencil(batch, &depth, &stencil,
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level, base_layer, layer_count,
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area.offset.x, area.offset.y,
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area.offset.x + area.extent.width,
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area.offset.y + area.extent.height,
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aspects & VK_IMAGE_ASPECT_DEPTH_BIT,
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ANV_HZ_FC_VAL,
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aspects & VK_IMAGE_ASPECT_STENCIL_BIT,
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stencil_value);
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/* From the SKL PRM, Depth Buffer Clear:
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*
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* "Depth Buffer Clear Workaround
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*
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* Depth buffer clear pass using any of the methods (WM_STATE,
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* 3DSTATE_WM or 3DSTATE_WM_HZ_OP) must be followed by a PIPE_CONTROL
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* command with DEPTH_STALL bit and Depth FLUSH bits “set” before
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* starting to render. DepthStall and DepthFlush are not needed between
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* consecutive depth clear passes nor is it required if the depth-clear
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* pass was done with “full_surf_clear” bit set in the
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* 3DSTATE_WM_HZ_OP."
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*
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* Even though the PRM provides a bunch of conditions under which this is
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* supposedly unnecessary, we choose to perform the flush unconditionally
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* just to be safe.
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*/
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anv_add_pending_pipe_bits(cmd_buffer,
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ANV_PIPE_DEPTH_CACHE_FLUSH_BIT |
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ANV_PIPE_DEPTH_STALL_BIT,
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"after clear hiz");
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}
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static void
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clear_depth_stencil_attachment(struct anv_cmd_buffer *cmd_buffer,
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struct blorp_batch *batch,
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@ -1570,106 +1675,14 @@ anv_image_hiz_clear(struct anv_cmd_buffer *cmd_buffer,
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uint32_t base_layer, uint32_t layer_count,
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VkRect2D area, uint8_t stencil_value)
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{
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assert(image->vk.aspects & (VK_IMAGE_ASPECT_DEPTH_BIT |
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VK_IMAGE_ASPECT_STENCIL_BIT));
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struct blorp_batch batch;
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anv_blorp_batch_init(cmd_buffer, &batch, 0);
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assert((batch.flags & BLORP_BATCH_USE_COMPUTE) == 0);
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struct blorp_surf depth = {};
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if (aspects & VK_IMAGE_ASPECT_DEPTH_BIT) {
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const uint32_t plane =
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anv_image_aspect_to_plane(image, VK_IMAGE_ASPECT_DEPTH_BIT);
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assert(base_layer + layer_count <=
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anv_image_aux_layers(image, VK_IMAGE_ASPECT_DEPTH_BIT, level));
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get_blorp_surf_for_anv_image(cmd_buffer->device,
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image, VK_IMAGE_ASPECT_DEPTH_BIT,
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0, ANV_IMAGE_LAYOUT_EXPLICIT_AUX,
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image->planes[plane].aux_usage, &depth);
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}
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struct blorp_surf stencil = {};
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if (aspects & VK_IMAGE_ASPECT_STENCIL_BIT) {
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const uint32_t plane =
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anv_image_aspect_to_plane(image, VK_IMAGE_ASPECT_STENCIL_BIT);
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get_blorp_surf_for_anv_image(cmd_buffer->device,
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image, VK_IMAGE_ASPECT_STENCIL_BIT,
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0, ANV_IMAGE_LAYOUT_EXPLICIT_AUX,
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image->planes[plane].aux_usage, &stencil);
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}
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/* From the Sky Lake PRM Volume 7, "Depth Buffer Clear":
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*
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* "The following is required when performing a depth buffer clear with
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* using the WM_STATE or 3DSTATE_WM:
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*
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* * If other rendering operations have preceded this clear, a
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* PIPE_CONTROL with depth cache flush enabled, Depth Stall bit
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* enabled must be issued before the rectangle primitive used for
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* the depth buffer clear operation.
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* * [...]"
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*
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* Even though the PRM only says that this is required if using 3DSTATE_WM
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* and a 3DPRIMITIVE, the GPU appears to also need this to avoid occasional
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* hangs when doing a clear with WM_HZ_OP.
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*/
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anv_add_pending_pipe_bits(cmd_buffer,
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ANV_PIPE_DEPTH_CACHE_FLUSH_BIT |
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ANV_PIPE_DEPTH_STALL_BIT,
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"before clear hiz");
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if ((aspects & VK_IMAGE_ASPECT_DEPTH_BIT) &&
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depth.aux_usage == ISL_AUX_USAGE_HIZ_CCS_WT) {
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/* From Bspec 47010 (Depth Buffer Clear):
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*
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* Since the fast clear cycles to CCS are not cached in TileCache,
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* any previous depth buffer writes to overlapping pixels must be
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* flushed out of TileCache before a succeeding Depth Buffer Clear.
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* This restriction only applies to Depth Buffer with write-thru
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* enabled, since fast clears to CCS only occur for write-thru mode.
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*
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* There may have been a write to this depth buffer. Flush it from the
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* tile cache just in case.
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*/
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anv_add_pending_pipe_bits(cmd_buffer,
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ANV_PIPE_DEPTH_CACHE_FLUSH_BIT |
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ANV_PIPE_TILE_CACHE_FLUSH_BIT,
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"before clear hiz_ccs_wt");
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}
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blorp_hiz_clear_depth_stencil(&batch, &depth, &stencil,
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level, base_layer, layer_count,
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area.offset.x, area.offset.y,
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area.offset.x + area.extent.width,
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area.offset.y + area.extent.height,
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aspects & VK_IMAGE_ASPECT_DEPTH_BIT,
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ANV_HZ_FC_VAL,
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aspects & VK_IMAGE_ASPECT_STENCIL_BIT,
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stencil_value);
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anv_fast_clear_depth_stencil(cmd_buffer, &batch, image, aspects, level,
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base_layer, layer_count, area, stencil_value);
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anv_blorp_batch_finish(&batch);
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/* From the SKL PRM, Depth Buffer Clear:
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*
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* "Depth Buffer Clear Workaround
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*
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* Depth buffer clear pass using any of the methods (WM_STATE,
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* 3DSTATE_WM or 3DSTATE_WM_HZ_OP) must be followed by a PIPE_CONTROL
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* command with DEPTH_STALL bit and Depth FLUSH bits “set” before
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* starting to render. DepthStall and DepthFlush are not needed between
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* consecutive depth clear passes nor is it required if the depth-clear
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* pass was done with “full_surf_clear” bit set in the
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* 3DSTATE_WM_HZ_OP."
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*
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* Even though the PRM provides a bunch of conditions under which this is
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* supposedly unnecessary, we choose to perform the flush unconditionally
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* just to be safe.
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*/
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anv_add_pending_pipe_bits(cmd_buffer,
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ANV_PIPE_DEPTH_CACHE_FLUSH_BIT |
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ANV_PIPE_DEPTH_STALL_BIT,
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"after clear hiz");
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}
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void
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