Commit graph

37260 commits

Author SHA1 Message Date
Dave Airlie
9dd92d08a5 softpipe: fix integer texture swizzling for 1 vs 1.0f
The swizzling was putting float one in not integer 1.

This fixes a lot of arb_texture_view-rendering-formats cases.

Reviewed-by: Brian Paul <brianp@vmware.com>
2019-03-22 09:30:35 +10:00
Dave Airlie
aae5ba72ab softpipe: remove shadow_ref assert.
I don't think this really buys us anything and TG4 with cubemap arrays
falls over because sampler == 2, but otherwise works fine.

Fixes:
./bin/textureGather fs shadow r  CubeArray repeat

on softpipe with ARB_gpu_shader5 enabled.

Reviewed-by: Brian Paul <brianp@vmware.com>
2019-03-22 09:30:29 +10:00
Dave Airlie
8dc8b1361a softpipe: handle 32-bit bitfield inserts
Fixes piglits if ARB_gpu_shader5 is enabled

Reviewed-by: Brian Paul <brianp@vmware.com>
2019-03-22 09:30:26 +10:00
Dave Airlie
7b7cb1bc35 softpipe: fix 32-bit bitfield extract
These didn't deal with the width == 32 case that TGSI is defined with.

Fixes piglit tests if ARB_gpu_shader5 is enabled.

Reviewed-by: Brian Paul <brianp@vmware.com>
2019-03-22 09:30:21 +10:00
Eric Anholt
16f2770eb4 v3d: Upload all of UBO[0] if any indirect load occurs.
The idea was that we could skip uploading the constant-indexed uniform
data and just upload the uniforms that are variably-indexed.  However,
since the VS bin and render shaders may have a different set of uniforms
used, this meant that we had to upload the UBO for each of them.  The
first case is generally a fairly small impact (usually the uniform array
is the most space, other than a couple of FSes in shader-db), while the
second is a larger impact: 3DMMES2 was uploading 38k/frame of uniforms
instead of 18k.

Given that the optimization is of dubious value, has a big downside, and
is quite a bit of code, just drop it.  No change in shader-db.  No change
on 3DMMES2 (n=15).
2019-03-21 14:20:50 -07:00
Eric Anholt
320e96bace v3d: Move constant offsets to UBO addresses into the main uniform stream.
We'd end up with the constant offset in the uniform stream anyway, since
they're bigger than small immediates.  Avoids the extra uniforms and adds
in the shader in favor of just adding once on the CPU.

shader-db:
total instructions in shared programs: 6496865 -> 6494851 (-0.03%)
total uniforms in shared programs: 2119511 -> 2117243 (-0.11%)
2019-03-21 14:20:50 -07:00
Eric Anholt
c36d2793ec v3d: Rename v3d_tmu_config_data to v3d_unit_data.
I want to reuse this for encoding small constant UBO/SSBO offsets into the
uniform stream to reduce the extra uniform loads and adds for the small
constant offsets.
2019-03-21 14:20:50 -07:00
Karol Herbst
99f202432b nv50/ir/nir: support gather offsets
v2: only emit offsets if those are !0

Signed-off-by: Karol Herbst <kherbst@redhat.com>
2019-03-21 02:58:41 +00:00
Rafael Antognolli
e7c8402163 iris: Let blorp update the clear color for us.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-03-20 16:46:26 -07:00
Rafael Antognolli
93123417dd iris: Track fast clear color.
v2: Update tracked clear color when we update the surface state.
v3: Update all aux surface states when updating the clear color.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-03-20 16:46:26 -07:00
Rafael Antognolli
5658c661de iris: Stall on the CPU and resolve predication during fast clears.
Only if the clear color/depth is changing. In those cases, it's hard to
keep track of the current clear color, and aux state of some layers,
when predication is enabled. So simplify everything by stalling on the
few cases where we would have a fast clear color change with
predication.

v2:
 - fix comment (Ken)
 - explicitly check for predicate state after resolving it (Ken)

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-03-20 16:46:26 -07:00
Rafael Antognolli
ce830a364e iris: Add iris_resolve_conditional_render().
This function can be used to stall on the CPU and resolve the predicate
for the conditional render. It will convert ice->state.predicate from
IRIS_PREDICATE_STATE_USE_BIT to either IRIS_PREDICATE_STATE_RENDER or
IRIS_PREDICATE_STATE_DONT_RENDER, depending on the result of the query.

v2:
 - return void (Ken)
 - update the stored condition (Ken)
 - simplify the code leading to resolve the predicate (Ken)

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-03-20 16:46:25 -07:00
Rafael Antognolli
131b42f0aa iris: Implement fast clear color.
If all the restrictions are satisfied, do a fast clear instead of
regular clear.

v2:
 - add perf_debug() when we can't fast clear (Ken)
 - improve comment: s/miptree/resource/ (Ken)
 - use swizzle_color_value from blorp (Ken)

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-03-20 16:46:25 -07:00
Rafael Antognolli
7f6344a726 iris: Bring back check for srgb and fast clear color.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-03-20 16:46:25 -07:00
Rafael Antognolli
a8b5ea8ef0 iris: Add function to update clear color in surface state.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-03-20 16:46:25 -07:00
Rafael Antognolli
32c8fa6411 iris: Add helper to convert fast clear color.
It needs to be converted to a value that can be used by ISL (and our
hardware SURFACE_STATE structure).

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-03-20 16:46:25 -07:00
Rafael Antognolli
51638cf18a iris: Fast clear depth buffers.
Check and do a fast clear instead of a regular clear on depth buffers.

v3:
 - remove swith with some cases that we shouldn't wory about (Ken)
 - more parens into the has_hiz check (Ken)

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-03-20 16:46:25 -07:00
Rafael Antognolli
34d00b4410 iris: Use the clear depth when emitting 3DSTATE_CLEAR_PARAMS.
Take the clear depth into account when IRIS_DIRTY_DEPTH_BUFFER is marked
as dirty.

Also update the blorp surface clear color.

v2: Use a single if (zres && zres->aux.bo) (Ken).

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-03-20 16:46:25 -07:00
Rafael Antognolli
37f2692591 iris: Allocate buffer space for the fast clear color.
Also store clear color in the iris_resource.

Always allocate clear color state buffer.

v2:
 - Make clear_color_offset be 64 bits (Ken).
 - Simplify the logic to decide when to memset the aux buffer (Ken).

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-03-20 16:46:25 -07:00
Dave Airlie
04189565a0 softpipe: fix texture view crashes
I noticed we crashed piglit arb_texture_view-rendering-formats
when run on softpipe.

This fixes the clear tiles to use the surface format not the
underlying storage format.

This fixes a bunch of srgb piglits as well.

Fixes: 396ac41fc2 (softpipe: add integer support)

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2019-03-21 05:06:07 +10:00
Kenneth Graunke
3c3f250456 nvc0: Skip new update barrier bits
I added new barrier bits in 220c1dce1e
and made most drivers skip them.  I thought nvc0 was already skipping
those but missed the else case here, which does something.  So make it
explicitly skip like I did everywhere else.

Thanks to Ilia for catching this.

Fixes: 220c1dce1e gallium: Add PIPE_BARRIER_UPDATE_BUFFER and UPDATE_TEXTURE bits.
2019-03-20 10:30:32 -07:00
Kenneth Graunke
220c1dce1e gallium: Add PIPE_BARRIER_UPDATE_BUFFER and UPDATE_TEXTURE bits.
The glMemoryBarrier() function makes shader memory stores ordered with
respect to things specified by the given bits.  Until now, st/mesa has
ignored GL_TEXTURE_UPDATE_BARRIER_BIT and GL_BUFFER_UPDATE_BARRIER_BIT,
saying that drivers should implicitly perform the needed flushing.

This seems like a pretty big assumption to make.  Instead, this commit
opts to translate them to new PIPE_BARRIER bits, and adjusts existing
drivers to continue ignoring them (preserving the current behavior).

The i965 driver performs actions on these memory barriers.  Shader
memory stores go through a "data cache" which is separate from the
render cache and other read caches (like the texture cache).  All
memory barriers need to flush the data cache (to ensure shader memory
stores are visible), and possibly invalidate read caches (to ensure
stale data is no longer visible).  The driver implicitly flushes for
most caches, but not for data cache, since ARB_shader_image_load_store
introduced MemoryBarrier() precisely to order these explicitly.

I would like to follow i965's approach in iris, flushing the data cache
on any MemoryBarrier() call, so I need st/mesa to actually call the
pipe->memory_barrier() callback.

Fixes KHR-GL45.shader_image_load_store.advanced-sync-textureUpdate
and Piglit's spec/arb_shader_image_load_store/host-mem-barrier on
the iris driver.

Roland said this looks reasonable to him.
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-03-19 23:43:33 -07:00
Tapani Pälli
3e534489ec iris: mark switch case fallthrough
CID: 1444103
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-03-20 08:21:50 +02:00
Tapani Pälli
03cbfbd913 iris: initialize num_cbufs
Currently initialized only if 'ish' is non-NULL.

CID: 1444106
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-03-20 08:20:09 +02:00
Daniel Stone
d258b787fa panfrost: Properly align stride
Handle buffers whose width is not aligned to 16px by padding the stride
and storing it accordingly.

This does not reject imports for images whose stride is not sufficiently
aligned.

v2: make sure bo->stride is set on imported buffers, and add missing
variable definition. (Tomeu)

Tested-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-03-20 04:20:42 +00:00
Eric Anholt
17115da6ad v3d: Expose the dma-buf modifiers query.
This allows DRI3 to pick between UIF and raster according to whether we're
pageflipping or not and whether the pageflipping display can do UIF,
avoiding copies for the windowed/composited case that previously was
forced to linear.

Improves windowed glmark2 -b build:use-vbo=false performance by 30.7783%
+/- 13.1719% (n=3)
2019-03-19 08:59:01 -07:00
Eric Anholt
bf6973199d v3d: Allow the UIF modifier with renderonly.
We ask the other side to make a buffer with the right number of pages, and
then just store the UIF in it.  This avoids an extra silent copy of the
buffer from linear to UIF if it gets used for texturing (X11 copy-based
swapbuffers, GL compositors).
2019-03-19 08:54:46 -07:00
Eric Anholt
eb5903a908 v3d: Always lay out shared tiled buffers with UIF_TOP set.
The samplers are already ready for this, we just needed to make sure that
layout chose UIF for level 0.
2019-03-19 08:54:46 -07:00
Rafael Antognolli
76f9ca6cf9 iris: Make intel_hiz_exec public.
Need to use it for fast clearing depth buffers.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-03-18 22:27:02 -07:00
Rafael Antognolli
9c63ec26ea iris: Enable HiZ for multisampled depth surfaces.
Fix this check so that we can get a HiZ aux buffer for multisampled
surfaces as well. Also make sure we don't try to emit a sampler view
surface state for multisampled depth sufaces with HiZ enabled, as
the sampler can't HiZ for multisampled buffers and isl would assert.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-03-18 22:21:30 -07:00
Alyssa Rosenzweig
b98955e128 panfrost: Rewrite varying assembly
There are two stages to varying assembly in the command stream: creating
the varying buffers in the command stream, and creating the varying meta
descriptors (also in the command stream) linked to the aforementioned
buffers. The previous code for this was ad hoc and brittle, making some
invalid assumptions causing unmaintainable workarounds to pile up across
the driver (both compiler and command stream side).

This patch completely rewrites the varying assembly code. There's a
trivial performance penalty (we now memcpy the varying meta to the
command stream on draw, rather than on compile). That said, the
improvement in flexibility and clarity is well-worth it.

The motivator for these changes was support for gl_PointCoord (and
eventually point sprites for legacy GL), which was impossible to
implement with the old varying assembly code.  With the new refactor,
it's super easy; support for gl_PointCoord is included with this patch.

All in all, I'm quite happy with how this turned out.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-03-19 03:55:10 +00:00
Alyssa Rosenzweig
5e6d33a7b6 panfrost: Replay more varying buffers
This is required for gl_PointCoord to show up on decodes.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-03-19 03:53:56 +00:00
Alyssa Rosenzweig
b517e36842 panfrost/decode: Respect primitive size pointers
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-03-19 03:53:48 +00:00
Alyssa Rosenzweig
4f89e4437c panfrost: Disable PIPE_CAP_TGSI_TEXCOORD
I don't know why this was on to begin with...?

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-03-19 03:52:43 +00:00
Alyssa Rosenzweig
7c02c4f114 panfrost: Fix primconvert check
In addition to fixing actual primconvert bugs, this prevents an infinite
loop when trying to draw POINTS.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-03-19 03:52:20 +00:00
Alyssa Rosenzweig
60d5b85261 panfrost: Workaround buffer overrun with mip level
Mipmaps are still broken, but at least this way we don't crash on some
apps using mipmaps.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-03-19 03:50:59 +00:00
Kenneth Graunke
d5974aeeae iris: Slightly better bounds on buffer sizes 2019-03-18 01:39:43 -07:00
Kenneth Graunke
836b47ca4e iris: Don't flush the batch for unsynchronized mappings
I messed this up when adding the GPU copy path.
2019-03-18 01:02:18 -07:00
Brian Paul
f7332fbc08 gallium/util: remove pipe_sampler_view_release()
It's no longer used.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Neha Bhende <bhenden@vmware.com>
Reviewed-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
Reviewed-By: Jose Fonseca <jfonseca@vmware.com>
2019-03-17 20:07:22 -06:00
Brian Paul
c473090b09 i915g: remove calls to pipe_sampler_view_release()
As with previous patches for svga, llvmpipe, swr drivers.
Compile tested only.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Neha Bhende <bhenden@vmware.com>
Reviewed-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
Reviewed-By: Jose Fonseca <jfonseca@vmware.com>
2019-03-17 20:07:22 -06:00
Brian Paul
768b770a86 swr: remove call to pipe_sampler_view_release()
As with svga, llvmpipe drivers in previous patches.
Compile tested only.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Neha Bhende <bhenden@vmware.com>
Reviewed-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
Reviewed-By: Jose Fonseca <jfonseca@vmware.com>
2019-03-17 20:07:22 -06:00
Brian Paul
2ff2a58774 llvmpipe: stop using pipe_sampler_view_release()
This was used to avoid freeing a sampler view which was created by a
context that was already deleted.  But the state tracker does not
allow that.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Neha Bhende <bhenden@vmware.com>
Reviewed-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
Reviewed-By: Jose Fonseca <jfonseca@vmware.com>
2019-03-17 20:07:22 -06:00
Brian Paul
a7afab7952 svga: stop using pipe_sampler_view_release()
This function was used in the past to avoid deleting a sampler view
for a context that no longer exists.  But the Mesa state tracker
ensures that cannot happen.  Use the standard refcounting function
instead.

Also, remove the code which checked for context mis-matches in
svga_sampler_view_destroy().  It's no longer needed since implementing
the zombie sampler view code in the state tracker.

Testing Done: google chrome, variety of GL demos/games

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Neha Bhende <bhenden@vmware.com>
Reviewed-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
Reviewed-By: Jose Fonseca <jfonseca@vmware.com>
2019-03-17 20:07:22 -06:00
Mauro Rossi
bfba0ecc1c android: nouveau: add support for nir
Add the necessary build rules for android, to avoid building errors.

Fixes: f014ae3 ("nouveau: add support for nir")
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
2019-03-18 00:29:39 +01:00
Timothy Arceri
de8ec6e117 radeonsi/nir: call some more var optimisation passes
shader-db results (VEGA64):

Totals from affected shaders:
SGPRS: 5328912 -> 5329680 (0.01 %)
VGPRS: 2969308 -> 2969164 (-0.00 %)
Spilled SGPRs: 37921 -> 37917 (-0.01 %)
Spilled VGPRs: 32882 -> 29024 (-11.73 %)
Private memory VGPRs: 0 -> 0 (0.00 %)
Scratch size: 1400 -> 1200 (-14.29 %) dwords per thread
Code Size: 121126000 -> 121282784 (0.13 %) bytes
LDS: 1501 -> 1501 (0.00 %) blocks
Max Waves: 933188 -> 933229 (0.00 %)
Wait states: 0 -> 0 (0.00 %)

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-03-18 09:29:40 +11:00
Karol Herbst
58376c6b9b nv50ir/nir: move immediates before use
Signed-off-by: Karol Herbst <kherbst@redhat.com>
2019-03-17 17:14:54 +01:00
Karol Herbst
4ded1cdef9 nv50/ir/nir: handle user clip planes for each emitted vertex
v9: convert to C++ style comments
    handle for tess eval shaders as well

Signed-off-by: Karol Herbst <kherbst@redhat.com>
2019-03-17 17:14:21 +01:00
Karol Herbst
b866012f7b nv50/ir/nir: implement intrinsic shader_clock
v9: mark as fixed

Signed-off-by: Karol Herbst <kherbst@redhat.com>
2019-03-17 10:33:28 +01:00
Karol Herbst
c00d45cb45 nv50/ir/nir: implement load_per_vertex_output
v4: use smarter getIndirect helper
    use new getSlotAddress helper
v5: use loadFrom helper
v8: don't require C++11 features

Signed-off-by: Karol Herbst <kherbst@redhat.com>
2019-03-17 10:33:28 +01:00
Karol Herbst
9c44f4e043 nv50/ir/nir: add memory barriers
v5: add more barrier intrinsics

Signed-off-by: Karol Herbst <kherbst@redhat.com>
2019-03-17 10:33:28 +01:00