Based on observations of the generated assembly, this instruction appears to:
- Swizzle the 8/16 component vector in src0 according to the pattern defined in src1.
- Apply a enable mask from src2 to selectively modify elements.
I encountered this instruction while experimenting with _viv_asm and
packed types.
Here is one exmaple kernel:
kernel void k(global int* out, int a, int b) {
_viv_char2_packed s;
_viv_asm(MOV, s.x, s, a);
_viv_asm(MOV, s.y, s, b);
out[0] = s.x + s.y;
}
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33474>
Some cores with the the instruction cache feature, such as the GC3000 found
on the i.MX6QP, have a wrong instruction limit encoded in hardware. The HWDB
entry for this core has the correct number (512). Fixup all cores with the
instruction cache feature to report at least 512 instructions, which was
already assumed when configuring the VS/FS instruction state memory split in
other parts of the driver.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33229>
There is no support for floating point depth formats in etnaviv,
so the clamping can be enabled unconditionally.
Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33140>
For whatever reason NXP decided to call the GC3000 in the i.MX6QP a
GC2000+. This being a lie is marked in the IP core by the upper half
of the revision register being all ones. The kernel driver already
fixes the model and revision when it encounters this core, but this
breaks matching in the HWDB, which uses the bogus model/rev from the
core.
Revert the fixup done by the kernel for the lookup in the HWDB.
Fixes: 2192e620bb ("etnaviv: hwdb: Add etna_query_feature_db(..)")
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33223>
Now that we fill in a dummy state, instead of allowing the FE to
run with undefined state when no vertex attributes are present
we can drop the failures that were caused by this issue.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32947>
Now that the varying use is properly set for color varyings, tests
related to flatshading are fixed.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32922>
We need to add variants of these instructions, which are used with a shadow
samper and passed the shadow reference value via src2.
Fixes: abe5bd35 ("etnaviv: Switch to isa_assemble_instruction(..)")
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32926>
We need to add a variant of the texld instruction, which is used with a shadow
samper and passed the shadow reference value via src2.
Blob generates such texld's for deqp's GLES3.functional.texture.shadow.2d.* (GC3000).
Fixes spec@arb_depth_texture@texdepth.
Fixes: abe5bd35 ("etnaviv: Switch to isa_assemble_instruction(..)")
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32926>
Now that the offset unit is correctly scaled depending on
the depth buffer format, this test can be expected to pass.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32756>
The BO list member is used to track the BO both on the cache bucket list
as well as the zombie list. The BO being on both lists at the same time
is an invalid state. Add some asserts to validate this assumption.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32233>
The BO list member isn't the head/entrypoint for a list, but is only
to be used to link the BO in various lists, so it should not be
initialized as a list head.
Now that the member is properly NULL initialized, we can use the
proper list_is_linked() function to check if the BO is on any
cache bucket or the zombie list.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32233>
Reverse engineered with the following OpenCL kernel:
kernel void add(global float* out, float a, float b) {
float r;
_viv_asm(CLAMP0MAX, r, a, b);
out[0] = r;
}
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31674>
Update to rnndb commit 3e64c80ed98f.
This extends two fields related to vertex attribute and stream
configuration, so they work correctly with the limits exposed
by the GPU.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31594>
This instruction is used to implement float type conversion. The source type
is defined via src1 immed (0: f32, 1: f16) and the dest type is defined via
the instruction type.
Blob generates such conv's for piglit's tests/cl/program/execute/mad-mix.cl
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30797>
Setting it to the same value as (or higher than) the job timeout
effectively bypasses the safety mechanism.
Let's change it to `job timeout - 5min`.
Fixes: f39ffc6911 ("ci/etnaviv: Get the gc2000_piglit manual job mostly working.")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30800>
Create a new stage called etnaviv-postmerge and move the full and manual
jobs over there, to avoid entanglement with the pre-merge jobs.
Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30784>
The ideal place to store the halti value is in struct etna_core_info.
Let's put it there and the determination of it into etna_gpu_new(..).
This makes it possible to reuse the halti level outside of gallium.
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30394>
This bumps the req for everything, but I think that's fine, because one
part restricting to a lower rust version doesn't make much sense as we are
also not doing it generally for C or C++.
This also makes it easier for packagers to know what requires rust.
Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30414>
COARSE clocks add a worst-case jitter of 10ms to the timing, as they
degrade the timing to Linux jiffy accuracy. However, they allow to skip
a syscall on platforms where the accurate version of the clock can not
be accelerated through the VDSO.
Switch to using the COARSE version of the clock when the timeout is
larger than 200ms, i.e. the accuracy of the timeout is degraded less
than 5% by the added worst-case jitter.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27079>
By using the the COARSE variant of the clock we can avoid a syscall
to fetch the current time on platforms where the more accurate
version of the clock can not be accelerated through the VDSO. The
most relevant platform with this restriction is ARM32 without the
architected timer extension, e.g. the NXP i.MX6.
The COARSE clock degrades the accuracy of the timing to Linux
jiffies, which means it adds a worst-case jitter of 10ms, which is
basically noise in relation to the 1sec holding time of the cache
and the irregular call pattern of etna_bo_cache_cleanup().
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27079>
Instead of having a hardcoded list of endian-independent format aliases
in the header, generate them from the format definitions.
Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29649>
Introduce unary and binary versions of the branch instruction. This will
give more ISA_OPC_BRANCH_XXX opcodes to work with. This helps to get rid
of these 'maybe' bitsets and is needed for the assembler.
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30030>
In isaspec the displayname of a bitset defines what is shown in
dissassembly. The assembler only sees this representation and
needs to be able to handle it.
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30030>
