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etnaviv: isa: Rework branch instruction

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Introduce unary and binary versions of the branch instruction. This will
give more ISA_OPC_BRANCH_XXX opcodes to work with. This helps to get rid
of these 'maybe' bitsets and is needed for the assembler.

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30030>
This commit is contained in:
Christian Gmeiner 2024-07-03 17:42:00 +02:00 • committed by Marge Bot
parent b771d2eef6
commit ae3e0ae26a
4 changed files with 66 additions and 38 deletions
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82
src/etnaviv/isa/etnaviv.xml
View file

@ -849,25 +849,15 @@ SPDX-License-Identifier: MIT
({SRC0_USE} != 0) &amp;&amp; ({SRC1_USE} == 0)
</expr>
<bitset name="#instruction-cf-maybe-src0-src1" extends="#instruction-cf">
<bitset name="#instruction-cf-src0" extends="#instruction-cf">
<meta valid_srcs="0"/>
<display>
{INSTR_CF} {:align=18}void, void, void, {TARGET}
{INSTR_CF} {:align=18}void, {SRC0}, void, {TARGET}
</display>
<override expr="#instruction-has-src0-src1">
<display>
{INSTR_CF} {:align=18}void, {SRC0}, {SRC1}, {TARGET}
</display>
</override>
<override expr="#instruction-has-src0">
<display>
{INSTR_CF} {:align=18}void, {SRC0}, void, {TARGET}
</display>
</override>
<!-- SRC0 -->
<field name="SRC0_USE" pos="43" type="bool"/>
<pattern pos="43">1</pattern> <!-- SRC0_USE -->
<field name="SRC0_REG" low="44" high="52" type="uint"/>
<field name="SRC0" low="54" high="63" type="#instruction-src">
<param name="SRC0_REG" as="SRC_REG"/>
@ -877,16 +867,44 @@ SPDX-License-Identifier: MIT
<field name="SRC0_AMODE" low="64" high="66" type="#reg_addressing_mode"/>
<field name="SRC0_RGROUP" low="67" high="69" type="#reg_group"/>
<!-- SRC1 -->
<field name="SRC1_USE" pos="70" type="bool"/>
<field name="SRC1_REG" low="71" high="79" type="uint"/>
<field name="SRC1" low="81" high="90" type="#instruction-src">
<param name="SRC1_REG" as="SRC_REG"/>
<param name="SRC1_AMODE" as="SRC_AMODE"/>
<param name="SRC1_RGROUP" as="SRC_RGROUP"/>
</field>
<field name="SRC1_AMODE" low="91" high="93" type="#reg_addressing_mode"/>
<field name="SRC1_RGROUP" low="96" high="98" type="#reg_group"/>
<!-- SRC1 -->
<pattern pos="70">0</pattern> <!-- SRC1_USE -->
<pattern low="71" high="79">000000000</pattern> <!-- SRC1_REG -->
<pattern low="81" high="88">00000000</pattern> <!-- SRC1_SWIZ -->
<pattern pos="89">0</pattern> <!-- SRC1_NEG -->
<pattern pos="90">0</pattern> <!-- SRC1_ABS -->
<pattern low="91" high="93">000</pattern> <!-- SRC1_AMODE -->
<pattern low="96" high="98">000</pattern> <!-- SRC1_RGROUP -->
</bitset>
<bitset name="#instruction-cf-src0-src1" extends="#instruction-cf">
<meta valid_srcs="0|1"/>
<display>
{INSTR_CF} {:align=18}void, {SRC0}, {SRC1}, {TARGET}
</display>
<!-- SRC0 -->
<pattern pos="43">1</pattern> <!-- SRC0_USE -->
<field name="SRC0_REG" low="44" high="52" type="uint"/>
<field name="SRC0" low="54" high="63" type="#instruction-src">
<param name="SRC0_REG" as="SRC_REG"/>
<param name="SRC0_AMODE" as="SRC_AMODE"/>
<param name="SRC0_RGROUP" as="SRC_RGROUP"/>
</field>
<field name="SRC0_AMODE" low="64" high="66" type="#reg_addressing_mode"/>
<field name="SRC0_RGROUP" low="67" high="69" type="#reg_group"/>
<!-- SRC1 -->
<pattern pos="70">1</pattern> <!-- SRC1_USE -->
<field name="SRC1_REG" low="71" high="79" type="uint"/>
<field name="SRC1" low="81" high="90" type="#instruction-src">
<param name="SRC1_REG" as="SRC_REG"/>
<param name="SRC1_AMODE" as="SRC_AMODE"/>
<param name="SRC1_RGROUP" as="SRC_RGROUP"/>
</field>
<field name="SRC1_AMODE" low="91" high="93" type="#reg_addressing_mode"/>
<field name="SRC1_RGROUP" low="96" high="98" type="#reg_group"/>
</bitset>
<bitset name="#left-shift" size="2">
@ -1142,7 +1160,17 @@ SPDX-License-Identifier: MIT
<pattern pos="80">0</pattern> <!-- OPCODE_BIT6 -->
</bitset>
<bitset name="branch" extends="#instruction-cf-maybe-src0-src1">
<bitset name="branch" extends="#instruction-cf-no-src">
<pattern low="0" high="5">010110</pattern> <!-- OPC -->
<pattern pos="80">0</pattern> <!-- OPCODE_BIT6 -->
</bitset>
<bitset name="branch_unary" extends="#instruction-cf-src0" displayname="branch">
<pattern low="0" high="5">010110</pattern> <!-- OPC -->
<pattern pos="80">0</pattern> <!-- OPCODE_BIT6 -->
</bitset>
<bitset name="branch_binary" extends="#instruction-cf-src0-src1" displayname="branch">
<pattern low="0" high="5">010110</pattern> <!-- OPC -->
<pattern pos="80">0</pattern> <!-- OPCODE_BIT6 -->
</bitset>
@ -1195,7 +1223,7 @@ SPDX-License-Identifier: MIT
<pattern pos="80">0</pattern> <!-- OPCODE_BIT6 -->
</bitset>
<bitset name="branch_any" extends="#instruction-cf-maybe-src0-src1">
<bitset name="branch_any" extends="#instruction-cf-src0-src1">
<pattern low="0" high="5">100100</pattern> <!-- OPC -->
<pattern pos="80">0</pattern> <!-- OPCODE_BIT6 -->
</bitset>

18
src/etnaviv/isa/tests/disasm.cpp
View file

@ -150,7 +150,7 @@ INSTANTIATE_TEST_SUITE_P(Opcodes, DisasmTest,
disasm_state{ {0x00801021, 0x00000004, 0x00000000, 0x00000008}, "sqrt t0.x___, void, void, t0.xxxx\n" },
disasm_state{ {0x03001022, 0x00000005, 0x00000000, 0x00154008}, "sin.rtz t0.zy, void, void, t0.yyyy\n" },
disasm_state{ {0x01801023, 0x00000005, 0x00000000, 0x00000008}, "cos.rtz t0.xy__, void, void, t0.xxxx\n" },
disasm_state{ {0x000001a4, 0x3e401804, 0x500000c0, 0x00000487}, "branch_any.ne.s32 void, t1.yzww, 1, 9\t; dontcare bits in branch_any: 00000000000000000000000400000000\n", FLAG_FAILING_PARSE | FLAG_FAILING_ASM},
disasm_state{ {0x000001a4, 0x3e401804, 0x500000c0, 0x00000487}, "branch_any.ne.s32 void, t1.yzww, 1, 9\t; dontcare bits in branch_any: 00000000000000000000000400000000\n", FLAG_FAILING_ASM},
disasm_state{ {0x00801025, 0x00000004, 0x00000000, 0x00000008}, "floor t0.x___, void, void, t0.xxxx\n"},
disasm_state{ {0x00801026, 0x00000004, 0x00000000, 0x00000008}, "ceil t0.x___, void, void, t0.xxxx\n"},
disasm_state{ {0x00801027, 0x00000004, 0x00000000, 0x00000008}, "sign t0.x___, void, void, t0.xxxx\n" },
@ -206,13 +206,13 @@ INSTANTIATE_TEST_SUITE_P(Branch, DisasmTest,
testing::Values(
// taken from deqp2 run on GC2000
disasm_state{ {0x00000016, 0x00000000, 0x00000000, 0x00001080}, "branch void, void, void, 33\n"},
disasm_state{ {0x00000056, 0x00000800, 0x000000d0, 0x00000280}, "branch.gt void, u0.xxxx, t1.xxxx, 5\n", FLAG_FAILING_PARSE | FLAG_FAILING_ASM},
disasm_state{ {0x00000056, 0x00000800, 0x000000d0, 0x00000280}, "branch.gt void, u0.xxxx, t1.xxxx, 5\n", FLAG_FAILING_PARSE | FLAG_FAILING_ASM},
disasm_state{ {0x00000096, 0x15402800, 0x00000040, 0x00000082}, "branch.lt void, t2.yyyy, u0.xxxx, 1\n", FLAG_FAILING_PARSE | FLAG_FAILING_ASM},
disasm_state{ {0x000000d6, 0x00001800, 0x01540250, 0x00000980}, "branch.ge void, u1.xxxx, t4.zzzz, 19\n", FLAG_FAILING_PARSE | FLAG_FAILING_ASM},
disasm_state{ {0x00000116, 0x3fc01800, 0x000000c0, 0x00000482}, "branch.le void, t1.wwww, u1.xxxx, 9\n", FLAG_FAILING_PARSE | FLAG_FAILING_ASM},
disasm_state{ {0x00000156, 0x39001800, 0x000002c0, 0x00001282}, "branch.eq void, t1.xyzw, u5.xxxx, 37\n", FLAG_FAILING_PARSE | FLAG_FAILING_ASM},
disasm_state{ {0x00000196, 0x15401800, 0x00aa0040, 0x00000382}, "branch.ne void, t1.yyyy, u0.yyyy, 7\n", FLAG_FAILING_PARSE | FLAG_FAILING_ASM}
disasm_state{ {0x00000056, 0x00000800, 0x000000d0, 0x00000280}, "branch.gt void, u0.xxxx, t1.xxxx, 5\n"},
disasm_state{ {0x00000056, 0x00000800, 0x000000d0, 0x00000280}, "branch.gt void, u0.xxxx, t1.xxxx, 5\n"},
disasm_state{ {0x00000096, 0x15402800, 0x00000040, 0x00000082}, "branch.lt void, t2.yyyy, u0.xxxx, 1\n"},
disasm_state{ {0x000000d6, 0x00001800, 0x01540250, 0x00000980}, "branch.ge void, u1.xxxx, t4.zzzz, 19\n"},
disasm_state{ {0x00000116, 0x3fc01800, 0x000000c0, 0x00000482}, "branch.le void, t1.wwww, u1.xxxx, 9\n"},
disasm_state{ {0x00000156, 0x39001800, 0x000002c0, 0x00001282}, "branch.eq void, t1.xyzw, u5.xxxx, 37\n"},
disasm_state{ {0x00000196, 0x15401800, 0x00aa0040, 0x00000382}, "branch.ne void, t1.yyyy, u0.yyyy, 7\n"}
)
);
// clang-format on
@ -329,7 +329,7 @@ INSTANTIATE_TEST_SUITE_P(TFShader, DisasmTest,
disasm_state{ {0x01831009, 0x00000000, 0x00000000, 0x00150008}, "mov.pack t3.xy__, void, void, t0.xyyy\n"},
disasm_state{ {0x03841009, 0x00000000, 0x00000000, 0x00290008}, "mov.pack t4.xyz_, void, void, t0.xyzz\n"},
disasm_state{ {0x0201102d, 0x00000800, 0x40000010, 0x00000000}, "i2f.s32.pack t1.__z_, u0.xxxx, void, void\n"},
disasm_state{ {0x00000156, 0x2a801800, 0x01540040, 0x00000402}, "branch.eq void, t1.zzzz, u0.zzzz, 8\n", FLAG_FAILING_PARSE | FLAG_FAILING_ASM},
disasm_state{ {0x00000156, 0x2a801800, 0x01540040, 0x00000402}, "branch.eq void, t1.zzzz, u0.zzzz, 8\n"},
disasm_state{ {0x0081100c, 0x3fc00800, 0x400100d0, 0x20154008}, "imadlo0.s32.pack t1.x___, u0.wwww, t1.xxxx, u0.yyyy\n"},
disasm_state{ {0x07820033, 0x00001800, 0x01540040, 0x0039002a}, "store.pack mem, t1.xxxx, u0.zzzz, t2.xyzw\t; dontcare bits in store: 00000000000000000000000000020000\n", FLAG_FAILING_ASM}
)

2
src/gallium/drivers/etnaviv/etnaviv_compiler_nir.c
View file

@ -1245,7 +1245,7 @@ etna_compile_shader(struct etna_shader_variant *v)
uint32_t *code = MALLOC(c->inst_ptr * 16);
for (unsigned i = 0; i < c->inst_ptr; i++) {
struct etna_inst *inst = &c->code[i];
if (inst->opcode == ISA_OPC_BRANCH)
if (inst->opcode == ISA_OPC_BRANCH || inst->opcode == ISA_OPC_BRANCH_UNARY || inst->opcode == ISA_OPC_BRANCH_BINARY)
inst->imm = block_ptr[inst->imm];
etna_assemble(&code[i * 4], inst, specs->has_no_oneconst_limit);

2
src/gallium/drivers/etnaviv/etnaviv_compiler_nir_emit.c
View file

@ -233,7 +233,7 @@ etna_emit_jump(struct etna_compile *c, unsigned block, struct etna_inst_src cond
}
struct etna_inst inst = {
.opcode = ISA_OPC_BRANCH,
.opcode = ISA_OPC_BRANCH_UNARY,
.cond = ISA_COND_NOT,
.type = ISA_TYPE_U32,
.src[0] = condition,