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etnaviv: isa: Add swizzle instruction

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Based on observations of the generated assembly, this instruction appears to:
 - Swizzle the 8/16 component vector in src0 according to the pattern defined in src1.
 - Apply a enable mask from src2 to selectively modify elements.

I encountered this instruction while experimenting with _viv_asm and
packed types.

Here is one exmaple kernel:

kernel void k(global int* out, int a, int b) {
  _viv_char2_packed s;

  _viv_asm(MOV, s.x, s, a);
  _viv_asm(MOV, s.y, s, b);

  out[0] = s.x + s.y;
}

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33474>
This commit is contained in:
Christian Gmeiner 2024-10-04 14:35:47 +02:00 • committed by Marge Bot
parent 96887a5ec1
commit e1cc8ffd5f
2 changed files with 27 additions and 1 deletions
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11
src/etnaviv/isa/etnaviv.xml
View file

@ -1275,7 +1275,16 @@ SPDX-License-Identifier: MIT
<pattern pos="80">0</pattern> <!-- OPCODE_BIT6 -->
</bitset>
<!-- swizzle -->
<bitset name="swizzle" extends="#instruction-alu-src0-src1-src2">
<doc>
Based on observations of the generated assembly, this instruction appears to:
- Swizzle the 8/16 component vector in src0 according to the pattern defined in src1.
- Apply a enable mask from src2 to selectively modify elements.
</doc>
<pattern low="0" high="5">101011</pattern> <!-- OPC -->
<pattern pos="80">0</pattern> <!-- OPCODE_BIT6 -->
</bitset>
<bitset name="i2i" extends="#instruction-alu-src0-src1">
<pattern low="0" high="5">101100</pattern> <!-- OPC -->

17
src/etnaviv/isa/tests/disasm.cpp
View file

@ -155,6 +155,7 @@ INSTANTIATE_TEST_SUITE_P(Opcodes, DisasmTest,
disasm_state{ {0x00801026, 0x00000004, 0x00000000, 0x00000008}, "ceil t0.x___, void, void, t0.xxxx\n"},
disasm_state{ {0x00801027, 0x00000004, 0x00000000, 0x00000008}, "sign t0.x___, void, void, t0.xxxx\n" },
disasm_state{ {0x0000002a, 0x00000000, 0x00000000, 0x00000000}, "barrier void, void, void, void\n" },
disasm_state{ {0x0787102b, 0x39202804, 0xc0a802c0, 0x781fdffa}, "swizzle.u8 t7, t2.xyzw, u5.xyyy, 65535\n", FLAG_FAILING_ASM },
disasm_state{ {0x0080102c, 0x00200804, 0x50001040, 0x00000007}, "i2i.s16 t0.x___, t0.xxxx, 32, void\n" },
disasm_state{ {0x0381102d, 0x00201804, 0x40000000, 0x00000000}, "i2f.s16 t1.xyz_, t1.xxxx, void, void\n"},
disasm_state{ {0x0101102e, 0x00201804, 0x80000020, 0x00002000}, "f2i.u32.t0 t1._y__, th1.xxxx, void, void\n"},
@ -381,3 +382,19 @@ INSTANTIATE_TEST_SUITE_P(ShadowSampler, DisasmTest,
)
);
// clang-format on
// clang-format off
INSTANTIATE_TEST_SUITE_P(SwizzleVariants, DisasmTest,
testing::Values(
// seen on GC7000
disasm_state{ {0x0782102b, 0x00000804, 0xa000007c ,0x7800001f}, "swizzle.s8 t2, 0, 0, 1\n", FLAG_FAILING_ASM },
disasm_state{ {0x0782102b, 0x00002804, 0xa0000040, 0x7800002f}, "swizzle.s8 t2, t2.xxxx, 0, 2\n", FLAG_FAILING_ASM },
disasm_state{ {0x0780102b, 0x00002804, 0xa0000040, 0x7800001f}, "swizzle.s8 t0, t2.xxxx, 0, 1\n", FLAG_FAILING_ASM },
disasm_state{ {0x0781102b, 0x00002804, 0xa00000c0, 0x7800001f}, "swizzle.s8 t1, t2.xxxx, 1, 1\n", FLAG_FAILING_ASM },
disasm_state{ {0x0781102b, 0x00200804, 0x6000007e, 0x7800003f}, "swizzle.s16 t1, 0.000000, 0, 3\n", FLAG_FAILING_ASM },
disasm_state{ {0x0781102b, 0x00201804, 0x60000040, 0x780000cf}, "swizzle.s16 t1, t1.xxxx, 0, 12\n", FLAG_FAILING_ASM },
disasm_state{ {0x0780102b, 0x00201804, 0x60000040, 0x7800003f}, "swizzle.s16 t0, t1.xxxx, 0, 3\n", FLAG_FAILING_ASM },
disasm_state{ {0x0781102b, 0x00202804, 0x600000c0, 0x7800003f}, "swizzle.s16 t1, t2.xxxx, 1, 3\n", FLAG_FAILING_ASM }
)
);
// clang-format on