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etnaviv: drm: fix instruction limit for cores with instruction cache

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Some cores with the the instruction cache feature, such as the GC3000 found
on the i.MX6QP, have a wrong instruction limit encoded in hardware. The HWDB
entry for this core has the correct number (512). Fixup all cores with the
instruction cache feature to report at least 512 instructions, which was
already assumed when configuring the VS/FS instruction state memory split in
other parts of the driver.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33229>
This commit is contained in:
Lucas Stach 2025-01-26 21:50:06 +01:00 • committed by Marge Bot
parent 5c44d70684
commit 992e9d07c5
2 changed files with 10 additions and 4 deletions
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8
src/etnaviv/drm/etnaviv_gpu.c
View file

@ -259,6 +259,14 @@ struct etna_gpu *etna_gpu_new(struct etna_device *dev, unsigned int core)
if (!core_info_okay) {
query_features_from_kernel(gpu);
query_limits_from_kernel(gpu);
/* GC3000 with the instruction cache feature has a incorrect instruction
* limit encoded in HW (HWDB has the correct number). Fix this up so
* other parts of the stack don't have to worry about this.
*/
if (etna_core_has_feature(&gpu->info, ETNA_FEATURE_INSTRUCTION_CACHE) &&
gpu->info.gpu.max_instructions < 512)
gpu->info.gpu.max_instructions = 512;
}
determine_halti(gpu);

6
src/gallium/drivers/etnaviv/etnaviv_screen.c
View file

@ -870,10 +870,8 @@ etna_get_specs(struct etna_screen *screen)
screen->specs.has_icache = true;
} else if (VIV_FEATURE(screen, ETNA_FEATURE_INSTRUCTION_CACHE)) {
/* GC3000 - this core is capable of loading shaders from
* memory. It can also run shaders from registers, as a fallback, but
* "max_instructions" does not have the correct value. It has place for
* 2*256 instructions just like GC2000, but the offsets are slightly
* different.
* memory. It can also run shaders from registers as a fallback, but the
* offsets are slightly different.
*/
screen->specs.vs_offset = 0xC000;
/* State 08000-0C000 mirrors 0C000-0E000, and the Vivante driver uses