Commit graph

15991 commits

Author SHA1 Message Date
Leder, Brendan Steve
9751b52a10 amd/vpelib: Update chip headers
Tested with corresponding test cases.

Reviewed-by: Roy Chan <Roy.Chan@amd.com>
Reviewed-by: Jesse Agate <Jesse.Agate@amd.com>
Acked-by: Chih-Wei Chien <Chih-Wei.Chien@amd.com>
Signed-off-by: Brendan Leder: <breleder@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31693>
2024-10-18 05:56:36 +00:00
Chan, Roy
c252d22e91 amd/vpelib: Fix compilation warnings
Reviewed-by: Navid Assadian <Navid.Assadian@amd.com>
Acked-by: Chih-Wei Chien <Chih-Wei.Chien@amd.com>
Signed-off-by: Roy Chan <roy.chan@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31693>
2024-10-18 05:56:36 +00:00
Leder, Brendan Steve
ab9bd6b932 amd/vpelib: Generalize visual confirm handling
Generalize the visual confirm handling through helper function with
minor coding style changes

Reviewed-by: Evan Damphousse <evan.damphousse@amd.com>
Reviewed-by: Roy Chan <Roy.Chan@amd.com>
Acked-by: Chih-Wei Chien <Chih-Wei.Chien@amd.com>
Signed-off-by: Brendan Leder <breleder@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31693>
2024-10-18 05:56:36 +00:00
Leder, Brendan Steve
257658cbca amd/vpelib: Fix backend bug for multiple instances
Fix potential duplicated config if config_writer_complete is called
multiple times

Reviewed-by: Roy Chan <Roy.Chan@amd.com>
Reviewed-by: Evan Damphousse <evan.damphousse@amd.com>
Acked-by: Chih-Wei Chien <Chih-Wei.Chien@amd.com>
Signed-off-by: Brendan Leder <BrendanSteve.Leder@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31693>
2024-10-18 05:56:36 +00:00
Hsieh, Mike
b010a2eaf6 amd/vpelib: Refactor 3D LUT code
Refactor 3D LUT code and tested with corresponding test cases

Reviewed-by: Roy Chan <Roy.Chan@amd.com>
Acked-by: Chih-Wei Chien <Chih-Wei.Chien@amd.com>
Signed-off-by: Mike Hsieh <Mike.Hsieh@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31693>
2024-10-18 05:56:36 +00:00
Brendan
338dd3b687 amd/vpelib: Fix duplicate config writer bug
[WHY]
Config writer duplicates packets when switching pipes.

[HOW]
Update config writer to only write new packets if new type is required.

[TESTING]
Tested with corresponding test cases.

Reviewed-by: Roy Chan <Roy.Chan@amd.com>
Acked-by: Chih-Wei Chien <Chih-Wei.Chien@amd.com>
Signed-off-by: Brendan Leder <breleder@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31693>
2024-10-18 05:56:36 +00:00
Jiali
8fa10461c9 amd/vpelib: Enhance output format capabilities
- Generalize the p2b programming to support chroma viewport if any
- Turn vpe_get_element_size_in_bytes to a global helper function

Reviewed-by: Jesse Agate <Jesse.Agate@amd.com>
Acked-by: Chih-Wei Chien <Chih-Wei.Chien@amd.com>
Signed-off-by: Jiali <jiali.zhao@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31693>
2024-10-18 05:56:36 +00:00
Guilherme Gallo
024bf6330f ci/amd: Reassign radv-raven-traces from zork to dalboz
With the addition of the radeonsi-raven-cdna-lower-image:x86_64 job,
zork devices are being overutilized.

To balance the load, we're moving the radv-raven-traces job to dalboz,
where one DUT per pipeline remains available.

Signed-off-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31699>
2024-10-18 03:27:46 +00:00
Guilherme Gallo
72659d04e6 ci/amd: Track merge-skips.txt changes
Signed-off-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31699>
2024-10-18 03:27:46 +00:00
Guilherme Gallo
9930e46fca ci/radv: Rebalance stoney-vkcts
- Increase the fraction for radv-stoney-vkcts from 15 to 18.
- Same for radv-angle, from 2 to 3

The last one should take around 7 minutes, but this new 3 minute gap can
be filled in by the ~95% DUT availability and eventual infra retries.

Signed-off-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31699>
2024-10-18 03:27:45 +00:00
Samuel Pitoiset
0f2363993d radv: fix emitting DB_RENDER_OVERRIDE on GFX12
This register is already set in the GFX12 preamble and it shouldn't
be overwritten.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31690>
2024-10-18 00:28:02 +00:00
Samuel Pitoiset
daefd280e2 radv do not force-disable hierarchical stencil testing
Looks like this was disabled by mistake. RadeonSI relies on the default
value which is "no force" and PAL only sets this to FORCE_DISABLE when
HTILE is completely disabled using settings.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31690>
2024-10-18 00:28:01 +00:00
Georg Lehmann
aabadb30fc aco/print_ir: use parse_depctr_wait
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31132>
2024-10-17 11:16:16 +00:00
Georg Lehmann
ced7a01954 aco/statistics: update branch issue cycles
Foz-DB Navi31:
Totals from 14319 (18.04% of 79395) affected shaders:
Instrs: 20064495 -> 20062876 (-0.01%)
CodeSize: 105334568 -> 105327704 (-0.01%)

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31132>
2024-10-17 11:16:16 +00:00
Georg Lehmann
ec11cfc69d aco/insert_delay_alu: do not delay lane mask fast forwarding
The delay actually hurts performance in this case.

Foz-DB Navi31:
Totals from 30340 (38.21% of 79395) affected shaders:
Instrs: 30778999 -> 30726605 (-0.17%); split: -0.17%, +0.00%
CodeSize: 162380180 -> 162170808 (-0.13%); split: -0.13%, +0.00%
Latency: 228185562 -> 228186976 (+0.00%); split: -0.00%, +0.00%
InvThroughput: 39001151 -> 39000897 (-0.00%); split: -0.00%, +0.00%

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31132>
2024-10-17 11:16:16 +00:00
Georg Lehmann
e4889fd4b5 aco/insert_delay_alu: consider more implicit waits
Foz-DB Navi31:
Totals from 37961 (47.81% of 79395) affected shaders:
Instrs: 34175286 -> 33978599 (-0.58%)
CodeSize: 180059352 -> 179190076 (-0.48%); split: -0.48%, +0.00%
Latency: 259826196 -> 259798474 (-0.01%); split: -0.01%, +0.00%
InvThroughput: 42792700 -> 42789298 (-0.01%); split: -0.01%, +0.00%

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31132>
2024-10-17 11:16:16 +00:00
Georg Lehmann
840b5841d3 aco: do not track ALU delay across jumps
This assumes that the best case jump latency is higher than the worst case
ALU latency.

Foz-DB Navi31:
Totals from 17720 (22.32% of 79395) affected shaders:
Instrs: 26009663 -> 25929989 (-0.31%); split: -0.31%, +0.00%
CodeSize: 136571496 -> 136254420 (-0.23%); split: -0.23%, +0.00%
Latency: 215731308 -> 215722059 (-0.00%); split: -0.01%, +0.00%
InvThroughput: 36534197 -> 36532070 (-0.01%); split: -0.01%, +0.00%

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31132>
2024-10-17 11:16:16 +00:00
Georg Lehmann
977f435f4c aco/ir: add function to parse depctr waits
No Foz-DB changes on Navi31.

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31132>
2024-10-17 11:16:16 +00:00
Georg Lehmann
dbf63a0788 nir: remove nir_op_is_derivative
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31014>
2024-10-17 09:50:19 +00:00
Georg Lehmann
cba575f4df nir: always emit ddx intrinsics
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31014>
2024-10-17 09:50:19 +00:00
Daniel Stone
400694c7c6 ci: Disable trace jobs using old Wine
The radv-raven and lavapipe trace jobs were using Wine installed from
Debian. lavapipe had a single post-merge trace running, and raven had
all but one trace disabled due to being flaky.

b2c is using Proton instead, and it makes absolutely no sense to have
two parallel versions of Wine installed. These should be brought back at
some point running on the same version of Wine as the newer b2c jobs.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31595>
2024-10-16 22:52:44 +00:00
Eric Engestrom
01285a1da4 ci: drop spec@egl_ext_surface_compression@create from the rest of the expected fails
Fixes: 68aa78a858 ("Uprev Piglit to 7ce69da1199d12ed0ddaa251ed489750523798fb")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31691>
2024-10-16 20:40:18 +00:00
Samuel Pitoiset
17dc91709d radv: use radv_normalize_blend_factor() more
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31688>
2024-10-16 18:24:22 +00:00
Samuel Pitoiset
38e12dd53c radv: optimize breaking batch when CB_TARGET_MASK change
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31688>
2024-10-16 18:24:22 +00:00
Samuel Pitoiset
fc52c6358c radv: stop recomputing the viewport xform for guarband/viewport
It's already computed when viewports are bound.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31680>
2024-10-16 16:10:12 +00:00
Konstantin Seurer
0098f8ef35 radv: Remap 10 and 12 bit formats to 16 bit formats
Preserves the previous behavior while handling the new formats.

Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30821>
2024-10-16 14:30:15 +00:00
Leder, Brendan Steve
bd6f3e30f2 amd/vpelib: Fix output_ctx gamma curve cache bug
[Why]
Reprogramming gamma curve unnecessary and wastes power/time.

[How]
Bool array checked instead of bool inside said array, add index.

[Testing]
Tested with corresponding test cases.

Reviewed-by: Roy Chan <Roy.Chan@amd.com>
Reviewed-by: Krunoslav Kovac <Krunoslav.Kovac@amd.com>
Acked-by: Chih-Wei Chien <Chih-Wei.Chien@amd.com>
Signed-off-by: Brendan Leder <breleder@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31605>
2024-10-16 02:30:17 +00:00
Jude Shih
259b44d97b amd/vpelib: Restructure CDC FE/BE
[Why]
CDC has two separate functionalities : backend and frontend.
split them into two for better resource management.

Reviewed-by: Roy Chan <Roy.Chan@amd.com>
Acked-by: Chih-Wei Chien <Chih-Wei.Chien@amd.com>
Signed-off-by: Jude Shih <shenshih@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31605>
2024-10-16 02:30:17 +00:00
Roy Chan
0d7f51724b amd/vpelib: Add documentation
Reviewed-by: Navid Assadian <navid.assadian@amd.com>
Acked-by: Chih-Wei Chien <Chih-Wei.Chien@amd.com>
Signed-off-by: Roy Chan <roy.chan@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31605>
2024-10-16 02:30:17 +00:00
Brendan
5826ef5e44 amd/vpelib: Visual confirm on input
[Why]
The gap pointer should advance if it is used.
Not a functional bug fix but a nice-to-have change.

[How]
Advancing the pointer once the memory is used

Reviewed-by: Jesse Agate <Jesse.Agate@amd.com>
Acked-by: Chih-Wei Chien <Chih-Wei.Chien@amd.com>
Signed-off-by: Brendan <brendanSteve.leder@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31605>
2024-10-16 02:30:17 +00:00
Assadian, Navid
a0d2f074cd amd/vpelib: Add mirror & rotation capability check function for vpe1.1
Reviewed-by: Roy Chan <Roy.Chan@amd.com>
Acked-by: Chih-Wei Chien <Chih-Wei.Chien@amd.com>
Signed-off-by: Navid Assadian <navid.assadian@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31605>
2024-10-16 02:30:16 +00:00
Brendan
af01d7a181 amd/vpelib: Update configs to be per-pipe specific
[Why]
config settings should be per pipe in concept

[How]
update the framework to store configs per pipe

Reviewed-by: Roy Chan <Roy.Chan@amd.com>
Acked-by: Chih-Wei Chien <Chih-Wei.Chien@amd.com>
Signed-off-by: Brendan <brendanSteve.leder@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31605>
2024-10-16 02:30:16 +00:00
Assadian, Navid
6a68af7d21 amd/vpelib: Add better rotation and mirror capability check
Add a general rotation and mirror support check support.

Reviewed-by: Roy Chan <Roy.Chan@amd.com>
Acked-by: Chih-Wei Chien <Chih-Wei.Chien@amd.com>
Signed-off-by: Navid Assadian <navid.assadian@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31605>
2024-10-16 02:30:16 +00:00
Evan
3ef8e6a6ae amd/vpelib: Luma AND Color Keyer Full Support
[New]
- Added new vpe_stream params for color keying
- Added new struct in dpp to capture keying params
- Added new capability for color keying
- Added keying support in vpe1.0

[Updated]
- Updated capability check
- Updated Luma and Color Keying functions to better implement the entire feature
- Updated resource to map stream params -> dpp keyer param

Reviewed-by: Roy Chan <Roy.Chan@amd.com>
Acked-by: Chih-Wei Chien <Chih-Wei.Chien@amd.com>
Signed-off-by: Evan <evan.damphousse@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31605>
2024-10-16 02:30:16 +00:00
Assadian, Navid
338760d9b5 amd/vpelib: Document public API structures
Doxygen style inline comments are added to the public API functions and
structures.

Reviewed-by: Roy Chan <Roy.Chan@amd.com>
Acked-by: Chih-Wei Chien <Chih-Wei.Chien@amd.com>
Signed-off-by: Navid Assadian <navid.assadian@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31605>
2024-10-16 02:30:16 +00:00
Brendan
ded1a2b3f0 amd/vpelib: Multiple instance support in caching framework
Generalize the caching to work with multiple instances of objects.
Change some static functions to public functions to maximize function
re-use possibilities.

Reviewed-by: Roy Chan <Roy.Chan@amd.com>
Acked-by: Chih-Wei Chien <Chih-Wei.Chien@amd.com>
Signed-off-by: Brendan <brendanSteve.leder@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31605>
2024-10-16 02:30:16 +00:00
Evan
7a293a812a amd/vpelib: Color Keyer Implementation
[New] - New color keyer function. Take input from VPE_STREAM and FORMAT, program - Added color keyer call in Front end - Hard code Alpha Keyer Range to be entire range - Added vpe_is_yuv() to determine if input format is any YUV format. Combines existing functions - Set Per-pixel Alpha in vpelib when stream.enable_luma_key=1

[Updated]
- Updated the macros to include the luma_key field
- Updated vpe10 and resource calls to have mathching function calls
- removed unused data structure for keying mode since hard code keyer mode to 0x3 in real world
- Updated Luma Key enum to properly represent reg spec

[Removed]
- Removed unused alpha keyer struct. Opted to take in directly from stream_ctx

Reviewed-by: Brendan Steve Leder <brendanSteve.leder@amd.com>
Acked-by: Chih-Wei Chien <Chih-Wei.Chien@amd.com>
Signed-off-by: Evan <evan.damphousse@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31605>
2024-10-16 02:30:16 +00:00
Georg Lehmann
40c4ec881d radv: call nir_opt_remove_phis in radv_optimize_nir_algebraic
Foz-DB Navi31:
Totals from 3048 (3.84% of 79395) affected shaders:
Instrs: 603535 -> 599281 (-0.70%); split: -0.74%, +0.03%
CodeSize: 3074416 -> 3056236 (-0.59%); split: -0.60%, +0.01%
Latency: 2851382 -> 2849808 (-0.06%); split: -0.07%, +0.01%
InvThroughput: 294247 -> 294201 (-0.02%); split: -0.02%, +0.01%
SClause: 18077 -> 18083 (+0.03%); split: -0.03%, +0.07%
Copies: 63860 -> 59926 (-6.16%); split: -6.33%, +0.17%
Branches: 15901 -> 15899 (-0.01%)
PreSGPRs: 62441 -> 61353 (-1.74%)
VALU: 291049 -> 291035 (-0.00%); split: -0.01%, +0.00%
SALU: 96786 -> 92606 (-4.32%); split: -4.42%, +0.10%

Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31360>
2024-10-15 10:01:43 +00:00
Marek Olšák
02923e237d nir: add hole_size parameter into the vectorize callback
It will be used to allow merging loads with a hole between them.

Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29398>
2024-10-15 05:50:24 +00:00
David Heidelberg
d14d3c5bdd amd: Pass addrlib cpp args to the tests
The declaration and definition used by tests otherwise differs from
addrlib.
Found by LTO -Werror=lto-type-mismatch.

Fixes: 1d69c0419b ("amd/addrlib: prevent defining regparm differently")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: David Heidelberg <david@ixit.cz>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31613>
2024-10-14 16:52:31 +00:00
Samuel Pitoiset
03b4477c8f radv: fix returning non-zero captured address without binding
The Vulkan spec says:
    "If the buffer was created with a non-zero value of
    VkBufferOpaqueCaptureAddressCreateInfo::opaqueCaptureAddress or
    VkBufferDeviceAddressCreateInfoEXT::deviceAddress, the return
    value will be the same address that was returned at capture time."

My interpretation is that you can get the buffer device address before
binding if you passed a non-zero address during buffer creation. The
returned BDA would be similar if a memory object is bound to the
buffer later.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31145>
2024-10-14 07:37:00 +00:00
Bas Nieuwenhuizen
c8c354d9c3 radv: Disable EXT BDA capture and replay.
Spec allows calling VkBufferGetDeviceAddressInfo without binding to memory:

VUID-VkBufferDeviceAddressInfo-buffer-02600
If buffer is non-sparse and was not created with the VK_BUFFER_CREATE_DEVICE_ADDRESS_CAPTURE_REPLAY_BIT flag, then it must be bound completely and contiguously to a single VkDeviceMemory object

Which  we can only do by making it sparse unconditionally, which feels very wrong to me for a capture & replay extension as that significantly impacts execution.

Current theory is that this was only intended for the EXT and not the core functionality. As such, let's disable capture using the EXT.

Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31140>
2024-10-11 22:17:33 +00:00
Konstantin Seurer
d975d23cd8 radv/meta: Do not pass NULL to vk_texcompress_astc_finish
The pointer can be NULL if initialization fails.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/11953
Fixes: f97b449 ("radv: integrate meta astc compute decoder to radv")
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31505>
2024-10-11 20:56:21 +00:00
Samuel Pitoiset
583b93f7a2 radv: rename 'gfx' to 'main' in the DGC path
It can be confusing because the main DGC IB can be executed either on
GFX or ACE compute queues.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31583>
2024-10-10 15:52:51 +00:00
Rhys Perry
33eb2d7fe4 aco: skip uniformization of certain merge phis
If a source is a VGPR, then skip if it's safe. This fixes the regressions
from the previous commit.

fossil-db (navi31):
Totals from 5118 (6.45% of 79395) affected shaders:
MaxWaves: 159560 -> 159520 (-0.03%); split: +0.01%, -0.03%
Instrs: 2165351 -> 2138456 (-1.24%); split: -1.26%, +0.02%
CodeSize: 11260340 -> 11152460 (-0.96%); split: -0.98%, +0.02%
VGPRs: 218124 -> 225144 (+3.22%); split: -0.13%, +3.35%
Latency: 11059208 -> 11116102 (+0.51%); split: -0.18%, +0.69%
InvThroughput: 1252148 -> 1230193 (-1.75%); split: -1.77%, +0.01%
VClause: 39513 -> 39518 (+0.01%); split: -0.48%, +0.49%
SClause: 59434 -> 59378 (-0.09%); split: -0.11%, +0.02%
Copies: 165997 -> 156172 (-5.92%); split: -6.68%, +0.76%
PreSGPRs: 181203 -> 181094 (-0.06%)
PreVGPRs: 139393 -> 139731 (+0.24%)
VALU: 1244301 -> 1220769 (-1.89%); split: -1.91%, +0.02%
SALU: 200240 -> 199567 (-0.34%); split: -0.34%, +0.00%

fossil-db (navi21):
Totals from 35520 (44.74% of 79395) affected shaders:
MaxWaves: 951870 -> 951830 (-0.00%)
Instrs: 20229388 -> 20227776 (-0.01%); split: -0.01%, +0.00%
CodeSize: 105379916 -> 105513740 (+0.13%); split: -0.01%, +0.13%
VGPRs: 1375232 -> 1375400 (+0.01%)
Latency: 81046435 -> 81013986 (-0.04%); split: -0.04%, +0.00%
InvThroughput: 15269166 -> 15273295 (+0.03%); split: -0.01%, +0.04%
VClause: 354314 -> 354310 (-0.00%); split: -0.00%, +0.00%
SClause: 417049 -> 417047 (-0.00%); split: -0.00%, +0.00%
Copies: 1699445 -> 1699488 (+0.00%); split: -0.01%, +0.01%
Branches: 591274 -> 591269 (-0.00%); split: -0.00%, +0.00%
PreSGPRs: 1371062 -> 1370567 (-0.04%)
PreVGPRs: 1100716 -> 1100953 (+0.02%)
VALU: 11076189 -> 11075167 (-0.01%); split: -0.01%, +0.00%
SALU: 3648002 -> 3647378 (-0.02%); split: -0.02%, +0.00%

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30211>
2024-10-10 14:59:27 +00:00
Rhys Perry
ce33ffd03a aco: ensure phis uniformized by divergence analysis are SGPR
Otherwise, they might not actually be uniform when divergence analysis
claimed they are.

fossil-db (navi31):
Totals from 5118 (6.45% of 79395) affected shaders:
MaxWaves: 159520 -> 159560 (+0.03%); split: +0.03%, -0.01%
Instrs: 2138456 -> 2165351 (+1.26%); split: -0.02%, +1.28%
CodeSize: 11152460 -> 11260340 (+0.97%); split: -0.02%, +0.98%
VGPRs: 225144 -> 218124 (-3.12%); split: -3.25%, +0.13%
Latency: 11116102 -> 11059208 (-0.51%); split: -0.69%, +0.18%
InvThroughput: 1230193 -> 1252148 (+1.78%); split: -0.01%, +1.80%
VClause: 39518 -> 39513 (-0.01%); split: -0.49%, +0.48%
SClause: 59378 -> 59434 (+0.09%); split: -0.02%, +0.11%
Copies: 156172 -> 165997 (+6.29%); split: -0.81%, +7.10%
PreSGPRs: 181094 -> 181203 (+0.06%)
PreVGPRs: 139731 -> 139393 (-0.24%)
VALU: 1220769 -> 1244301 (+1.93%); split: -0.02%, +1.95%
SALU: 199567 -> 200240 (+0.34%); split: -0.00%, +0.34%

fossil-db (navi21):
Totals from 35520 (44.74% of 79395) affected shaders:
MaxWaves: 951830 -> 951870 (+0.00%)
Instrs: 20227773 -> 20229388 (+0.01%); split: -0.00%, +0.01%
CodeSize: 105513724 -> 105379916 (-0.13%); split: -0.13%, +0.01%
VGPRs: 1375400 -> 1375232 (-0.01%)
Latency: 81013985 -> 81046435 (+0.04%); split: -0.00%, +0.04%
InvThroughput: 15273291 -> 15269166 (-0.03%); split: -0.04%, +0.01%
VClause: 354310 -> 354314 (+0.00%); split: -0.00%, +0.00%
SClause: 417047 -> 417049 (+0.00%); split: -0.00%, +0.00%
Copies: 1699486 -> 1699445 (-0.00%); split: -0.01%, +0.01%
Branches: 591269 -> 591274 (+0.00%); split: -0.00%, +0.00%
PreSGPRs: 1370567 -> 1371062 (+0.04%)
PreVGPRs: 1100953 -> 1100716 (-0.02%)
VALU: 11075164 -> 11076189 (+0.01%); split: -0.00%, +0.01%
SALU: 3647378 -> 3648002 (+0.02%); split: -0.00%, +0.02%

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30211>
2024-10-10 14:59:26 +00:00
Rhys Perry
67ad7359ff nir/divergence_analysis: disable phi undef optimization by default
If the backend does not implement this too, or some other future transform
modifiess the phi so that this isn't the case (replace the phi with a
bcsel or replace undef with zero), then it will not actually be uniform.

This keeps it enabled to some degree for RADV/ACO.

fossil-db (navi31):
Totals from 76 (0.10% of 79395) affected shaders:
Instrs: 195008 -> 195282 (+0.14%)
CodeSize: 1012592 -> 1015884 (+0.33%)
Latency: 3892826 -> 3898843 (+0.15%); split: -0.00%, +0.15%
InvThroughput: 460681 -> 460964 (+0.06%)
Copies: 13508 -> 13516 (+0.06%)
Branches: 5244 -> 5412 (+3.20%)
PreVGPRs: 5092 -> 5096 (+0.08%)
VALU: 116177 -> 116197 (+0.02%)
SALU: 23449 -> 23785 (+1.43%)

fossil-db (navi21):
Totals from 76 (0.10% of 79395) affected shaders:
Instrs: 164471 -> 164981 (+0.31%)
CodeSize: 883988 -> 888420 (+0.50%)
Latency: 4074287 -> 4082043 (+0.19%)
InvThroughput: 783783 -> 784276 (+0.06%); split: -0.00%, +0.06%
Branches: 5262 -> 5430 (+3.19%)
PreVGPRs: 5100 -> 5104 (+0.08%)
VALU: 116375 -> 116381 (+0.01%)
SALU: 23589 -> 23925 (+1.42%)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30211>
2024-10-10 14:59:26 +00:00
Samuel Pitoiset
2643c48700 radv/amdgpu: remove unused code about external IBs in the submit path
Now that everything is chained, the driver no longer uses external IBs.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30809>
2024-10-10 14:08:39 +00:00
Samuel Pitoiset
d686ba36a9 radv/amdgpu: simplify cs_execute_ib()
It's only used for executing IB2 on GFX.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30809>
2024-10-10 14:08:39 +00:00
Samuel Pitoiset
c1b2cb6ef7 radv: implement IB chaining for DGC when it's executed on compute
The IB2 packet is only supported on the graphics queue. To execute DGC
IB on compute, the previous solution was to submit it separately
without any chaining. Though this solution was incomplete because it's
easy to reach the maximum number of IBs per submit when there is a lot
of ExecuteIndirect() calls.

To fix that, the proposed solution is to implement DGC IB chaining when
it's executed on the compute only. The idea is to add a trailer that is
added at the beginning of the DGC IB (to know the offset). This trailer
is used to chain back back the DGC IB to a normal CS, it's patched at
execution time. Patching is fine because it's not allowed to execute
the same DGC IB concurrently and the entire solution relies on that.

When the DGC IB is executed on graphics, the trailer isn't patched and
it only contains NOPs padding. Performance should be mostly similar.

This fixes
dEQP-VK.dgc.nv.compute.misc.execute_many_*_primary_cmd_compute_queue.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30809>
2024-10-10 14:08:39 +00:00