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amd/vpelib: Update chip headers

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Tested with corresponding test cases.

Reviewed-by: Roy Chan <Roy.Chan@amd.com>
Reviewed-by: Jesse Agate <Jesse.Agate@amd.com>
Acked-by: Chih-Wei Chien <Chih-Wei.Chien@amd.com>
Signed-off-by: Brendan Leder: <breleder@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31693>
This commit is contained in:
Leder, Brendan Steve 2024-09-20 11:17:02 -04:00 • committed by Marge Bot
parent c252d22e91
commit 9751b52a10
2 changed files with 10 additions and 9 deletions
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17
src/amd/vpelib/src/chip/vpe10/inc/vpe10_dpp.h
View file

@ -234,7 +234,6 @@ extern "C" {
SFRB(RECOUT_HEIGHT, VPDSCL_RECOUT_SIZE, post_fix), \
SFRB(VPMPC_WIDTH, VPMPC_SIZE, post_fix), SFRB(VPMPC_HEIGHT, VPMPC_SIZE, post_fix), \
SFRB(ALPHA_EN, VPLB_DATA_FORMAT, post_fix), \
SFRB(MEMORY_CONFIG, VPLB_MEMORY_CTRL, post_fix), \
SFRB(LB_MAX_PARTITIONS, VPLB_MEMORY_CTRL, post_fix), \
SFRB(LB_NUM_PARTITIONS, VPLB_MEMORY_CTRL, post_fix), \
SFRB(LB_NUM_PARTITIONS_C, VPLB_MEMORY_CTRL, post_fix), \
@ -388,15 +387,9 @@ extern "C" {
SFRB(VPCM_DEALPHA_ABLND, VPCM_DEALPHA, post_fix), \
SFRB(VPCM_BIAS_FORMAT, VPCM_COEF_FORMAT, post_fix), \
SFRB(VPCM_POST_CSC_COEF_FORMAT, VPCM_COEF_FORMAT, post_fix), \
SFRB(VPDPP_CLOCK_ENABLE, VPDPP_CONTROL, post_fix), \
SFRB(VPECLK_G_GATE_DISABLE, VPDPP_CONTROL, post_fix), \
SFRB(VPECLK_G_DYN_GATE_DISABLE, VPDPP_CONTROL, post_fix), \
SFRB(VPECLK_G_VPDSCL_GATE_DISABLE, VPDPP_CONTROL, post_fix), \
SFRB(VPECLK_R_GATE_DISABLE, VPDPP_CONTROL, post_fix), \
SFRB(DISPCLK_R_GATE_DISABLE, VPDPP_CONTROL, post_fix), \
SFRB(DISPCLK_G_GATE_DISABLE, VPDPP_CONTROL, post_fix), \
SFRB(VPDPP_FGCG_REP_DIS, VPDPP_CONTROL, post_fix), \
SFRB(VPDPP_TEST_CLK_SEL, VPDPP_CONTROL, post_fix), \
SFRB(VPDPP_CRC_EN, VPDPP_CRC_CTRL, post_fix), \
SFRB(VPDPP_CRC_CONT_EN, VPDPP_CRC_CTRL, post_fix), \
SFRB(VPDPP_CRC_420_COMP_SEL, VPDPP_CRC_CTRL, post_fix), \
@ -424,7 +417,15 @@ extern "C" {
SFRB(VPCM_GAMUT_REMAP_C32, VPCM_GAMUT_REMAP_C31_C32, post_fix), \
SFRB(VPCM_GAMUT_REMAP_C33, VPCM_GAMUT_REMAP_C33_C34, post_fix), \
SFRB(VPCM_GAMUT_REMAP_C34, VPCM_GAMUT_REMAP_C33_C34, post_fix), \
SFRB(VPCM_GAMUT_REMAP_COEF_FORMAT, VPCM_COEF_FORMAT, post_fix)
SFRB(VPCM_GAMUT_REMAP_COEF_FORMAT, VPCM_COEF_FORMAT, post_fix), \
SFRB(MEMORY_CONFIG, VPLB_MEMORY_CTRL, post_fix), \
SFRB(VPECLK_G_DYN_GATE_DISABLE, VPDPP_CONTROL, post_fix), \
SFRB(VPECLK_R_GATE_DISABLE, VPDPP_CONTROL, post_fix), \
SFRB(DISPCLK_R_GATE_DISABLE, VPDPP_CONTROL, post_fix), \
SFRB(DISPCLK_G_GATE_DISABLE, VPDPP_CONTROL, post_fix), \
SFRB(VPDPP_TEST_CLK_SEL, VPDPP_CONTROL, post_fix), \
SFRB(VPDPP_CLOCK_ENABLE, VPDPP_CONTROL, post_fix)
#define DPP_REG_VARIABLE_LIST_VPE10_COMMON \
reg_id_val VPCNVC_SURFACE_PIXEL_FORMAT; \

2
src/amd/vpelib/src/chip/vpe10/inc/vpe10_mpc.h
View file

@ -184,7 +184,6 @@ extern "C" {
#define MPC_FIELD_LIST_VPE10_COMMON(post_fix) \
SFRB(VPECLK_R_GATE_DISABLE, VPMPC_CLOCK_CONTROL, post_fix), \
SFRB(VPMPC_TEST_CLK_SEL, VPMPC_CLOCK_CONTROL, post_fix), \
SFRB(VPMPCC0_SOFT_RESET, VPMPC_SOFT_RESET, post_fix), \
SFRB(VPMPC_SFR0_SOFT_RESET, VPMPC_SOFT_RESET, post_fix), \
SFRB(VPMPC_SFT0_SOFT_RESET, VPMPC_SOFT_RESET, post_fix), \
@ -579,6 +578,7 @@ extern "C" {
#define MPC_FIELD_LIST_VPE10(post_fix) \
MPC_FIELD_LIST_VPE10_COMMON(post_fix), \
SFRB(VPMPC_TEST_CLK_SEL, VPMPC_CLOCK_CONTROL, post_fix), \
SFRB(VPMPCC_BG_BPC, VPMPCC_CONTROL, post_fix), \
SFRB(VPMPCC_GLOBAL_ALPHA, VPMPCC_CONTROL, post_fix), \
SFRB(VPMPCC_GLOBAL_GAIN, VPMPCC_CONTROL, post_fix), \