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radv: rename 'gfx' to 'main' in the DGC path

Browse source 
It can be confusing because the main DGC IB can be executed either on
GFX or ACE compute queues.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31583>
This commit is contained in:
Samuel Pitoiset 2024-10-09 17:08:46 -04:00 • committed by Marge Bot
parent 33eb2d7fe4
commit 583b93f7a2
3 changed files with 16 additions and 16 deletions
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8
src/amd/vulkan/radv_cmd_buffer.c
View file

@ -11598,13 +11598,13 @@ radv_dgc_execute_ib(struct radv_cmd_buffer *cmd_buffer, const VkGeneratedCommand
struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
const bool has_task_shader = radv_dgc_with_task_shader(pGeneratedCommandsInfo);
const uint32_t cmdbuf_size = radv_get_indirect_gfx_cmdbuf_size(pGeneratedCommandsInfo);
const uint32_t cmdbuf_size = radv_get_indirect_main_cmdbuf_size(pGeneratedCommandsInfo);
const uint64_t ib_va =
radv_buffer_get_va(prep_buffer->bo) + prep_buffer->offset + pGeneratedCommandsInfo->preprocessOffset;
const uint64_t gfx_trailer_va = ib_va + radv_get_indirect_gfx_trailer_offset(pGeneratedCommandsInfo);
const uint64_t gfx_ib_va = ib_va + radv_get_indirect_gfx_cmdbuf_offset(pGeneratedCommandsInfo);
const uint64_t main_trailer_va = ib_va + radv_get_indirect_main_trailer_offset(pGeneratedCommandsInfo);
const uint64_t main_ib_va = ib_va + radv_get_indirect_main_cmdbuf_offset(pGeneratedCommandsInfo);
device->ws->cs_chain_dgc_ib(cmd_buffer->cs, gfx_ib_va, cmdbuf_size >> 2, gfx_trailer_va,
device->ws->cs_chain_dgc_ib(cmd_buffer->cs, main_ib_va, cmdbuf_size >> 2, main_trailer_va,
cmd_buffer->state.predicating);
if (has_task_shader) {

18
src/amd/vulkan/radv_device_generated_commands.c
View file

@ -420,19 +420,19 @@ radv_get_indirect_trailer_offset(const VkGeneratedCommandsInfoNV *cmd_info, enum
}
uint32_t
radv_get_indirect_gfx_cmdbuf_offset(const VkGeneratedCommandsInfoNV *cmd_info)
radv_get_indirect_main_cmdbuf_offset(const VkGeneratedCommandsInfoNV *cmd_info)
{
return radv_get_indirect_cmdbuf_offset(cmd_info, AMD_IP_GFX);
}
uint32_t
radv_get_indirect_gfx_cmdbuf_size(const VkGeneratedCommandsInfoNV *cmd_info)
radv_get_indirect_main_cmdbuf_size(const VkGeneratedCommandsInfoNV *cmd_info)
{
return radv_get_indirect_cmdbuf_size(cmd_info, AMD_IP_GFX);
}
uint32_t
radv_get_indirect_gfx_trailer_offset(const VkGeneratedCommandsInfoNV *cmd_info)
radv_get_indirect_main_trailer_offset(const VkGeneratedCommandsInfoNV *cmd_info)
{
return radv_get_indirect_trailer_offset(cmd_info, AMD_IP_GFX);
}
@ -1043,7 +1043,7 @@ build_dgc_buffer_tail(nir_builder *b, nir_def *cmd_buf_offset, nir_def *cmd_buf_
}
static void
build_dgc_buffer_tail_gfx(nir_builder *b, nir_def *sequence_count, const struct radv_device *device)
build_dgc_buffer_tail_main(nir_builder *b, nir_def *sequence_count, const struct radv_device *device)
{
nir_def *cmd_buf_offset = load_param32(b, cmd_buf_main_offset);
nir_def *cmd_buf_size = dgc_cmd_buf_size(b, sequence_count, false, device);
@ -1103,7 +1103,7 @@ build_dgc_buffer_trailer(nir_builder *b, nir_def *cmd_buf_offset, unsigned trail
}
static void
build_dgc_buffer_trailer_gfx(nir_builder *b, const struct radv_device *device)
build_dgc_buffer_trailer_main(nir_builder *b, const struct radv_device *device)
{
nir_def *cmd_buf_offset = nir_imm_int(b, 0);
const unsigned trailer_size = radv_dgc_trailer_cmdbuf_size(device, AMD_IP_GFX);
@ -1159,7 +1159,7 @@ build_dgc_buffer_preamble(nir_builder *b, nir_def *cmd_buf_preamble_offset, nir_
}
static void
build_dgc_buffer_preamble_gfx(nir_builder *b, nir_def *sequence_count, const struct radv_device *device)
build_dgc_buffer_preamble_main(nir_builder *b, nir_def *sequence_count, const struct radv_device *device)
{
nir_def *cmd_buf_preamble_offset = load_param32(b, cmd_buf_preamble_offset);
nir_def *cmd_buf_main_offset = load_param32(b, cmd_buf_main_offset);
@ -2095,7 +2095,7 @@ build_dgc_prepare_shader(struct radv_device *dev, struct radv_indirect_command_l
sequence_count = nir_load_var(&b, count_var);
build_dgc_buffer_trailer_gfx(&b, dev);
build_dgc_buffer_trailer_main(&b, dev);
nir_push_if(&b, nir_ult(&b, sequence_id, sequence_count));
{
@ -2169,8 +2169,8 @@ build_dgc_prepare_shader(struct radv_device *dev, struct radv_indirect_command_l
}
nir_pop_if(&b, NULL);
build_dgc_buffer_tail_gfx(&b, sequence_count, dev);
build_dgc_buffer_preamble_gfx(&b, sequence_count, dev);
build_dgc_buffer_tail_main(&b, sequence_count, dev);
build_dgc_buffer_preamble_main(&b, sequence_count, dev);
/* Prepare the ACE command stream */
nir_push_if(&b, nir_ieq_imm(&b, load_param8(&b, has_task_shader), 1));

6
src/amd/vulkan/radv_device_generated_commands.h
View file

@ -57,15 +57,15 @@ struct radv_indirect_command_layout {
VK_DEFINE_NONDISP_HANDLE_CASTS(radv_indirect_command_layout, base, VkIndirectCommandsLayoutNV,
VK_OBJECT_TYPE_INDIRECT_COMMANDS_LAYOUT_NV)
uint32_t radv_get_indirect_gfx_cmdbuf_size(const VkGeneratedCommandsInfoNV *cmd_info);
uint32_t radv_get_indirect_main_cmdbuf_size(const VkGeneratedCommandsInfoNV *cmd_info);
uint32_t radv_get_indirect_ace_cmdbuf_size(const VkGeneratedCommandsInfoNV *cmd_info);
uint32_t radv_get_indirect_gfx_cmdbuf_offset(const VkGeneratedCommandsInfoNV *cmd_info);
uint32_t radv_get_indirect_main_cmdbuf_offset(const VkGeneratedCommandsInfoNV *cmd_info);
uint32_t radv_get_indirect_ace_cmdbuf_offset(const VkGeneratedCommandsInfoNV *cmd_info);
uint32_t radv_get_indirect_gfx_trailer_offset(const VkGeneratedCommandsInfoNV *cmd_info);
uint32_t radv_get_indirect_main_trailer_offset(const VkGeneratedCommandsInfoNV *cmd_info);
uint32_t radv_get_indirect_ace_trailer_offset(const VkGeneratedCommandsInfoNV *cmd_info);