Commit graph

101986 commits

Author SHA1 Message Date
Vlad Golovkin
967aabca06 nv50: Extract needed value bits without shifting them before calling bitcount
This can save one instruction since bitcount doesn't care about specific
bits' positions.

Reviewed-by: Karol Herbst <kherbst@redhat.com>
2018-05-02 15:12:48 +02:00
Antia Puentes
3a1df14a7b intel: activate the gl_BaseVertex lowering
Surplus code related to the basevertex is removed.

The Vertex Elements contain now:
* VE 1: <firstvertex, BaseInstance, VertexID, InstanceID>
* VE 2: <DrawID, is_indexed_draw, 0, 0>

Also fixes unreachable message.

Fixes OpenGL CTS tests:
* KHR-GL46.shader_draw_parameters_tests.ShaderDrawArraysInstancedParameters
* KHR-GL46.shader_draw_parameters_tests.ShaderMultiDrawArraysParameters
* KHR-GL46.shader_draw_parameters_tests.MultiDrawArraysIndirectCountParameters
* KHR-GL46.shader_draw_parameters_tests.ShaderDrawArraysParameters
* KHR-GL46.shader_draw_parameters_tests.ShaderMultiDrawArraysIndirectParameters

Fixes Piglit tests:
* arb_shader_draw_parameters-drawid-indirect baseinstance
* arb_shader_draw_parameters-basevertex

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102678
2018-05-02 11:24:46 +02:00
Antia Puentes
0fb204fac1 compiler/nir: Add conditional lowering for gl_BaseVertex
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2018-05-02 11:24:31 +02:00
Antia Puentes
0cbf29fa55 intel: emit is_indexed_draw in the same VE than gl_DrawID
The Vertex Elements are now:
* VE 1: <BaseVertex/firstvertex, BaseInstance, VertexID, InstanceID>
* VE 2: <DrawID, is-indexed-draw, 0, 0>

VE1 is it kept as it was before, VE2 additionally contains the new
system value.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2018-05-02 11:23:34 +02:00
Antia Puentes
6ba9088d9c intel/compiler: Add uses_is_indexed_draw flag
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2018-05-02 11:20:48 +02:00
Antia Puentes
9e6b886cf2 compiler: Add SYSTEM_VALUE_IS_INDEXED_DRAW and instrinsics
This VS system value contains if the draw command used to start the
rendering was an indexed draw command or a non-indexed one
(~0/0 respectively). Useful to calculate the gl_BaseVertex as:
(SYSTEM_VALUE_IS_INDEXED_DRAW & SYSTEM_VALUE_FIRST_VERTEX).

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2018-05-02 11:20:40 +02:00
Samuel Pitoiset
0737c1e3a6 radv: enable out-of-order rasterization by default
As the implementation is conservative, we can now enable it
by default. It can be disabled with RADV_DEBUG=nooutoforder.

Don't expect much more than 1% of improvements, but the gain
seems consistent.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-05-02 10:33:24 +02:00
Samuel Pitoiset
1d766b0196 radv: only disable out-of-order rast for perfect occlusion queries
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-05-02 10:33:22 +02:00
Kenneth Graunke
1122fb2d98 i965: Drop unused gen5 sampler default color struct.
Trivial.
2018-05-01 23:09:25 -07:00
Kenneth Graunke
9f6082f6c7 i965: Make brw_vs_outputs_written static.
Drop a prototype.  Trivial.
2018-05-01 23:09:16 -07:00
Nanley Chery
3e56e4642f i965/tex_image: Avoid the ASTC LDR workaround on gen9lp
Both the internal documentation and the results of testing this in the
CI suggest that this is unnecessary. Add the fixes tag because this
reduces an internal benchmark's startup time by about 17 seconds
(reported by Eero).

Fixes: 710b1d2e66 "i965/tex_image: Flush certain subnormal ASTC channel values"
Tested-by: Eero Tamminen <eero.t.tamminen@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
2018-05-01 16:47:39 -07:00
Eric Anholt
800be7f277 freedreno: Fix ir3_cmdline.c build.
Fixes: 6487e7a30c ("nir: move GL specific passes to src/compiler/glsl")
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Rob Clark <robdclark@gmail.com>
2018-05-01 16:38:37 -07:00
Jason Ekstrand
d216ffc604 anv: Allow lookup of vkEnumerateInstanceVersion without an instance
Fixes: cbab2d1da5
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-05-01 14:45:51 -07:00
Jason Ekstrand
d5a0787f03 anv: Don't advertise Float64 or Int64 on HW without 64-bit types
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
2018-05-01 14:45:50 -07:00
Samuel Pitoiset
d8db5986ce radv: compute the number of subpass attachments correctly
Only count color attachments twice if resolves are used, also
account for the depth stencil attachment if present.

Cc: 18.0 18.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2018-05-01 22:18:03 +02:00
Dave Airlie
e66f64c285 radv: set fmask_surf_index on fmask surfaces.
This is needed for gfx9 and later for all fmask surface index.

(Mentioned by Marek on irc)

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2018-05-02 06:01:42 +10:00
Brian Paul
f298ed93d9 gallium/i915: fix PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE typo
Fixes: fffe5e2d14 ("gallium: add initial support for conservative
rasterization")
Trivial.
2018-05-01 09:52:22 -06:00
Rhys Perry
07dac3e040 nvc0: add conservative rasterization support
Subpixel precision bias, dilation and the post-snap mode are supported on
GM200 and newer. The pre-snap mode is supported for triangle primitives on
GP100.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2018-04-30 21:13:53 -06:00
Rhys Perry
97f5f399ef st/mesa: add support for nvidia conservative rasterization extensions
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
2018-04-30 21:13:53 -06:00
Rhys Perry
fffe5e2d14 gallium: add initial support for conservative rasterization
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2018-04-30 21:13:53 -06:00
Rhys Perry
4580617509 mesa: add support for nvidia conservative rasterization extensions
Although the specs are written against compatibility GL 4.3 and allows core
profile and GLES2+, it is exposed for GL 1.0+ and GLES1 and GLES2+.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
2018-04-30 21:13:53 -06:00
Brian Paul
31ab0427a7 glsl/tests: add GLSL_TYPE_UINT8, GLSL_TYPE_INT8 cases to switch statements
To silence warnings about unhandled switch values.
Untested otherwise.

v2: move the INT/UINT8 cases after the INT/UINT16 cases, per Eric.

Reviewed-by: Eric Anholt <eric@anholt.net>
2018-04-30 21:13:53 -06:00
Brian Paul
efec712d51 tgsi: use enums instead of unsigned in ureg code
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
2018-04-30 21:13:53 -06:00
Timothy Arceri
6487e7a30c nir: move GL specific passes to src/compiler/glsl
With this we should have no passes in src/compiler/nir with any
dependencies on headers from core GL Mesa.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
2018-05-01 12:39:33 +10:00
Andres Rodriguez
f56e22e496 radv/winsys: fix leaking resources from bo's imported by fd
A bo's ref_count was not being initialized when imported from an fd.
Therefore, we would fail to free the resource during VkFreeMemory().

This patch fixes applications like hifi VR in threaded mode, which
perform frequent imports/releases of IPC shared memory.

Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
CC: 18.0 18.1 <mesa-stable@lists.freedesktop.org>
2018-04-30 18:20:30 -04:00
Scott D Phillips
2a08ae3c7c i965/tiled_memcpy: ytiled_to_linear a cache line at a time
Similar to the transformation applied to linear_to_ytiled, also align
each readback from the ytiled source to a cacheline (i.e. transfer a
whole cacheline from the source before moving on to the next column).
This will allow us to utilize movntqda (_mm_stream_si128) in a
subsequent patch to obtain near WB readback performance when accessing
the uncached ytiled memory, an order of magnitude improvement.

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2018-04-30 15:18:36 -07:00
Chris Wilson
682bdaa658 i965: Record mipmap resolver for unmapping
When mapping a region of the mipmap_tree, record which complementary
method to use to unmap it afterwards. By doing so we can avoid
duplicating the decision tree used when mapping and thereby eliminate
trivial errors that can be introduced if the two if-chains become out of
sync.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2018-04-30 14:06:23 -07:00
Chris Wilson
5367295e1a i965: Move unmap_depthstencil before map_depthstencil
Reorder code to avoid a forward declaration in the next patch.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
2018-04-30 14:06:23 -07:00
Chris Wilson
ab2825c898 i965: Move unmap_etc before map_etc
Reorder code to avoid a forward declaration in the next patch.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
2018-04-30 14:06:23 -07:00
Chris Wilson
9e7e88049f i965: Move unmap_s8 before map_s8
Reorder code to avoid a forward declaration in the next patch.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
2018-04-30 14:06:23 -07:00
Chris Wilson
b3ad6f5ca6 i965: Move unmap_movntdqa before map_movntdqa
Reorder code to avoid a forward declaration in the next patch.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
2018-04-30 14:06:23 -07:00
Chris Wilson
f348d07a62 i965: Move unmap_blit before map_blit
Reorder code to avoid a forward declaration in the next patch.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
2018-04-30 14:06:23 -07:00
Chris Wilson
359624142d i965: Move unmap_gtt before map_gtt
Reorder code to avoid a forward declaration in the next patch.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
2018-04-30 14:06:23 -07:00
Dave Airlie
8d3529872c ac/nir: expand 64-bit vec3 loads to fix shuffling.
If loading 64-bit vec3 values, a 4 component load would be followed
by a 2 component load and the resulting shuffle would fail as it
requires 2 4 components. This just expands the second results
vector out to 4 components.

This fixes 100 CTS tests:
dEQP-VK.spirv_assembly.type.vec3.*64*

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-05-01 05:58:14 +10:00
Kenneth Graunke
bde12f75e1 i965: Don't stomp initial kflags for program cache.
We want to flag EXEC_OBJECT_CAPTURE, but we ought to preserve any
existing kflags.  Today, there are none (as the program cache doesn't
support 48-bit addressing), but once we start using softpin, we'll
need to preserve EXEC_OBJECT_PINNED.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-04-30 11:34:19 -07:00
Kenneth Graunke
0cc98522f9 i965: Let batchbuffers be placed anywhere in the 48-bit address space.
We were trying to mark batch buffers with EXEC_OBJECT_CAPTURE, and
accidentally stomped EXEC_OBJECT_SUPPORTS_48B_ADDRESS in the process.

There's no reason to restrict batch buffers to the lower 4GB.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-04-30 11:34:19 -07:00
Scott D Phillips
8ffc6ee251 intel: fix check for 48b ppgtt support
The previous logic of the supports_48b_addresses wasn't actually
checking if i915.ko was running with full_48bit_ppgtt. The ENOENT
it was checking for was actually coming from the invalid context
id provided in the test execbuffer.  There is no path in the
kernel driver where the presence of
EXEC_OBJECT_SUPPORTS_48B_ADDRESS leads to an error.

Instead, check the default context's GTT_SIZE param for a value
greater than 4 GiB

v2 (Ken): Fix in i965 as well.
v3 Check GTT_SIZE instead of HAS_ALIASING_PPGTT (Chris Wilson)

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2018-04-30 11:34:19 -07:00
Leo Liu
1c5f4f4e17 st/omx/enc: fix blit setup for YUV LoadImage
The blit here involves scaling since it's copying from I8 format to R8G8 format.
Half of source will be filtered out with PIPE_TEX_FILTER_NEAREST instruction, it
looks that GPU always uses the second half as source. Currently we use "1" as
the start point of x for R, then causing 1 source pixel of U component shift to
right. So "-1" should be the start point for U component.

Cc: 18.0 18.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2018-04-30 11:55:36 -04:00
Juan A. Suarez Romero
4d449c94e4 autotools, meson: bump up required VA version
Due using a new VP9 config we use, required VA API 0.39

Fixes: 413c5ca372 ("travis: update libva required version")
CC: 18.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2018-04-30 13:59:37 +02:00
Juan A. Suarez Romero
96ed3714fc docs: update calendar, add news and link release notes to 18.0.2
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
2018-04-28 17:01:48 +00:00
Juan A. Suarez Romero
8f1159bf9a docs: add sha256 checksums for 18.0.2
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
(cherry picked from commit b3eed3ad03)
2018-04-28 16:58:39 +00:00
Juan A. Suarez Romero
14f85260de docs: add release notes for 18.0.2
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
(cherry picked from commit d38da7bd2d)
2018-04-28 16:58:36 +00:00
Marek Olšák
8b7358fe43 radeonsi: increase the number of compiler threads depending on the CPU
The compiler queue was limited to 3 threads, so shader-db running
on a 16-thread CPU would have a bottleneck on the 3-thread queue.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Tested-by: Benedikt Schemmer <ben at besd.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2018-04-27 17:56:04 -04:00
Marek Olšák
3f0eaaf6d9 radeonsi: avoid a crash in gallivm_dispose_target_library_info
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Tested-by: Benedikt Schemmer <ben at besd.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2018-04-27 17:56:04 -04:00
Marek Olšák
e75fc8d033 radeonsi: move data_layout into si_compiler
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Tested-by: Benedikt Schemmer <ben at besd.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2018-04-27 17:56:04 -04:00
Marek Olšák
797d673c9a radeonsi: move passmgr into si_compiler
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Tested-by: Benedikt Schemmer <ben at besd.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2018-04-27 17:56:04 -04:00
Marek Olšák
c1823ff661 radeonsi: move target_library_info into si_compiler
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Tested-by: Benedikt Schemmer <ben at besd.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2018-04-27 17:56:04 -04:00
Marek Olšák
5a94f15aa7 radeonsi: use si_compiler::triple in si_llvm_optimize_module
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Tested-by: Benedikt Schemmer <ben at besd.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2018-04-27 17:56:04 -04:00
Marek Olšák
43f0a10051 radeonsi: add triple into si_compiler
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Tested-by: Benedikt Schemmer <ben at besd.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2018-04-27 17:56:04 -04:00
Marek Olšák
87eb597758 radeonsi: add struct si_compiler containing LLVMTargetMachineRef
It will contain more variables.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Tested-by: Benedikt Schemmer <ben at besd.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2018-04-27 17:56:04 -04:00