Commit graph

115447 commits

Author SHA1 Message Date
Eric Engestrom
486091bc00 gbm: add missing comma between strings
Fixes: d971a4230d "loader: Factor out the common driver
                              opening logic from each loader."
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Eric Anholt <eric@anholt.net>
2018-11-19 15:50:56 +00:00
Samuel Pitoiset
724107553c radv: implement fast HTILE clears for depth or stencil only on GFX9
This allows to fast clear the depth part (or the stencil part)
of a depth+stencil surface when HTILE is enabled. I didn't test
on GFX8, so it's disabled currently.

This gives a very nice boost, for example when clearing the depth
aspect of a 4096x4096 D32_SFLOAT_S8_UINT image (18x faster).

BEFORE: 235 us
AFTER: 13 us

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-11-19 16:32:18 +01:00
Samuel Pitoiset
7dcddbe54d radv: rewrite the condition that checks allowed depth/stencil values
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-11-19 16:32:16 +01:00
Samuel Pitoiset
9133bbf186 radv: check allowed fast HTILE clears a bit earlier
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-11-19 16:32:14 +01:00
Samuel Pitoiset
193ad4748b radv: add radv_is_fast_clear_{depth,stencil}_allowed() helpers
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-11-19 16:32:12 +01:00
Samuel Pitoiset
c7e142ed78 radv: add radv_get_htile_fast_clear_value() helper
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-11-19 16:32:10 +01:00
Samuel Pitoiset
6f3fbcc041 radv: remove unnecessary goto in the fast clear paths
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-11-19 16:32:08 +01:00
Samuel Pitoiset
36006e3cec radv/winsys: remove the max IBs per submit limit for the sysmem path
This path will be eventually improved later but as it's only
used on SI (or with RADV_DEBUG=noibs), I'm not sure if that
matters much.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-11-19 16:32:06 +01:00
Samuel Pitoiset
4d30f2c6f4 radv/winsys: remove the max IBs per submit limit for the fallback path
The chained submission is the fastest path and it should now
be used more often than before. This removes some EOP events.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-11-19 16:32:04 +01:00
Lucas Stach
8ca8a6a7b1 etnaviv: use dummy RT buffer when rendering without color buffer
At least GC2000 seems to push some dirt from the PE color cache into
the last bound render target when drawing depth only. Newer cores
seem to behave properly and don't do this, but I have found no way
to fix it on GC2000. Flushes and stalls don't seem to make any
difference.

In order to stop the core from pushing the dirt into a precious real
render target, plug in dummy buffer when rendering without a color
buffer.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
2018-11-19 15:48:10 +01:00
Dave Airlie
8706204074
virgl: fix vtest regression since fencing changes.
The in_fence_fd needs to be initialised to -1.

Fixes: d1a1c21e7 (virgl: native fence fd support)

Reviewed-by: Robert Foss <robert.foss@collabora.com>
2018-11-19 15:33:19 +01:00
Samuel Pitoiset
55c75d2b49 radv: always clear the FCE predicate after DCC/FMASK/CMASK decompressions
DCC and FMASK also imply a fast-clear eliminate, so it should be
safe to reset the predicate unconditionally. We still only skip
FMASK or CMASK decompressions for now.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-11-19 14:05:35 +01:00
Samuel Pitoiset
483a28bfd4 radv: tidy up radv_set_dcc_need_cmask_elim_pred()
This is just a small cleanup.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-11-19 14:05:33 +01:00
Nicolai Hähnle
46a59ce026 radeonsi: fix an out-of-bounds read reported by ASAN
We read 4 values out of sample_locs_8x, so make sure the array is
big enough.

Fixes: ac76aeef20 ("radeonsi: switch back to standard DX sample positions")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2018-11-19 11:16:35 +01:00
Gert Wollny
d174cbccfa r600: Only set context streamout strides info from the shader that has outputs
With 5d517a streamout info is only attached to the shader for which the
transform feedback is actually recorded, but the driver set the context info
with each state submitted, thereby always using the info data that was
attached to the vertex shader.

Pass the streamout stride info to the context only from the shader that
actually has outputs. (Thanks to Marek Olšák for pointing me in the right
direction)

Fixes regresion with: dEQP-GLES31.functional.tessellation.invariance.*
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108734
Fixes: 5d517a599b
  st/mesa: Don't record garbage streamout information in the non-SSO case.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2018-11-19 11:06:56 +01:00
Gert Wollny
18a8e11aea i965:use FRAMEBUFFER_UNSUPPORTED instead of FRAMEBUFFER_INCOMPLETE_DIMENSIONS
FRAMEBUFFER_INCOMPLETE_DIMENSIONS is not supported for GLES 3.0 and later and
not defined for Desktop OpenGL. Instead use FRAMEBUFFER_UNSUPPORTED like it
was done before.

Thanks to Iago Toral and Andrey Simiklit for pointing out the problem and the
details.

Fixes:  ebcde34545
   i965: be more specific about FBO completeness errors
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
2018-11-19 11:06:52 +01:00
Gert Wollny
40eca7d3e1
virgl: Use file descriptor instead of un-allocated object
The structure qdws is not allocated at this point, nor is the
file descriptor set to it's member. Use the fd directly instead.

Fixes:  d1a1c21e76
    virgl: native fence fd support

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
2018-11-19 11:03:56 +01:00
Gert Wollny
78fdc507a3 i965: Add support for and expose EXT_texture_sRGB_R8
Emulate MESA_FORMAT_R_SRGB8 by using L8_UNORM_SRGB. This is possible
because component swizzling is handled based on the mesa format and,
hence, the a r001 swizzling can be used to correct the components.

Enables and makes pass (tested on Kabylake)

  dEQP-GLES31.functional.srgb_texture_decode.skip_decode.sr8.*
  dEQP-GLES31.functional.texture.filtering.cube_array.formats.sr8*

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Acked-by: Eric Engestrom <eric.engestrom@intel.com>
2018-11-19 08:05:44 +01:00
Gert Wollny
c5363869d4 i965: Force zero swizzles for unused components in GL_RED and GL_RG
This makes it possible to use a hardware luminance format as RED format.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2018-11-19 08:05:44 +01:00
Gert Wollny
ebcde34545 i965: be more specific about FBO completeness errors
The driver was returning GL_FRAMEBUFFER_UNSUPPORTED for all cases of an
incomplete fbo, be a bit more specific about this following the description
of glCheckFramebufferStatus.

This helps to keeps dEQP happy when adding EXT_texture_sRGB_R8 support.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2018-11-19 08:05:44 +01:00
Gert Wollny
24a02157dd i965: Correct L8_UNORM_SRGB table entry
As the name says, the format is an sRGB format.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2018-11-19 08:05:44 +01:00
Robert Foss
70692adf48
virgl: Clean up fences commit
Remove a dead variable, a int->bool conversion and some
whitespace changes.

Signed-off-by: Robert Foss <robert.foss@collabora.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2018-11-18 12:14:55 +01:00
Kenneth Graunke
c2e3d0f163 i915: Delete swizzling detection logic.
This is all leftover from the i965 split.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-17 10:26:31 -08:00
Ilia Mirkin
beb66d3747 nv50/ir/ra: enforce max register requirement, and change spill order
On nv50, certain operations must happen on regs below 64, due to
encoding requirements. First of all, we add infrastructure to enforce
this. Secondly we change the spill order to first spill RIG nodes that
are unconstrained, followed by ones that are.

This makes the gamecube logo shadertoy compile properly. Curiously, if
we adjust the spill order so that we first spill the constrained RIG
nodes instead, the RA also succeeds. However it seems more logical to
first spill the unconstrained ones.

While we're at it, drop the nv50 max register to reserve r127 as the
zero register of last resort (r63 is preferred).

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Acked-by: Karol Herbst <kherbst@redhat.com>
2018-11-16 22:43:52 -05:00
Ilia Mirkin
799e021894 nv50/ir/ra: improve condition for short regs, unify with cond for 16-bit
Instead of the size restriction existing in two places, and potentially
being applied twice, we move this together. Ops with 16-bit register
addresses can only take a short reg, and ops with immediates can only
take a short reg.

Of course we leave the immediate 0 in place since we know that it will
be replaced by r63/r127 down the line, so don't treat zeroes as an
immediate.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
2018-11-16 20:53:33 -05:00
Ilia Mirkin
955d943c33 nv50/ir: delete MINMAX instruction that is no longer in the BB
We removed the op from the BB, but it was still listed in its sources'
uses. This could trip up some logic down the line which analyzes all the
uses of an l-value, e.g. spilling.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
2018-11-16 20:53:09 -05:00
Eric Anholt
7e9fc11ff8 egl: Print the actual message to the console from _eglError().
Previously we would print errors on the console like:

   libEGL debug: EGL user error 0x3001 (EGL_NOT_INITIALIZED) in eglInitialize

When we had everything we needed for:

   libEGL debug: EGL user error 0x3001 (EGL_NOT_INITIALIZED) in eglInitialize: DRI2: failed to find EGLDevice

(for a gbm error in my case)

Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2018-11-16 17:49:31 -08:00
Eric Anholt
d971a4230d loader: Factor out the common driver opening logic from each loader.
I copied the code from egl_dri2.c, but the functionality was equivalent
between all the loaders other than their particular environment variables.

v2: Drop the logging function equivalent to loader_default_logger()
    (requested by Eric, Emil).  Move the SCons workaround across.  Drop
    the now-unused driGetDriverExtensions() declaration that was lost in a
    rebase.

Reviewed-by: Eric Engestrom <eric.engestrom@intel.com> (v1)
Reviewed-by: Emil Velikov <emil.velikov@collabora.com> (v1)
2018-11-16 17:49:17 -08:00
Eric Anholt
cc19815738 loader: Stop using a local definition for an in-tree header
I need other types from the header now, and "gl.h is big" is not a good
reason to duplicate definitions.

Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2018-11-16 15:38:18 -08:00
Eric Anholt
2bc1f5c2e7 egl: Move loader_set_logger() up to egl_dri2.c.
Everyone needs to call it, and platform_x11 forgot to.

Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2018-11-16 15:38:18 -08:00
Eric Anholt
c2b515379b glx: Move DRI extensions pointer loading to driOpenDriver().
The only thing you do with a dri driver handle is get the extensions
pointer, so just fold it in to simplify the callers.

v2: Add the declaration of driGetDriverExtensions() that got lost in a
    rebase.

Reviewed-by: Eric Engestrom <eric.engestrom@intel.com> (v1)
Reviewed-by: Emil Velikov <emil.velikov@collabora.com> (v1)
2018-11-16 15:38:18 -08:00
Eric Anholt
7076e9f116 glx: Remove an old DEFAULT_DRIVER_DIR default.
You can tell by "Mesa/configs/default" how old this is.  Your build system
really has to provide the DEFAULT_DRIVER_DIR, or other loaders will break.

v2: Move the bad (non-prefix-dependent) define to the SConscript to avoid
    breaking it.

Reviewed-by: Eric Engestrom <eric.engestrom@intel.com> (v1)
Reviewed-by: Emil Velikov <emil.velikov@collabora.com> (v1)
2018-11-16 15:37:47 -08:00
Samuel Pitoiset
d031d5c999 radv: enable primitive binning by default
After doing a bunch of benchmarks, primitive binning helps
some games like The Talos Principle (+5%) or Serious Sam 2017
(+3%). For other titles, either it doesn't change anything or
it hurts very few (less than 1%).

This only affects GFX9.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-11-16 17:51:15 +01:00
Samuel Pitoiset
afd834b62e radv: add a debug option for disabling primitive binning
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-11-16 17:51:12 +01:00
Robert Foss
d1a1c21e76
virgl: native fence fd support
Following the support for fences on the virtio driver add support
for native fence on virgl. This was somewhat based on the freedeno one.

Signed-off-by: Gustavo Padovan <gustavo.padovan@collabora.com>
Signed-off-by: Robert Foss <robert.foss@collabora.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2018-11-16 14:41:57 +01:00
Lionel Landwerlin
0db898cef2 intel/aub_viewer: Print blend states properly
Identical fix to :

commit 70de31d0c1
Author: Jason Ekstrand <jason.ekstrand@intel.com>
Date:   Fri Aug 24 16:05:08 2018 -0500

    intel/batch_decoder: Print blend states properly

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Toni Lönnberg <toni.lonnberg@intel.com>
2018-11-16 11:40:38 +00:00
Lionel Landwerlin
ac324a6809 intel/aub_viewer: fix dynamic state printing
Identical fix to :

commit cbd4bc1346
Author: Jason Ekstrand <jason.ekstrand@intel.com>
Date:   Fri Aug 24 16:04:03 2018 -0500

    intel/batch_decoder: Fix dynamic state printing

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Toni Lönnberg <toni.lonnberg@intel.com>
2018-11-16 11:40:14 +00:00
Lionel Landwerlin
59c1059528 intel/aubinator: fix ring buffer pointer
We can only start parsing commands from the head pointer. This was
working fine up to now because we only dealt with a "made up" ring
buffer (generated by aub_write) which always had its head at 0.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Toni Lönnberg <toni.lonnberg@intel.com>
2018-11-16 11:39:54 +00:00
Lionel Landwerlin
25443cbb72 intel/decoders: read ring buffer length
Use this value to limit reading the ring buffer.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Toni Lönnberg <toni.lonnberg@intel.com>
2018-11-16 11:37:08 +00:00
Lionel Landwerlin
1c56d21156 egl/dri: fix error value with unknown drm format
According to the EGL_EXT_image_dma_buf_import spec, creating an EGL
image with a DRM format not supported should yield the BAD_MATCH
error :

"
       * If <target> is EGL_LINUX_DMA_BUF_EXT, and the EGL_LINUX_DRM_FOURCC_EXT
         attribute is set to a format not supported by the EGL, EGL_BAD_MATCH
         is generated.
"

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 20de7f9f22 ("egl/dri2: support for creating images out of dma buffers")
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Chad Versace <chadversary@chromium.org>
2018-11-16 10:28:06 +00:00
Daniel Stone
5e1fe240c4 gbm: Clarify acceptable formats for gbm_bo
gbm_bo_create() was presumably meant to originally accept gbm_bo_format
enums, but it's accepted GBM_FORMAT_* tokens since the dawn of time.
This is good, since gbm_bo_format is rarely used and covers a lot less
ground than GBM_FORMAT_*.

Change the documentation to refer to both; this involves removing a 'see
also' for gbm_bo_format, since we can't also use \sa to refer to a
family of anonymous #defines.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Reported-by: Pekka Paalanen <pekka.paalanen@collabora.co.uk>
Reviewed-by: Eric Anholt <eric@anholt.net>
2018-11-16 09:40:46 +00:00
Connor Abbott
ba94a00c7c Revert "radv: disable VK_SUBGROUP_FEATURE_VOTE_BIT"
This reverts commit 647c2b90e9. There was
one recently-introduced bug in ac for dvec3 loads, but the other test
failures were actually bugs in the tests. See
9429e621c4

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-11-16 10:32:03 +01:00
Eric Anholt
cc71bf529c vc4: Don't return a vc4 BO handle on a renderonly screen.
The handles exported need to be on the KMS device's fd, anything else is
failure.  Also, this code is assuming that the scanout resource has been
created already, so assert it.
2018-11-15 21:11:44 -08:00
Eric Anholt
cc0bc76a38 vc4: Make sure we make ro scanout resources for create_with_modifiers.
The DRI3 create_with_modifiers paths don't set tmpl.bind to SCANOUT or
SHARED, with the theory that given that you've got modifiers, that's all
you need.  However, we were looking at the tmpl.bind for setting up the
KMS handle in the renderonly case, so we'd end up trying to use vc4's
handle on the hx8357d fd.

Fixes: 84ed8b67c5 ("vc4: Set shareable BOs as T tiled if possible")
2018-11-15 21:11:44 -08:00
Danylo Piliaiev
f9fd0cf479 i965: Fix calculation of layers array length for isl_view
Handle all cases in calculation of layers count for isl_view
taking into account texture view and image unit.
st_convert_image was taken as a reference.

When u->Layered is true the whole level is taken with respect to
image view. In other case only one layer is taken.

v3: (Józef Kucia and Ilia Mirkin)
    - Rewrote patch by taking st_convert_image as a reference
    - Removed now unused get_image_num_layers function
    - Changed commit message

v4: (Jason Ekstrand)
    - Added assert

Fixes: 5a8c8903
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107856

Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2018-11-15 19:59:54 -06:00
Jason Ekstrand
6339aba775 intel/compiler: Lower SSBO and shared loads/stores in NIR
We have a bunch of code to do this in the back-end compiler but it's
fairly specific to typed surface messages and the way we emit them.
This breaks it out into NIR were it's easier to do things a bit more
generally.  It also means we can easily share the code between the vec4
and FS back-ends if we wish.

Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
2018-11-15 19:59:49 -06:00
Jason Ekstrand
d34fd81e76 nir: Add alignment parameters to SSBO, UBO, and shared access
This also changes spirv_to_nir and glsl_to_nir to set them.  The one
place that doesn't set them is shared memory access lowering in
nir_lower_io.  That will have to be updated before any consumers of it
can effectively use these new alignments.

Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Acked-by: Karol Herbst <kherbst@redhat.com>
2018-11-15 19:59:42 -06:00
Jason Ekstrand
fb127f7729 nir/lower_io: Add shared to get_io_offset_src
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
2018-11-15 19:59:31 -06:00
Jason Ekstrand
b5c48271d4 nir/glsl: Force 32-bit for UBO and SSBO Booleans
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
2018-11-15 19:59:30 -06:00
Jason Ekstrand
44b7005581 nir/spirv: Force 32-bit for UBO and SSBO Booleans
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
2018-11-15 19:59:29 -06:00