Commit graph

39979 commits

Author SHA1 Message Date
Greg V
c0dc5c1859 meson: define ETIME to ETIMEDOUT if not present
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2019-08-08 21:44:33 +01:00
Roman Stratiienko
28061e0ab0 lima: Fix Android.mk
1. Update LOCAL_SRC_FILES according to commit
54434fe670 ("lima/gpir: Rework the scheduler").

2. Add libpanfrost_shared.a dependency.

3. Generate lima_nir_algebraic.c with Android.mk
Fixes Android build error introduced by commit 5adfc8602c
("lima/ppir: move sin/cos input scaling into NIR")

Signed-off-by: Roman Stratiienko <roman.stratiienko@globallogic.com>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Acked-by: Qiang Yu <yuq825@gmail.com>
2019-08-08 17:47:22 +00:00
Rhys Perry
c52c54a746 anv,i965,iris: deduplicate setting of total_shared
v5: add patch

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2019-08-08 12:10:39 -05:00
Erik Faye-Lund
1e21bb4123 mesa: avoid warning on Windows
On Windows, p_atomic_inc_return returns an unsigned long long rather
than the type the pointer refers to, so let's make sure we cast the
result to the right type. Otherwise, we'll trigger a warning about
the wrong format-string for the type.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Acked-by: Eric Engestrom <eric@engestrom.ch>
2019-08-08 18:20:29 +02:00
Lucas Stach
68c24b09c2 etnaviv: remember data offset into BO
Imported resources might not start at offset 0 into the buffer object.
Make sure to remember the offset that is provided with the handle on
import.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2019-08-08 16:11:34 +02:00
Jan Zielinski
207026d29e swr/rasterizer: modernize thread TLB
Reviewed-by: Alok Hota <alok.hota@intel.com>
2019-08-08 12:33:21 +02:00
Jan Zielinski
387599a661 swr/rasterizer: Refactor events collection mechanism
Several improvements and cleanups in events and statstics mechanisms

Reviewed-by: Alok Hota <alok.hota@intel.com>
2019-08-08 11:15:07 +02:00
Jan Zielinski
ff75c35846 swr/rasterizer: improvements in simdlib
1. fix build issues with MSVC 2019 compiler

The MSVC 2019 compiler seems to have an issue with optimized code-gen
when using the _mm256_and_si256() intrinsic.
Only disable use of integer vpand on buggy versions MSVC 2019.
Otherwise allow use of integer vpand intrinsic.

2. Remove unused vec/matrix functionality

Reviewed-by: Alok Hota <alok.hota@intel.com>
2019-08-08 10:53:47 +02:00
Jan Zielinski
b55a93fdd4 swr/rasterizer: Events are now grouped and enabled by knobs
All events are now grouped as follows:

-Framework (i.e. ThreadStart) [always ON]
-Api (i.e. SwrSync) [always ON]
-Pipeline [default ON]
-Shader [default ON]
-SWTag [default OFF]
-Memory [default OFF]

Reviewed-by: Alok Hota <alok.hota@intel.com>
2019-08-08 10:33:25 +02:00
Jan Zielinski
982d99490f swr/rasterizer: do not mark tiles dirty until actually rendered
Reviewed-by: Alok Hota <alok.hota@intel.com>
2019-08-08 10:16:20 +02:00
Jan Zielinski
4f04f260d9 swr/rasterizer: enable size accumulation in mem stats
Small refactoring is also performed

Reviewed-by: Alok Hota <alok.hota@intel.com>
2019-08-08 10:16:20 +02:00
Jan Zielinski
365ad367f1 swr/rasterizer: enable using AOS vertex data format
Reviewed-by: Alok Hota <alok.hota@intel.com>
2019-08-08 10:16:20 +02:00
Iago Toral Quiroga
fb9f7872e7 v3d: handle wait requirement when retrieving query results correctly
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-08-08 08:36:52 +02:00
Iago Toral Quiroga
0f2d1dfe65 v3d: use the GPU to record primitives written to transform feedback
We can use the PRIMITIVE_COUNTS_FEEDBACK packet to write various primitive
counts to a buffer, including the number of primives written to transform
feedback buffers, which will handle buffer overflow correctly.

There are a couple of caveats with this:

Primitive counters are reset when we emit a 'Tile Binning Mode Configuration'
packet, which can happen in the middle of a primitives query, so we need to
read the buffer when we submit a job and accumulate the counts in the context
so we don't lose them.

We also need to do the same when we switch primitive type during transform
feedback so we can compute the correct number of recorded vertices from
the number of primitives. This is necessary so we can provide an accurate
vertex count for draw from transform feedback.

v2:
 - When computing the number of vertices for a primitive, pass in the base
   primitive, since that is what the hardware will count.
 - No need to update primitive counts when switching primitive types if
   the base primitives are the same.
 - Log perf warning when mapping the primitive counts BO for readback (Eric).
 - Only emit the primitive counts packet once at job end (Eric).
 - Use u_upload mechanism for the primitive counts buffer (Eric).
 - Use the XML to generate indices into the primitive counters buffer (Eric).

Fixes piglit tests:
spec/ext_transform_feedback/overflow-edge-cases
spec/ext_transform_feedback/query-primitives_written-bufferrange
spec/ext_transform_feedback/query-primitives_written-bufferrange-discard
spec/ext_transform_feedback/change-size base-shrink
spec/ext_transform_feedback/change-size base-grow
spec/ext_transform_feedback/change-size offset-shrink
spec/ext_transform_feedback/change-size offset-grow
spec/ext_transform_feedback/change-size range-shrink
spec/ext_transform_feedback/change-size range-grow
spec/ext_transform_feedback/intervening-read prims-written

Reviewed-by: Eric Anholt <eric@anholt.net>
2019-08-08 08:36:52 +02:00
Iago Toral Quiroga
cf8986bce0 gallium/util: add a helper to compute vertex count from primitive count
v2:
  - Only compute vertex counts for base primitives.
  - Add a unit test (Eric)

Reviewed-by: Eric Anholt <eric@anholt.net>
2019-08-08 08:36:52 +02:00
Iago Toral Quiroga
9eb8699e0f v3d: be more explicit about the query types supported
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-08-08 08:36:52 +02:00
Iago Toral Quiroga
9b316ab57a v3d: generate packet unpack functions
These were not being compiled because of the lack of __gen_unpack_address.

v2:
 - Shift raw address correctly (Eric).

Reviewed-by: Eric Anholt <eric@anholt.net>
2019-08-08 08:36:52 +02:00
Tomeu Vizoso
e7eac8a1e8 panfrost: Print errors from kernel
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-08-08 07:42:52 +02:00
Tomeu Vizoso
7c8434889d panfrost: Mark buffers as PANFROST_BO_HEAP
What we call GROWABLE in Mesa corresponds to the HEAP BO flag in the
kernel. These buffers cannot be memory mapped in the CPU side at the
moment, so make sure they are also marked INVISIBLE.

This allows us to allocate a big heap upfront (16MB) without actually
reserving space unless it's needed.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-08-08 07:42:52 +02:00
Tomeu Vizoso
19afd41e65 panfrost: Mark BOs as NOEXEC
Unless a BO has the EXECUTABLE flag, mark it as NOEXEC.

v2: - Rework version detection (Alyssa).

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-08-08 07:42:52 +02:00
Tomeu Vizoso
9398932c2d panfrost: Take into account flags when looking up in the BO cache
This will be useful right now so we avoid retrieving a non-executable
buffer when a executable one is needed.

As we support more flags, this logic will need to be extended to
consider the different trade-offs to be made when matching BO
specifications to BOs in the cache.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-08-08 07:42:52 +02:00
Tomeu Vizoso
950b5fc596 panfrost: Allocate shaders in their own BOs
Instead of all shaders being stored in a single BO, have each shader in
its own.

This removes the need for a 16MB allocation per context, and allows us
to place transient blend shaders in BOs marked as executable (before
they were allocated in the transient pool, which shouldn't be
executable).

v2: - Store compiled blend shaders in a malloc'ed buffer, to avoid
      reading from GPU-accessible memory when patching (Alyssa).
    - Free struct panfrost_blend_shader (Alyssa).
    - Give the job a reference to regular shaders when emitting
      (Alyssa).

v3: - Split out the allocation flags change (Rob).

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-08-08 07:42:52 +02:00
Mark Janes
2446f5cfd8 intel/perf: move perf-related constants to common location
The perf subsystem needs several macro definitions that were
duplicated in Iris and i965 headers.  Place these macros within perf,
if the perf implementation contains the only references to the values.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-08-07 21:33:55 -07:00
Ilia Mirkin
9ff8da0e50 nvc0: fix program dumping, use _debug_printf
This debug situation is unforunate. debug_printf only does something
with DEBUG set, but in practice all that needs to be moved to !NDEBUG.
For now, use _debug_printf which always prints. However the whole
function is guarded by !NDEBUG.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2019-08-07 22:32:02 -04:00
Ilia Mirkin
f6af104340 nvc0: add support for ATOMC_WRAP TGSI operations
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2019-08-07 22:32:02 -04:00
Ilia Mirkin
a2bb7b26a1 gallium: redefine ATOMINC_WRAP to be more hardware-friendly
Both AMD and NVIDIA hardware define it this way. Instead of replicating
the logic everywhere, just fix it up in one place.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-08-07 22:31:56 -04:00
Pierre-Eric Pelloux-Prayer
519bebdb40 radeonsi: limit DPBB context_states_per_bin batches when using gfx9 workaround
It seems that using 'context_states_per_bin = 1' for DPBB fixes the reported issue.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110214

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-08-07 18:45:24 -04:00
Pierre-Eric Pelloux-Prayer
120d0ef937 radeonsi: reduce DPBB persistent_states_per_bin value for APUs
Fixes some reported GPU hangs on RAVEN.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111231

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-08-07 18:45:22 -04:00
Pierre-Eric Pelloux-Prayer
6bda9ca062 radeonsi: fix typo in DPBB register field
Also only set FLUSH_ON_BINNING_TRANSITION for GPU families that needs it (matches
what si_emit_dpbb_disable is doing).

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-08-07 18:45:20 -04:00
Pierre-Eric Pelloux-Prayer
90bded140e radeonsi: fix S_028C48_MAX_ALLOC_COUNT value
This field uses "value minus 1" encoding.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-08-07 18:45:09 -04:00
Christian Gmeiner
323cda475b etnaviv: drop struct etna_3d_state
Also drop #if 0 code block.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Philipp Zabel <philipp.zabel@gmail.com>
2019-08-07 22:12:00 +02:00
Bas Nieuwenhuizen
5a26f528cb meson,i965: Link with android deps when building for android.
The DBG marco in brw_blorp.c ends up calling an android log function:

error: undefined reference to '__android_log_print'

v2: On suggestion from Lionel, hang the Android dependency onto a new
    libintel_common dependency.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-08-07 15:34:46 +02:00
Erik Faye-Lund
da9e2958ec gallium/dump: add missing query-type to short-list
Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Fixes: 3f6b3d9db7 ("gallium: add PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-08-07 12:03:24 +00:00
Erik Faye-Lund
70a93922db gallium/dump: add missing query-type to short-list
Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Fixes: a677799e51 ("gallium: add PIPE_QUERY_SO_OVERFLOW_ANY_PREDICATE
                     and corresponding cap")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-08-07 12:03:24 +00:00
Jan Vesely
6b8269d0bb clover: Fix build after clang r367864
v2: Drop special case of llvm-9
Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
Acked-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Aaron Watry <awatry@gmail.com>
2019-08-06 23:33:55 -04:00
John Stultz
fcfa2d1447 mesa: freedreno: Android.registers.mk: Fix up register xml.h file generation
The current Androdi.registers.mk file causes build failures that
look like:
 FAILED:
 external/mesa3d/src/freedreno/Android.registers.mk:49: error: implicit rules are obsolete: out/target/product/linaro_db845c/gen/STATIC_LIBRARIES/libfreedreno_registers_intermediates/registers/%.xml.h

Caused by the following Android build rule change:
https://android.googlesource.com/platform/build/+/HEAD/Changes.md#implicit_rules

I tried to replace this with something similar to the static
pattern suggested in the URL above, but ended up getting all the
xml.h files generated using only the first a2xx.xml source file.

So I've fallen back to explicitly defining the make rules for
each.

Additionally, we needed to provide the proper
LOCAL_EXPORT_C_INCLUDE_DIRS and add the defined static library
to the components that depend on the register headers.

Acked-by: Eric Anholt <eric@anholt.net>
Signed-off-by: John Stultz <john.stultz@linaro.org>
2019-08-07 02:18:38 +00:00
John Stultz
96baf052b2 mesa: Add ir3/ir3_nir_imul.c generation to Android.mk
With current master we're seeing build failures with AOSP:
  error: undefined symbol: ir3_nir_lower_imul

This is due to the ir3_nir_imul.c file not being generated
in the Android.mk files.

This patch simply adds it to the Android build, after which
thigns build and book ok on db410c.

Cc: Rob Clark <robdclark@chromium.org>
Cc: Emil Velikov <emil.l.velikov@gmail.com>
Cc: Amit Pundir <amit.pundir@linaro.org>
Cc: Sumit Semwal <sumit.semwal@linaro.org>
Cc: Alistair Strachan <astrachan@google.com>
Cc: Greg Hartman <ghartman@google.com>
Cc: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: John Stultz <john.stultz@linaro.org>
2019-08-07 02:18:19 +00:00
Rohan Garg
16edd56fcc panfrost: Take into account a index_bias for glDrawElementsBaseVertex calls
Midgard does not accept a index_bias directly and relies instead on a
bias correction offset (offset_bias_correction) in order to calculate
the unbiased vertex index.

We need to make sure we adjust offset_start and vertex_count in order to
take into account the index_bias as required by a
glDrawElementsBaseVertex call and then supply a additional
offset_bias_correction to the hardware.

Signed-off-by: Rohan Garg <rohan.garg@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
2019-08-06 17:18:19 -07:00
Timothy Arceri
dca119f12c mesa/gallium: add dric option to allow overriding GL vendor string
Will be used in the following patch.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93551
2019-08-07 10:12:49 +10:00
Marek Olšák
16577f5002 tgsi_to_nir: add a few needed double opcodes
for internal radeonsi shaders

v2 (Connor):
- Split out prep work from adding opcodes, and rewrite the former

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-08-06 18:03:26 -04:00
Marek Olšák
2207daf549 tgsi_to_nir: implement a few needed 64-bit integer opcodes
for internal radeonsi shaders

v2 (Connor):
- Split this out from the prep work, and rework the former
- Add support for U64SNE

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-08-06 18:03:24 -04:00
Connor Abbott
37f6350c1d ttn: Prepare for 64-bit sources and destinations
v2: Properly handle 32->64 bit conversions

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-08-06 18:03:22 -04:00
Connor Abbott
4b10949482 ttn: Use 1-bit NIR comparison opcodes
We shouldn't be using the versions that output a 32-bit boolean, since
nir_opt_algebraic won't optimize them as well. Drivers will lower these
to the 32-bit versions after optimizing, if appropriate. Also, this will
make implementing 64-bit comparisons easier.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-08-06 18:03:19 -04:00
Pierre-Eric Pelloux-Prayer
f84c9ad17a radeonsi: enable EXT_shader_image_load_store
This depends on LLVM 10 because this needs https://reviews.llvm.org/D65283

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-08-06 17:41:07 -04:00
Pierre-Eric Pelloux-Prayer
25fff591c1 radeonsi: add support for nir atomic_inc_wrap/atomic_dec_wrap
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-08-06 17:41:06 -04:00
Pierre-Eric Pelloux-Prayer
8789248541 radeonsi: add support for tgsi ATOMDEC_WRAP / ATOMINC_WRAP opcodes
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-08-06 17:41:04 -04:00
Pierre-Eric Pelloux-Prayer
91924453ee gallium: add PIPE_CAP_TGSI_ATOMINC_WRAP to indicate support
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-08-06 17:40:51 -04:00
Pierre-Eric Pelloux-Prayer
8b6bfed3d2 tgsi: add ATOMICINC_WRAP/ATOMICDEC_WRAP opcode
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-08-06 17:40:34 -04:00
Marek Olšák
1d8a71af57 radeonsi/gfx10: enable all CUs for GS if NGG is never used
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-08-06 17:09:03 -04:00
Marek Olšák
91227a1e17 radeonsi/gfx10: add global use_ngg and use_ngg_streamout flags
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-08-06 17:09:02 -04:00