Commit graph

13804 commits

Author SHA1 Message Date
Ian Romanick
8b2be206f3 brw/algebraic: Constant folding for BROADCAST and SHUFFLE
This prevents assertion failures in brw_eu_emit in a later commit in
this MR. Even though they have not been previously observed, these
assertion failures could happen even without that commit.

No shader-db or fossil-db changes on any Intel platform.

Fixes: 04e1783278 ("brw: Call brw_fs_opt_algebraic less often")

v2: Add SHUFFLE. Suggested by Ken. Fixed indentation.

v3: Update BROADCAST exec_size after rebasing on "brw/build: Use SIMD8
temporaries in emit_uniformize".

v4: Explain why munging the exec_size is correct.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31497>
2025-04-04 06:45:02 +00:00
Ian Romanick
1b997c7bcc brw/coalesce: Prepare brw_opt_register_coalesce for load_reg
v2: Explain the problematic situation a little better in the
comment. Suggested by Caio.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31497>
2025-04-04 06:45:02 +00:00
Ian Romanick
15637334ce brw/copy: Prepare copy_propagation for load_reg
The changes to try_copy_propagate will be removed later in the series.

v2: Fix up some comments to note that offset != 0 is allowed only when
stride == 0. Apply same offset=0 restriction in try_copy_propagate_def
too. Allow copy propagation if the source is either a def or
UNIFORM. Don't copy prop a load_reg through a non-def value.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31497>
2025-04-04 06:45:02 +00:00
Ian Romanick
cfc50390fb brw: Add basic infrastructure for load_reg pseudo op
load_reg is something like load_payload except it has a single
source. It copies the entire source to the destination. Its purpose is
to convert a non-SSA VGRF into an SSA value. This copy is marked as
volatile so that it will act as a scheduling barrier.

v2: Fix some typos in the commit message. Eliminate the
brw_builder::LOAD_REG overload that returns a brw_inst*. This is
unlikely to ever be used. Add some checks to brw_validate. All
suggested by Caio.

v3: Force the source and destination types of the LOAD_REG to by
integer. This will (eventually) simplify the creating of unit tests for
the pass that adds LOAD_REG instructions.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31497>
2025-04-04 06:45:02 +00:00
Ian Romanick
b9656d51c0 brw/opt: Move non-SSA register accounting after first brw_opt_split_virtual_grfs
v2: Move to immediately before the main optimization loop. Most
importantly, this is after the first call to DCE.

fossil-db:

All Intel platforms had similar results. (Lunar Lake shown)
Totals:
Non SSA regs after NIR: 237045283 -> 100183460 (-57.74%); split: -58.12%, +0.39%

Totals from 701423 (99.26% of 706657) affected shaders:
Non SSA regs after NIR: 236868848 -> 100007025 (-57.78%); split: -58.17%, +0.39%

Suggested-by: Ken
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31497>
2025-04-04 06:45:02 +00:00
Caleb Callaway
5ad00bae8b intel/compiler: fix lingering i965 references
Some checks are pending
macOS-CI / macOS-CI (dri) (push) Waiting to run
macOS-CI / macOS-CI (xlib) (push) Waiting to run
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34351>
2025-04-03 03:17:25 +00:00
Dylan Baker
ff4b1b1e43 intel/decoder: free memory in error case
This was handled in other instances in a previous patch, but this
instance remains, as the zlib decompression routine is slightly
different.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34118>
2025-04-02 19:26:55 +00:00
Dylan Baker
da14c0af67 intel/tools: move ascii85_decode to common code
We have 3 copies of this function, so put it in the shared static
library.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34118>
2025-04-02 19:26:55 +00:00
Dylan Baker
7b791cd0b4 intel/tools: deduplicate zlib_inflate function
There are three copies of this function, all of them have the same
memory leak in them. Instead of fixing them one by one, just use a
common implementation for all three, since they already all have a
shared helper lib.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34118>
2025-04-02 19:26:55 +00:00
Ian Romanick
e210b79ce3 brw/nir: Lower fsign again after last call to brw_nir_optimize
Some checks are pending
macOS-CI / macOS-CI (dri) (push) Waiting to run
macOS-CI / macOS-CI (xlib) (push) Waiting to run
No shader-db or fossil-db changes on any Intel platform.

Fixes: 13332c23 ("intel/brw: Unconditionally run optimizations after nir_opt_uniform_subgroup")
Closes: #12888
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34251>
2025-04-02 01:59:49 +00:00
Ian Romanick
ca95cb8178 brw: Fix typo in comment
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34251>
2025-04-02 01:59:49 +00:00
Collabora's Gfx CI Team
1ce0cef6bf Uprev ANGLE to 1b34d2a18af12cc55a3bc74dd679c2937d10cc5c
6abdc11741...1b34d2a18a

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34277>
2025-04-01 12:51:06 +00:00
Lionel Landwerlin
4ac900b5bf anv/genxml: use special genX video pack files
Before:

   30453 ./build/src/intel/genxml/gen125_pack.h

After:

   17026 ./build/src/intel/genxml/gen125_pack.h
   21589 ./build/src/intel/genxml/gen125_video_pack.h

The idea is to have fewer line to parse in each genX_*.c file.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34276>
2025-04-01 00:03:56 +03:00
Lionel Landwerlin
4fdf5618f9 intel/genxml: add MI_FLUSH_DW to blitter engine
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34276>
2025-04-01 00:03:53 +03:00
Lionel Landwerlin
79a463e40b intel/genxml: define post-sync operations for MI_FLUSH_DW
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34276>
2025-04-01 00:03:50 +03:00
Lionel Landwerlin
d4899b0486 intel/genxml: fixup engine filtering
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34276>
2025-04-01 00:03:47 +03:00
Lionel Landwerlin
04b6eeba63 intel/genxml: add more engine tagging on instructions
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34276>
2025-04-01 00:03:42 +03:00
Lionel Landwerlin
891965a471 intel/genxml: remove ISA fields
Those are for the compiler afaict.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34276>
2025-04-01 00:03:07 +03:00
Caio Oliveira
71ae31dbd8 intel/executor: Allow selecting a device to use
Some checks are pending
macOS-CI / macOS-CI (dri) (push) Waiting to run
macOS-CI / macOS-CI (xlib) (push) Waiting to run
Add a command line option `-d DEVICE` to select
a device either by index or by substring of the
name.

Use `-d list` to print available devices.

Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34267>
2025-03-31 19:20:10 +00:00
Caio Oliveira
9b2b3255e1 intel/executor: Use getopt for command line arguments
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34267>
2025-03-31 19:20:10 +00:00
irql-notlessorequal
5d6b6c376f hasvk: Advertise VK_KHR_maintenance5
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34298>
2025-03-31 16:56:13 +00:00
irql-notlessorequal
b1fe67f118 hasvk: Implement VK calls and formats.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34298>
2025-03-31 16:56:13 +00:00
irql-notlessorequal
f08c87e2b0 hasvk: Implement VkPipelineCreateFlags2KHR support
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34298>
2025-03-31 16:56:13 +00:00
irql-notlessorequal
0d6d23a54f hasvk: Pre-plumbing needed for VK_KHR_maintenance5
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34298>
2025-03-31 16:56:13 +00:00
irql-notlessorequal
255166a349 elk: always write the VUE header
ELK equivalent of !34211, also required to avoid potential rendering errors with hasvk.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34298>
2025-03-31 16:56:13 +00:00
irql-notlessorequal
fe7e0fd4f1 elk: ensure VUE header writes in HS/DS/GS stages
ELK equivalent of !34041, required to avoid potential rendering errors with VK_KHR_maintenance5

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34298>
2025-03-31 16:56:13 +00:00
Hyunjun Ko
ae75376c8f anv: Move rateControlMode to the video session.
Some checks are pending
macOS-CI / macOS-CI (dri) (push) Waiting to run
macOS-CI / macOS-CI (xlib) (push) Waiting to run
Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34250>
2025-03-31 04:25:14 +00:00
Lionel Landwerlin
47cfc77085 anv: expose VK_KHR_maintenance8 support
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33138>
2025-03-29 02:15:19 +00:00
Lionel Landwerlin
7fca7cc721 anv: wire VkAccessFlagBits3KHR flags in internal helpers
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33138>
2025-03-29 02:15:18 +00:00
Lionel Landwerlin
23de5abcb5 anv: enable non uniform texture offset lowering
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33138>
2025-03-29 02:15:18 +00:00
Lionel Landwerlin
4346210ae6 brw: move texture offset packing to NIR
That way we can deal with upcoming non constant values for
VK_KHR_maintenance8.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33138>
2025-03-29 02:15:18 +00:00
Lionel Landwerlin
67ae49dede intel: move lower_texture to brw
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33138>
2025-03-29 02:15:18 +00:00
Lionel Landwerlin
86773b2ba6 brw: don't lower tg4 offsets without LOD
The problem this fixes is currently hidden because of the order in
which we run nir_lower_tex & intel_nir_lower_texture. The issue is
that nir_lower_tex removes the LOD source in some cases and the second
run of nir_lower_tex can add it back.

This is also only needed on Gfx12.5+ if the LOD is present.

Finally move all of the texture lowering to the postprocess phase. No
need to run this multiple times.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33138>
2025-03-29 02:15:18 +00:00
Lionel Landwerlin
b87dccc64c elk: stop using intel_nir_lower_texture
It's not doing anything.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33138>
2025-03-29 02:15:18 +00:00
Caio Oliveira
63224f64cc brw: Remove adjust_block_ips and brw_inst::remove() with defer
Now that the brw_ip_ranges analysis is being used, there's no
need to track start_ip/end_ips in the blocks as they are mutate.  And
also no need to call adjust_block_ips at the end of some passes.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34012>
2025-03-29 00:25:51 +00:00
Caio Oliveira
8057cfc49d brw: Use brw_ip_ranges in liveness analysis
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34012>
2025-03-29 00:25:51 +00:00
Caio Oliveira
a6b0783375 brw: Use brw_ip_ranges in scheduling / regalloc
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34012>
2025-03-29 00:25:51 +00:00
Caio Oliveira
3659d36087 brw: Use brw_ip_ranges in passes
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34012>
2025-03-29 00:25:50 +00:00
Caio Oliveira
10660f5adf brw: Add analysis for block IP ranges
Calculate the IP ranges of the shader as an analysis pass.  This will
later replace the existing tracking of start_ip/end_ip as the blocks are
changed (and the defer/adjust scheme to avoid too much churn when that
happen).

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34012>
2025-03-29 00:25:50 +00:00
Caio Oliveira
fd6045cca9 brw: Track total_instructions in a shader
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34012>
2025-03-29 00:25:50 +00:00
Caio Oliveira
7224b653b5 brw: Use block's num_instructions in scoreboard tests
Stop using the start_ip / end_ip, these are not really important for
those tests.  What the test care was the number of instructions in the
block to check for changes and ensure we can peek at them by index.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34012>
2025-03-29 00:25:50 +00:00
Caio Oliveira
1139ede508 brw: Track num_instructions in a block
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34012>
2025-03-29 00:25:50 +00:00
Caio Oliveira
abe8d35cb8 brw: Remove brw_cfg::dump()
It was used by the pass tests to verify output with TEST_DEBUG=1,
replace it with brw_print_instructions().

The output is slightly different (not printing IP, not reordering the
blocks), we can add those features as we need, but given the usage was
already very reduced, don't bother with that until need arises.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34012>
2025-03-29 00:25:50 +00:00
Dave Airlie
737d66379d anv: expose VK_KHR_video_maintenance2
Reviewed-by: Hyunjun Ko <zzoon@igalia.com>
Reviewed-by: Lynne <dev@lynne.ee>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34204>
2025-03-28 21:18:00 +00:00
Dave Airlie
af560cd680 anv/video: don't write to params if not set.
This should probably be done different, params should probably be considered immutable,
and this should be moved into the command buffer, also this gets set on decode paths as well
which might not make sense.

Reviewed-by: Hyunjun Ko <zzoon@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34204>
2025-03-28 21:18:00 +00:00
Dave Airlie
e4981731be anv/video: convert to common parameters retrieval code
Reviewed-by: Lynne <dev@lynne.ee>
Reviewed-by: Hyunjun Ko <zzoon@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34204>
2025-03-28 21:18:00 +00:00
Michael Cheng
169e7acee1 vulkan: add leaves and ir_leaves sizes to encode for utrace.
Some checks are pending
macOS-CI / macOS-CI (dri) (push) Waiting to run
macOS-CI / macOS-CI (xlib) (push) Waiting to run
Expose number of leaves and ir_leaves to the debug marker for encode.

Signed-off-by: Michael Cheng <michael.cheng@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34200>
2025-03-28 18:25:40 +00:00
Kenneth Graunke
51c67ad7cf brw: Avoid regioning restrictions for u2u16/i2i16 narrowing conversions
Cuts 0.83% of instructions on Alchemist in affected fossil-db shaders
(nearly all of which are in parallel-rdp).

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31833>
2025-03-28 13:40:07 +00:00
Kenneth Graunke
86f8b8860e brw: Use a smaller type for masked sub-32-bit shift values
Cuts 0.14% of instructions on Alchemist in affected fossil-db shaders
(all of which are in parallel-rdp).

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31833>
2025-03-28 13:40:07 +00:00
Kenneth Graunke
2e108afb8c brw: Skip unnecessary UNDEFs for comparisons
For example, SIMD16 W/UW fills an entire REG_SIZE so UNDEF isn't needed.

No change in fossil-db.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31833>
2025-03-28 13:40:07 +00:00