brw: Track total_instructions in a shader

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34012>

src/intel/compiler/brw_analysis.cpp

@@ -80,8 +80,7 @@ brw_idom_tree::dump(FILE *file) const
 brw_register_pressure::brw_register_pressure(const brw_shader *v)
 {
    const brw_live_variables &live = v->live_analysis.require();
-   const unsigned num_instructions = v->cfg->num_blocks ?
-      v->cfg->blocks[v->cfg->num_blocks - 1]->end_ip + 1 : 0;
+   const unsigned num_instructions = v->cfg->total_instructions;
 
    regs_live_at_ip = new unsigned[num_instructions]();
 

src/intel/compiler/brw_cfg.cpp

@@ -85,10 +85,11 @@ append_inst(bblock_t *block, brw_inst *inst)
    inst->block = block;
    block->instructions.push_tail(inst);
    block->num_instructions++;
+   block->cfg->total_instructions++;
 }
 
 cfg_t::cfg_t(brw_shader *s, exec_list *instructions) :
-   s(s)
+   s(s), total_instructions(0)
 {
    mem_ctx = ralloc_context(NULL);
    block_list.make_empty();
@@ -518,6 +519,8 @@ brw_calculate_cfg(brw_shader &s)
 void
 cfg_t::validate(const char *stage_abbrev)
 {
+   unsigned counted_total_instructions = 0;
+
    foreach_block(block, this) {
       foreach_list_typed(bblock_link, successor, link, &block->children) {
          /* Each successor of a block must have one predecessor link back to
@@ -580,6 +583,8 @@ cfg_t::validate(const char *stage_abbrev)
       }
       cfgv_assert(num_instructions == block->num_instructions);
 
+      counted_total_instructions += num_instructions;
+
       brw_inst *first_inst = block->start();
       if (first_inst->opcode == BRW_OPCODE_DO) {
          /* DO instructions both begin and end a block, so the DO instruction
@@ -627,5 +632,7 @@ cfg_t::validate(const char *stage_abbrev)
          cfgv_assert(block->children.length() == 1);
       }
    }
+
+   cfgv_assert(counted_total_instructions == total_instructions);
 }
 #endif

src/intel/compiler/brw_cfg.h

@@ -231,6 +231,8 @@ struct cfg_t {
    struct exec_list block_list;
    struct bblock_t **blocks;
    int num_blocks;
+
+   unsigned total_instructions;
 };
 
 inline bblock_t *

src/intel/compiler/brw_inst.cpp

@@ -983,6 +983,7 @@ brw_inst::insert_before(bblock_t *block, brw_inst *inst)
 
    inst->block = block;
    inst->block->num_instructions++;
+   inst->block->cfg->total_instructions++;
 }
 
 void
@@ -999,7 +1000,9 @@ brw_inst::remove(bool defer_later_block_ip_updates)
    }
 
    assert(block->num_instructions > 0);
+   assert(block->cfg->total_instructions > 0);
    block->num_instructions--;
+   block->cfg->total_instructions--;
 
    if (defer_later_block_ip_updates) {
       block->end_ip_delta--;

src/intel/compiler/brw_lower_scoreboard.cpp

@@ -263,7 +263,7 @@ namespace {
    unsigned
    num_instructions(const brw_shader *shader)
    {
-      return shader->cfg->blocks[shader->cfg->num_blocks - 1]->end_ip + 1;
+      return shader->cfg->total_instructions;
    }
 
    /**

src/intel/compiler/brw_reg_allocate.cpp

@@ -246,7 +246,7 @@ public:
       /* Stash the number of instructions so we can sanity check that our
        * counts still match liveness.
        */
-      live_instr_count = fs->cfg->last_block()->end_ip + 1;
+      live_instr_count = fs->cfg->total_instructions;
 
       spill_insts = _mesa_pointer_set_create(mem_ctx);
 

src/intel/compiler/brw_schedule_instructions.cpp

@@ -716,7 +716,7 @@ brw_instruction_scheduler::brw_instruction_scheduler(void *mem_ctx, const brw_sh
    const unsigned grf_write_scale = MAX_VGRF_SIZE(s->devinfo);
    this->last_grf_write = linear_zalloc_array(lin_ctx, schedule_node *, grf_count * grf_write_scale);
 
-   this->nodes_len = s->cfg->last_block()->end_ip + 1;
+   this->nodes_len = s->cfg->total_instructions;
    this->nodes = linear_zalloc_array(lin_ctx, schedule_node, this->nodes_len);
 
    const struct brw_isa_info *isa = &s->compiler->isa;

src/intel/compiler/brw_shader.cpp

@@ -1009,7 +1009,7 @@ save_instruction_order(const struct cfg_t *cfg)
     * of brw_inst *.  This way, we can reset it between scheduling passes to
     * prevent dependencies between the different scheduling modes.
     */
-   int num_insts = cfg->last_block()->end_ip + 1;
+   int num_insts = cfg->total_instructions;
    brw_inst **inst_arr = new brw_inst * [num_insts];
 
    int ip = 0;
@@ -1025,7 +1025,7 @@ save_instruction_order(const struct cfg_t *cfg)
 static void
 restore_instruction_order(struct cfg_t *cfg, brw_inst **inst_arr)
 {
-   ASSERTED int num_insts = cfg->last_block()->end_ip + 1;
+   ASSERTED int num_insts = cfg->total_instructions;
 
    int ip = 0;
    foreach_block (block, cfg) {