fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2025-12-24 15:20:10 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

brw/coalesce: Prepare brw_opt_register_coalesce for load_reg

Browse source 
v2: Explain the problematic situation a little better in the
comment. Suggested by Caio.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31497>
This commit is contained in:
Ian Romanick 2025-03-11 13:24:04 -07:00 • committed by Marge Bot
parent 15637334ce
commit 1b997c7bcc
1 changed files with 15 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

15
src/intel/compiler/brw_opt_register_coalesce.cpp
View file

@ -240,6 +240,7 @@ brw_opt_register_coalesce(brw_shader &s)
brw_inst **mov = new brw_inst *[MAX_VGRF_SIZE(devinfo)];
int *dst_var = new int[MAX_VGRF_SIZE(devinfo)];
int *src_var = new int[MAX_VGRF_SIZE(devinfo)];
const brw_def_analysis &defs = s.def_analysis.require();
foreach_block_and_inst(block, brw_inst, inst, s.cfg) {
if (!is_coalesce_candidate(&s, inst))
@ -251,6 +252,20 @@ brw_opt_register_coalesce(brw_shader &s)
continue;
}
/* Do not allow register coalescing of a value that was generated by a
* LOAD_REG. Register coalesce works by making the destination of the
* original instruction (in this case the LOAD_REG) be the same as the
* destination of the MOV.
*
* If the MOV result is not a def (due to multiple writes or being used
* outside the body of a loop), this will cause the LOAD_REG to also not
* be a def. That violates the requirement of the LOAD_REG, and it will
* fail validation.
*/
const brw_inst *const def = defs.get(inst->src[0]);
if (def && def->opcode == SHADER_OPCODE_LOAD_REG)
continue;
if (src_reg != inst->src[0].nr) {
src_reg = inst->src[0].nr;